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8.2.7 Cautions
(1) Error on starting timer
An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is
because 16-bit timer register n (TMn) is started asynchronously to the count pulse.
Remark n = 0, 1, 7 to 12
(2) 16-bit capture/compare register setting (in the clear & start mode entered on match between TMn and
CRn0)
Set 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) to a value other than 0000H (a 1-pulse count
operation is disabled when these registers are used as event counters).
(3) Setting compare register during timer count operation
If the value to which the current value of 16-bit capture/compare register n0 (CRn0) has been changed is less
than the value of 16-bit timer register n (TMn), TMn continues counting, overflows, and starts counting again from
0.
If the new value of CRn0 (M) is less than the old value (N), the timer must be reset and restarted after the value
of CRn0 has been changed.
Figure 8-28. Timing After Changing Compare Register During Timer Count Operation
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Remarks 1. N > X > M
2. n = 0, 1, 7 to 12
CHAPTER 8
TIMER/COUNTER FUNCTION
Figure 8-27. Start Timing of 16-Bit Timer Register n
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