Clock Generator; Data Storage - HP 59501A Operating And Service Manual
Hp-ib isolated d/a power supply programmer
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Also See for 59501A:
- Operating manual (16 pages) ,
- Operating and service manual (54 pages)
Table of Contents
4-24
Listen Logic
4-25
The listen logic consists of logic gates which set
or reset the listen flip-flop. When the listen flip-flop is set,
the 59501A is enabled to function as a ''listener". The
listen logic is enabled when the HP-IB is in the command
mode {ATN is LO). If ATN is LO and the 59501A's listen
address is decoded (ADDRESS is HI), the listen flip-flop is
set {U12-3 goes HI) when ACDS is received from the
acceptor handshake circuit. Note that only a portion of the
listen address is specified by the ADDRESS signal. In addi¬
tion, HP-iB data input line DI07 must be H! and line DI06
must be LO to specify that a listen address is present on the
bus. When the listen flip-flop is set, driver Q14 turns the
LISTENING indicator on. Also, with the listen flip-flop
set, the clock generator will be enabled when the bus is
placed in the data mode (ATN goes HI). The clock generator
produces clock pulses which gate the data sequencer storing
the data characters received on the bus (see paragraph 4-28).
4-26
If the ATN line goes LO again (command mode)
and an unlisten command (ASCI I ''?") is placed on the bus,
the listen flip-flop is reset (U1 2-3 goes LO) when ACDS is
received, turning off the LISTENING indicator, inhibiting
the clock generator, and resetting the data sequencer. Note
that the interface clear (TFC) signal also resets the listen
flip-flop. The IFC signal is used by the controller to ter¬
minate activity on the bus.
4-27
Clock Generator
4-28
The clock generator is enabled when the listen
flip-flop is set (U12-3 is HI) and the HP-IB is in the data
mode (ATN is HI), When enabled, the clock generator
produces a clock pulse (approximately 4/Jsec wide) on the
leading edge of the ACDS signal received from the acceptor
handshake circuit. The clock pulse gates the data storage
sequencer which loads the data on lines DTUT-DTD^ into
the appropriate storage latch (see paragraph 4-32).
4'29
Isolators
4-30
Data bits DI01-DI04, the sequencer clock signal,
and the sequencer reset signal are applied through inverter
drivers (U13, U14) to photo-isolators {U15, U16, U17).
The inputs to the isolators are referenced to HP-IB signal
ground
while the outputs are referenced to power supply
ground
^.
With these input and output connections,
up to 600Vdc isolation is provided between the HP-IB data
input lines and the 59501A output terminals. Each dual
isolator 1C package contains a pair of light emitting diodes
and integrated photon detectors. The isolated DI01-DI04
data bits are routed to the appropriate data 1 storage latches
while the isolated clock and reset signals are sent to the data
storage sequencer.
4-31
Data Storage
4-32
The data storage circuits consist of data storage 1
latches, data storage 2 latches, and the data storage sequencer
circuit. The circuits store a data word which consists of
four characters. The characters are transferred from the bus
one at a time with the range character transferred first
followed by the three magnitude characters. Each character,
bits DI04 (MSB) - D101 (LSB), is transferred into data
storage 1 during the accompanying 3-wire handshake cycle.
After the fourth character is transferred into data storage 1,
all four characters (data word) are automatically loaded into
the data storage 2 latches. The timing sequence for the data
word transfer is provided in Figure 4-3,
4-33
The leading edge of each ACDS pulse generates a
clock pulse which gates the data storage sequencer, Initially,
the data shift register (U25) in the data storage sequencer
is reset and the data input (U25-7) is a HI level. The timing
sequence that occurs during the transfer of a data word is
described below (Refer to Figure 4-3).
a. Cycle 1. The first clock pulse produces a negative
4-4
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