Detailed Circuit Description; Power-On Preset - HP 59501A Operating And Service Manual
Hp-ib isolated d/a power supply programmer
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Also See for 59501A:
- Operating manual (16 pages) ,
- Operating and service manual (54 pages)
Table of Contents
4-13
The output amplifier includes overvoltage protec¬
tion and current limiting circuits to protect the 59501A
and user equipment. In addition, a turn-on/turn-off control
circuit clamps the output terminals at a low level when
power is turned-on or off.
The purpose of this circuit is to
prevent transients at power turn-on and turn-off from
affecting the output of the 59501A and also prevent random
programming of a power supply prior to receipt of valid
programming data.
4-14
The front panel ZERO ADJUST allows a zero
(:.t250mV) output adjustment. The D/A FULL SCALE
ADJUST allows setting the maximum 59501A output
(±5%) in the high and low ranges,
4-15
When the 59501A is used as a power supply pro¬
grammer, the POWER SUPPLY FULL SCALE ADJUST
potentiometers (COARSE and FINE) allow the user to set
the maximum power supply output when the 59501A is
programmed to its maximum output. Power supply
programming is accomplished by connecting the 59501 A's
output terminals to the power supply's voltage program¬
ming terminals (see Section IH).
4-16
DETAILED CIRCUIT DESCRIPTION
4-17
The following paragraphs describe, in more detail,
the operation of the 59501 A's major circuits. Note that
only those circuits not covered in sufficient detail in the
preceding overall description, will be described. Throughout
this discussion refer to the fold-out schematic diagram at the
rear of this manual.
4-18
Power-On Preset
4-19
When power is initially applied, the preset circuit
(Q3, U1, U5) generates a LO level pulse (PON) which resets
the listen flip-flop (acceptor handshake), and the data storage
sequencer. Thus, the preset circuit ensures that the 59501A
is not a "listener" and is properly initialized when power is
applied.
4-20
Address Comparator
4-21
The address comparator consists of 5-bit comparator
U3 and the address switches on the rear of the supply. When
the levels on data lines DfOi-DIOS match the address switch
settings, U3 provides a HI level ADDRESS output to the
listen logic. Note that the schematic illustrates the address
switches set to the suggested listen address of
4-22
Acceptor Handshake
4-23
The acceptor handshake circuit implements the
3-wire handshake cycle that occurs with each command or
data character received on the bus data lines DI01-DI07.
Unrecognized command characters (e. g., talk address) will
be ignored but the handshake cycle between the controller
and the 59501A will occur anyway. The 3-wire handshake
lines are designated DAV (data valid), NRFD (not ready
for data), and f^AC (data not accepted). The acceptor
handshake circuit is enabled when the bus is in the command
mode (ATN is LO) or if the 59501A is in the listen mode
(listen flip-flop set) and ATN is HI (data mode). For either
of the above conditions, the output of NAND gate U8-3
goes HI and NAND gate U5-6 goes LO enabling the acceptor
handshake circuits. Figure 4-2 illustrates the 3-wire hand¬
shake cycle timing sequence for each character received by
the 59501A in the command and data modes.
Tq: Initially the NRFD signal (Jl-7) is HI (59501A is
ready for data) and the
signal (J1-8) is LO (data not
accepted). Also DAV (J1-6) is HI (data on bus is not valid).
T^: The source (assume controller) puts a character on
the bus and indicates that the character is valid by setting
DAV (J1-6) LO.
T2-
After a delay of approximately l^sec NRFD goes
LO (59501A not ready for data). Also, accept data signals,
ACDS {U11-13) and ACDS (011-4), are generated.
a. If the HP-IB is in the command mode (ATN LO),
the ACDS signal gates a recognized command character
(59501 A's listen address
or unlisten command "?")
which sets or resets the listen flip-flop (see paragraph 4-24).
b. if the HP-IB is in the data more (ATN HI) and the
59501A had previously been addressed to listen, the ACDS
signal gates the clock generator, producing a clock pulse
which loads the data character (range or magnitude) present
on bus lines (DTo1-DT04) into the appropriate storage
register (see paragraph 4-31).
T^: After approximately 1 5jUsec, the trailing (positive)
edge of the ACDS (U11-4) signal produces a negative pulse
{U1 2-8) which sets the DAC F/F (U8-11 goes HI and U9-6
goes LO). With U9-6 LO, NDAC (J1-8) goes HI indicating
that the 59501A has accepted the data.
The controller, sensing NDAC HI, sets DAV HI
indicating that the data on the bus is no longer valid.
Tpi When'DAV goes HI, the DAC F/F is reset (U9-6
goes Hi and U8-11 goes LO) causing
{J1-8) to go LO
(data not accepted). Also, with D^V HI, NRFD goes HI
indicating that the 59501A is ready for the next character,
T
0
: With NRFD HI, the controller sets DAV LO and
the next character is transferred (T2 through T5).
4-3
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