Register Cher, Iowr, Tcr, Mcra, Mcrb And Rcr - Fujitsu MB88121 Application Note

Register CHER decides whether the data, read from the chip select area, is saved in the

built-in cache or not. For the communication controller the cache function is disabled through

register ICHCR. MCU accesses the communication controller directly without cache

intervention.

;===================================================

; 4.8 Enable/Disable I-CACHE

;===================================================

#set

C1024

#set

C2048

#set

C4096

#set

CACHE

#set

CACHE_SIZE

; This is a general CACHE-Enable. By the configuration of the external bus

;

it is selected, which chip select area should be cached

;====================================

; 4.9.8 Enable CACHE for chip select

;====================================

; select which chip select area is used with Cache functionality

#set

CHEENA

B'11111111

;

||||||||__ CHE0 bit, CS0 area

;

|||||||___ CHE1 bit, CS1 area

;

||||||____ CHE2 bit, CS2 area

;

|||||_____ CHE3 bit, CS3 area

;

||||______ CHE4 bit, CS4 area

;

|||_______ CHE5 bit, CS5 area

;

||________ CHE6 bit, CS6 area

;

|_________ CHE7 bit, CS7 area

;=======================================

; 6.6.14 Enable CACHE for selected CS

;=======================================

LDI

LDI

ORB

;=========================================

; 6.7 I-cache ON/OFF

;=========================================

LDI

#0x03E7, R1

LDI

#0x06, R2

STB

R2, @R1

© Fujitsu Microelectronics Europe GmbH

Interfacing MB91460 TO MB88121

Chapter 3 Software

1

; CACHE Size: 1024 BYTE

2

; CACHE Size: 2048 BYTE

3

; CACHE Size: 4096 BYTE

OFF

; I-CACHE is disabled

C4096

; select size of CACHE

;enable cache for each CS

#0x0681, R3

; cache enable register CHER

#CHEENA, R2

R2, @R3

; Cache control register ICHCR

; disable cache

;

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MCU-AN-300016-E-V10