Control/Status Registers B (Dmacb0-4); Table 2-2: Dmacbn - Fujitsu FR Series Application Note
32-bit direct memory access
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2.3.2 Control/Status Registers B (DMACB0-4)
These registers control the operation of the corresponding DMAC channel.
Bit
Name
Explanation
No.
31
...
TYPE
Transfer Type
30
29
...
MOD
Transfer Mode
28
27
...
WS
Data Width
26
Source
25
SADM
Address Count
Mode Select
Destination
24
DADM
Address Count
Mode Select
Transfer Count
23
DTCR
Register
Reload
Source
Address
22
SADR
Register
Reload
Destination
Address
21
DADR
Register
Reload
Error Interrupt
20
ERIE
Request
Enable
End Interrupt
19
Request
EDIE
Enable
5
Source and destination address register reload feature is only valid if the Transfer count register
reload feature is enabled (DTCR = 1).
© Fujitsu Microelectronics Europe GmbH
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
Initial
Value
Value
0,0
0,0
0,0
0
0
0
0
5
0
5
0
0
Table 2-2: DMACBn
- 11 -
Operation
0,0
2-cycle transfer
Fly-by: External Memory --> external
0,1
I/O transfer
Fly-by: external I/O --> external
1,0
memory transfer
Setting disabled
1,1
0,0
Block/Step transfer
0,1
Burst transfer
1,0
Demand transfer
1,1
Setting disabled
Byte transfer
0,0
0,1
Half-word transfer
1,0
Word transfer
1,1
Setting disabled
0
Increment transfer source address
1
Decrement transfer source address
Increment transfer destination
0
address
Decrement transfer destination
1
address
Transfer count register reloading
0
disabled
Transfer count register reloading
1
enabled
Source address register reloading
0
disabled
Source address register reloading
1
enabled
Destination address register reloading
0
disabled
Destination address register reloading
1
enabled
0
Error Interrupt Request enabled
1
Error Interrupt Request disabled
0
End Interrupt Request enabled
1
End Interrupt Request disabled
MCU-AN-300059-E-V11
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