Table 3.6-3 Main Clock Mode Operation Start Conditions And Oscillation Stabilization Delay Time - Fujitsu F2MC-8L Series Hardware Manual
8-bit microcontroller
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Also See for F2MC-8L Series:
- Hardware manual (131 pages) ,
- Application note (14 pages) ,
- Getting started (15 pages)
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CHAPTER 3 CPU
Oscillation stabilization delay time after a reset
The oscillation stabilization delay time (the WT1 and WT0 initial values) taken after a reset is
selected by option settings.
The product with the power-on reset function requires the oscillation stabilization delay time
after resets in subclock mode, a power-on reset, or an external reset to cancel the stop mode.
The product without the power-on reset function requires the oscillation stabilization delay time
only after a software or watchdog reset in subclock mode.
Table 3.6-3 shows the relationships between main clock mode operation start conditions and
oscillation stabilization delay time.
Table 3.6-3 Main clock Mode Operation Start Conditions and Oscillation Stabilization Delay Time
Main clock mode
operation start
conditions
Selection of oscillation
stabilization delay time
Product with power-on
reset function
Product without
power-on reset
function
Y: Take oscillation stabilization delay time.
N: Do not take oscillation stabilization delay time.
*1: System clock select bit in the system clock control register
*2: Oscillation stabilization delay time select bits in the system clock control register
Subclock Oscillation Stabilization Delay Time
When waking up from sub-stop mode (stopping subclock oscillation) to sub-RUN mode (starting
subclock oscillation), the CPU takes a certain period of subclock oscillation stabilization delay
time (2
The subclock oscillation stabilization delay time is the time from when the watch prescaler starts
operation in the cleared state to when it causes an overflow.
The subclock oscillation stabilization delay time is required after the power is turned on. Before
switching to subclock mode after turning the power on, therefore, take the subclock oscillation
stabilization delay time by means of software.
72
In subclock mode
Turning
the
power
External
on
reset
Y
Y
N
N
15
/F
L, where F
is subclock oscillation).
C
CL
Wake-up from of
main-stop mode
Software
or
External
watchdog
reset
reset
Optional
Y
Y
Switching from
subclock mode to
main clock mode
External
(SYCC: SCS*
interrupt
SYCC : WT1, WT0*
Y
Y
N
Y
1
= 1)
2
Y
Y
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