Non-Maskable Interrupt (Nmi) - Fujitsu F2MC-FR Series Application Note

Bit

Bit

No.

Name

7

MHALTI

6-5

-

4

LVL4

4-0

LVL4-0

Non-maskable interrupt is available in few derivatives. If the signal on the NMIX pin is at

LOW level for 1 CLKP cycle then NMI is generated. In order to clear the NMI the MHALTI

flag of HRCL register needs to be cleared after the level of the signal appearing on the NMIX

pin changes to HIGH.

MCU-AN-300055-E-V10

INTERRUPTS

Chapter 2 Interrupt Types

Initial

Description

Value

This bit is set to 1 in case of Non-maskable Interrupt.

0

It is also set to 1 in case of a peripheral interrupt with the higher

priority than specified with LVL bits.

-

-

1

These bits define the interrupt level at which a hold request

cancel request is generated for the bus master. For e.g. if the

LVL bits are configured as 20 (b'10100) then all the peripherals

whose interrupt level is configured from 16 to 19 and the NMI

can generate hold request cancel request.

11111

It should be noted that LVL4 bit is read-only. Since the power-on

reset value of this bit is 1, if the value of 0x0F is attempted to be

written to LVL bits then the actual LVL value would become

0x10.

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