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SONY,
CXD1 160AP/AQ
(2)
30bit
delay
mode
By
turning
DIO
;
of
the
microcomputer
interface
R mode
to
'L',
30bit
delay
mode
is
set
on.
To
realize
this,
the following
hardware
conditions
should
be
met.
LRCK2128KCK=256ACK
That
is.
512
fsMP
256
fsMp
30bit
delay
mode
can
perform
the delay
of
DI/DO
register
upper
30bit.
DIHIj,
E,
s
E,,
E..
Dl
L
Bit
Bm
E
3
E
=
D
H
F,,
t*,
—tti
F,<
DOL
Fi,
F,<
F,
Fj
x
x
Hera,
DOL
register
lower
2bit
are
at don't care,
DIL
register
lower
2bit
contain
0.
Timing
(LRCK=128KCK
Example)
126127
29 30
31
32
61 62 63
64
93
94 95
96
125126127
kck
nruTJ
rLnrLru
nnjuu
jump;
jltloju
KSL PI
PI
_PL
_pl
-PL
XRAS
_PL_
xcas
i
—
u
sir
~u
ru
—
u
nr
XWSCXWE1
i
A7-A5
ECX
JZOC
L_
3XO
A4-60
xzran
xuxxod:
hieds
m.
do
a a
u>
n
Dl
oo
PJECX
:
i(29K^n(oi
a
-Calculating operations
-
Should
the
data
written
iast
between
cycle
to
62
in
DO
register
be
at
CHl(n), data
CH1(n-r) from
the
previous cycle
126 up
to
the
present
cycle
61
in
Dl register
can
perform
read.
Similarly,
should data
written
last
between
cycle
64 and
last
cycle
1
in
DO
register
be
at
CH(n), data CH2(n-r)
between
cycle
62
to
125
in
Dl
register
can
perform
read.
-
134-
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