Dc Remote Channel Adapter (950-9716); Tone Remote Lotl Channel Adapter (950-9719); Individual Channel Dtmf Ani Decoder (950-9722) - ZETRON 4010 Service Manual
Radio dispatch console
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Also See for 4010:
- Installation and programming (138 pages) ,
- Spec sheet (4 pages) ,
- Programming manual (117 pages)
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U17 interface to the crystal Y1 and along with U14 and U16B form the 2175Hz oscillator. U17 also
provides the 3.48MHz clock for the audio delay circuit of sheet 2. U18B and U15 form a filter and
amplifier for the guard tone. R47 provides the amplitude adjustment for the guard tone.
On sheet 2, the patch bus and mic bus go to a continuously variable slope delta (CVSD) modulator
U12 and U13. The DIGOUT of the modulator is the digitized audio which goes to a buffer, U8, and
is enabled to the DRAM input by /OE. The same DRAM data goes to the DATA input of U5 and
U9, the CVSD demodulators. AOUT of U5 and U9 is the delay audio output, which is filtered and
put back on the MIC OUT and PAT OUT signals of J1. The MIC delayed audio can be bypassed by
activating the audio switch U4A, which the main processor has under software control. This switch
is activated when using the Phone Patch Card. The jumpers JP2 and JP3 enable the delay circuit to
be bypassed for either bus.
The cycle rate and synchronous signals for the audio delay circuit are generated by the PAL, U7.
U16A divides the 3.28MHz clock by 8 and forms the master clock for the PAL's internal state
machine. The PAL generates seven states for circuit timing at 62KHz cycle rate. JP1 selects the
audio time delay options for the PAL at .25, .50, .75, and 1.0 seconds. The time settings determines
when the CLR (clear) signal is generated to restart the address counters U2 and U11. The multi-
plexers U3 and U10 are interleaved by /OE for the RAS and CAS addresses of the 4Meg DRAM,
U6. The stored digitized data from RAM is clocked out to U5 and U9 in the first part of the clock
cycle to form the delayed audio output. The received audio data from U12 and U13 is stored in RAM
on the second part of the clock cycle.
DC REMOTE CHANNEL ADAPTER (950-9716)
The DC Remote daughter card adds the DC current control to the channel it is installed on. The card
is capable generating a current source from zero to 15 milliamps in 0.5 milliamp increments. The
card also provides the line operator transmit light (LOTL) indication if the channel is busy to the
operator. The schematic for the card is 008-9380.
The interface to the line transformer's center taps is LOOP+ and LOOP- and the external line
connections are BSY+ and BSY-. The signals associated with the DC current control is CURRENT*,
CLEAR, HOLD and NEG-POL. The steady state levels provide a '1' at U4A-3 and keeps Q1 turned
on. This causes current to flow in U5 and applies voltage at U5-4. This voltage is generated by the
150Vdc through R9 and regulated by the CR6 Zener to 6Vdc. With voltage applied, the inputs to
U6A and U6B are both at '1'. This causes the clock and clear inputs of U7A and U7B to be in the
inactive state. U7A and U7B form a 32 bit counter.
The CLEAR signal will turn off Q1 and the output of U5. The inputs of U6A and U6B will then start
to discharge their input capacitors through their series 330K resistors and R11. The CLEAR signal
will be maintained longer than the RC time constant formed by C8, R10, and R11 to generate a reset
signal to U7.
When the HOLD signal is low, the CURRENT* signal enabled to turn off Q1. CURRENT* is a
series of pulses which allows the input of U6B to discharge through R12 and R11 but are shorter in
duration than the time required to trigger U6A. The U6B signal will generate a series of clock pulse
Model 4010 Radio Dispatch Console Service Manual
to the U7 counter. The count of zero is no current and the maximum count of 30 is for a 15 mA out-
put current. The binary count goes to the resistor R/2R network RP1 and to the feedback amplifier
U8B and Q2. The potentiometer R15 is adjusted so each binary count produces 0.25 mA of collector
current through Q2 and the LOOP- signal when connected to a load through the output transformer.
The relay K1 is driven by the NEG-POL signal to reverse the direction of current flow through the
load.
The power source for the current generator is PS1, which is a 12Vdc to 150Vdc switching regulator.
The 150V source goes through the blocking diode CR10 and relay K1 to the LOOP+ connection.
The BSY+ and BSY- signals come from the radio line inputs. If the line is in use by another parallel
console, there will be a voltage potential across the signal pair. This voltage will charge C4 through
R6. The diode bridge will connect the charge of C1 across the input of U2. The CURRENT* signal
is a low going pulse which turns on U3 collector and dumps the C1 charge through U2 input. The
collector of U2 produces a high at U1A-2 and the trailing edge of CURRENT* will latch the U1A-2
state into U1A. This BSY '1' state will cause the LOTL* signal at J1 to go low and light the LOTL
LED on the rear panel.
When the radio line is no longer in use, the BSY lines have no voltage and C1 is discharged. The
next CURRENT* pulse will clock a '0' into U1A returning LOTL* high. Jumper JP1 disables the
LOTL circuit in the B position.
TONE REMOTE LOTL CHANNEL ADAPTER (950-9719)
The Tone LOTL Daughter Board will generate a LOTL signal if a tone remote parallel console is
using the radio line. The schematic for the board is 008-9450. The board is the same as 950-9722
with the DTMF decoder circuit not installed.
From the Dual Channel Card's daughter board connector J1, the receive audio (RX) signal goes to an
internal amplifier input AIN of U5. U5 is a band pass, switched capacitor filter that is tuned for a
center frequency of 2175Hz at the CMOS and RC inputs. The C8, R15, R14, and R16 form the tun-
ing circuit. When a high level guard tone at 2175Hz is passed through the filter, the amplifier U4A
forms a peak detector to the input of U3A. The holding capacitor C5 will hold the detected peaks and
provide a steady-state signal at U3B. With JP1 in position A, the signal will drive Q1 and the LOTL
LED on the back panel and the feedback FET Q2. Q2 will lower the impedance in the input amplifier
U4A and increase the gain. The gain will increase 30dB so the amplifier will keep locked on the low
level guard tone signal. The LOTL* output to the channel card will remain low until the guard tone
signal is dropped.
INDIVIDUAL CHANNEL DTMF ANI DECODER (950-9722)
The Tone LOTL/DTMF Decoder Daughter Board will decode any DTMF signals and generate a
LOTL signal if a tone remote parallel console is using the radio line. The schematic for the board is
008-9535.
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