Chapter 12 - CB Fail Protection
4.4
CIRCUIT BREAKER FAIL LOGIC - PART 4
LatchATripResetIncomp
Latch3PhTripResetIncomp
LatchNonITripResetIncomp
CB1 ZCD State A
WI INFEED A
TripStateA CB1
CB1 Fail1 Status
Enabled
CB1 Fail1 Timer
TripStateA
CB1 Fail2 Status
Enabled
CB1 Fail2 Timer
ZCD StateSEF
TripStateSEF
CB1 Fail1 Status
Enabled
CB1 Fail1 Timer
TripStateSEF
CB1 Fail2 Status
Enabled
CB1 Fail2 Timer
V00742
Figure 200: Circuit Breaker Fail logic - part 4
Note:
This diagram shows only phase-A for the first CB (CB1) of a dual-CB device. The diagrams for phases B and C and for the
second CB (CB2) follow the same principle and are not repeated here.
354
1
&
t
0
t
&
0
&
t
0
t
&
0
From phase B equivalent
From phase C equivalent
1
&
1
&
1
&
1
&
1
834
CB1 Fail1 Trip
298
1
CB1 Fail Alarm
1
835
CB1 Fail2 Trip
1
1672
CB1 Fail1 Trip A
1675
1
CB1 Fail2 Trip A
P446SV-TM-EN-1
P446SV