Hitachi SH7750 series Manuals

Overview

51

SH7750 Series (SH7750, SH7750S, SH7750R) Features

51

Table 1.1 SH7750 Series Features

53

Block Diagram

59

Figure 1.1 Block Diagram of SH7750 Series Functions

59

Figure 1.2 Pin Arrangement (256-Pin BGA)

60

Pin Arrangement

60

Figure 1.3 Pin Arrangement (208-Pin QFP)

61

Figure 1.4 Pin Arrangement (264-Pin CSP)

62

Pin Functions

63

Data Formats

91

Programming Model

91

Register Configuration

92

Figure 2.2 CPU Register Configuration in each Processor Mode

94

Index

94

Memory-Mapped Registers

102

Data Format in Registers

103

Data Formats in Memory

103

Figure 2.1 Data Formats

103

Figure 2.5 Data Formats in Memory

103

Processor States

104

Figure 2.6 Processor State Transitions

105

Processor Modes

105

Memory Management Unit (MMU)

107

Overview

107

Figure 3.2 MMU-Related Registers

111

Register Descriptions

111

Address Space

114

Physical Address Space
114
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
115
Figure 3.4 P4 Area
116
External Memory Space
117
Figure 3.5 External Memory Space
117
Virtual Address Space
118
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
118
On-Chip RAM Space
119
Address Translation
119
Single Virtual Memory Mode and Multiple Virtual Memory Mode
120
Address Space Identifier (ASID)
120

TLB Functions

121

MMU Functions

128

MMU Hardware Management
128
MMU Software Management
128
MMU Instruction (LDTLB)
128
Hardware ITLB Miss Handling
129
Figure 3.12 Operation of LDTLB Instruction
129
Avoiding Synonym Problems
130

MMU Exceptions

131

Memory-Mapped TLB Configuration

137

ITLB Address Array
138
Figure 3.13 Memory-Mapped ITLB Address Array
138
ITLB Data Array 1
139
Figure 3.14 Memory-Mapped ITLB Data Array 1
139
ITLB Data Array 2
140
UTLB Address Array
140
Figure 3.15 Memory-Mapped ITLB Data Array 2
140
Figure 3.16 Memory-Mapped UTLB Address Array
141
UTLB Data Array 1
142
Figure 3.17 Memory-Mapped UTLB Data Array 1
142
UTLB Data Array 2
143
Figure 3.18 Memory-Mapped UTLB Data Array 2
143

Caches

145

Overview

145

Features
145
Table 4.1 Cache Features (SH7750, SH7750S)
145
Table 4.2 Cache Features (SH7750R)
145
Register Configuration
146
Table 4.3 Features of Store Queues
146
Table 4.4 Cache Control Registers
146

Figure 4.1 Cache and Store Queue Control Registers

147

Register Descriptions

147

Operand Cache (OC)

149

Configuration
149
Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S)
150
Figure 4.3 Configuration of Operand Cache (SH7750R)
151
Read Operation
153
Write Operation
154
Write-Back Buffer
155
Write-Through Buffer
155
Figure 4.4 Configuration of Write-Back Buffer
155
Figure 4.5 Configuration of Write-Through Buffer
155
RAM Mode
156
OC Index Mode
157
Coherency between Cache and External Memory
157
Instruction Cache (IC)
158
Configuration
158
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)
159
Figure 4.7 Configuration of Instruction Cache (SH7750R)
160
Read Operation
161
IC Index Mode
161

Memory-Mapped Cache Configuration (SH7750, SH7750S)

162

IC Address Array
162
IC Data Array
163
Figure 4.8 Memory-Mapped IC Address Array
163
OC Address Array
164
Figure 4.9 Memory-Mapped IC Data Array
164
OC Data Array
165
Figure 4.10 Memory-Mapped OC Address Array
165

Figure 4.11 Memory-Mapped OC Data Array

166

IC Address Array
167
IC Data Array
168
Figure 4.12 Memory-Mapped IC Address Array
168
OC Address Array
169
Figure 4.13 Memory-Mapped IC Data Array
169
OC Data Array
170
Figure 4.14 Memory-Mapped OC Address Array
170
Summary of the Memory-Mapping of the OC
171
Figure 4.15 Memory-Mapped OC Data Array
171

Memory-Mapped Cache Configuration (SH7750R)

166

Store Queues

172

SQ Configuration
172
SQ Writes
172
Transfer to External Memory
172
Figure 4.16 Store Queue Configuration
172
SQ Protection
174
Reading the Sqs (SH7750R Only)
174
SQ Usage Notes
175

Exceptions

177

Overview

177

Features
177
Register Configuration
177
Table 5.1 Exception-Related Registers
177

Figure 5.1 Register Bit Configurations

178

Register Descriptions

178

Exception Handling Functions

179

Exception Types and Priorities

180

Figure 21.3 H-UDI Reset

180

Table 5.2 Exceptions

180

Exception Flow

182

Description of Exceptions

185

Resets
186
Table 5.3 Types of Reset
187
General Exceptions
191
Interrupts
205
Priority Order with Multiple Exceptions
208

209

210

211

211

211

215

218

Floating-Point Exceptions

219

Graphics Support Functions

220

Execution Environment

223

Instruction Set

223

Addressing Modes

225

Table 7.1 Addressing Modes and Effective Addresses

228

Instruction Set

229

Table 7.2 Notation Used in Instruction List

229

Table 7.3 Fixed-Point Transfer Instructions

230

Table 7.4 Arithmetic Operation Instructions

233

Table 7.5 Logic Operation Instructions

234

Table 7.6 Shift Instructions

235

Table 7.7 Branch Instructions

236

Table 7.8 System Control Instructions

237

Table 7.9 Floating-Point Single-Precision Instructions

239

Table 7.10 Floating-Point Double-Precision Instructions

240

Table 7.11 Floating-Point Control Instructions

240

Table 7.12 Floating-Point Graphics Acceleration Instructions

241

Pipelines

243

Pipelining

243

Figure 8.1 Basic Pipelines

244

Figure 8.2 Instruction Execution Patterns

249

Parallel-Executability

250

Table 8.1 Instruction Groups

250

Execution Cycles and Pipeline Stalling

254

Table 8.2 Parallel-Executability

254

Figure 8.3 Examples of Pipelined Execution

259

Table 8.3 Execution Cycles

261

Overview

271

Power-Down Modes

271

Register Descriptions

274

Deep Sleep Mode

280

Transition to Deep Sleep Mode
280
Exit from Deep Sleep Mode
281

Sleep Mode

280

Transition to Sleep Mode
280
Exit from Sleep Mode
280

Standby Mode

281

Transition to Standby Mode
281
Table 9.4 State of Registers in Standby Mode
281
Exit from Standby Mode
282
Clock Pause Function
282

Module Standby Function

283

Hardware Standby Mode (SH7750S, SH7750R Only)

285

STATUS Pin Change Timing

286

Overview

297

Features
297

Section 10 Clock Oscillation Circuits

297

Overview of CPG

299

Block Diagram of CPG
299
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
299
Figure 10.1 (2) Block Diagram of CPG (SH7750R)
300
CPG Pin Configuration
302
CPG Register Configuration
302
Table 10.1 CPG Pins
302
Table 10.2 CPG Register
302

Clock Operating Modes

303

Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)

303

Table 10.3 (2) Clock Operating Modes (SH7750R)

303

CPG Register Description

304

Changing the Frequency

307

Output Clock Control

308

Overview of Watchdog Timer

309

WDT Register Descriptions

310

Watchdog Timer Counter (WTCNT)
310
Table 10.5 WDT Registers
310
Watchdog Timer Control/Status Register (WTCSR)
311
Notes on Register Access
313

Using the WDT

313

Standby Clearing Procedure
313
Figure 10.3 Writing to WTCNT and WTCSR
313
Frequency Changing Procedure
314
Using Watchdog Timer Mode
314
Using Interval Timer Mode
315

Figure 10.4 Points for Attention When Using Crystal Resonator

315

Notes on Board Design

315

Figure 10.5 Points for Attention When Using PLL Oscillator Circuit

316

Overview

317

Section 11 Realtime Clock (RTC)

317

Register Descriptions

321

64 Hz Counter (R64CNT)
321
Second Counter (RSECCNT)
321
Minute Counter (RMINCNT)
322
Hour Counter (RHRCNT)
322
Day-Of-Week Counter (RWKCNT)
323
Day Counter (RDAYCNT)
324
Month Counter (RMONCNT)
324
Year Counter (RYRCNT)
325
Second Alarm Register (RSECAR)
326
Minute Alarm Register (RMINAR)
326
Hour Alarm Register (RHRAR)
327
Day-Of-Week Alarm Register (RWKAR)
327
Day Alarm Register (RDAYAR)
328
Month Alarm Register (RMONAR)
329
RTC Control Register 1 (RCR1)
329
RTC Control Register 2 (RCR2)
331
RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR)
333
(SH7750R Only)
333

335

339

339

341

Section 12 Timer Unit (TMU)

341

Register Descriptions

345

Timer Output Control Register (TOCR)
345
Timer Start Register (TSTR)
346
Timer Start Register 2 (TSTR2) (SH7750R Only)
347
Timer Constant Registers (TCOR)
348
Timer Counters (TCNT)
348
Timer Control Registers (TCR)
349
Input Capture Register (TCPR2)
353

Operation

354

Figure 12.7 Operation Timing When Using Input Capture Function

358

Interrupts

358

Usage Notes

359

Overview

361

Features
361
Block Diagram
363
Figure 13.1 Block Diagram of BSC
363
Pin Configuration
364
Table 13.1 BSC Pins
364
Register Configuration
368
Table 13.2 BSC Registers
368
Overview of Areas
369
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space
369
Table 13.3 External Memory Space Map
370
Figure 13.3 External Memory Space Allocation
371
PCMCIA Support
372
Table 13.4 PCMCIA Interface Features
372
Table 13.5 PCMCIA Support Interfaces
373

Section 13 Bus State Controller (BSC)

361

Register Descriptions

376

Operation

420

Address Pins (64-Bit Bus Width, AMX2-AMX0 = 011, AMXEXT = 0)

466

Table 13.17 Cycles for Which Pipeline Access Is Possible

481

Burst ROM Interface
491
PCMCIA Interface
494
Table 13.18 Relationship between Address and CE When Using PCMCIA Interface
496
MPX Interface
505
Byte Control SRAM Interface
523
13.3.10 Waits between Access Cycles
528
13.3.11 Bus Arbitration
530
13.3.12 Master Mode
533
13.3.13 Slave Mode
534
13.3.14 Partial-Sharing Master Mode
535
13.3.15 Cooperation between Master and Slave
536
13.3.16 Notes on Usage
537

Overview

539

Features
539
Block Diagram (SH7750, SH7750S)
542
Pin Configuration (SH7750, SH7750S)
543
Table 14.1 DMAC Pins
543
Register Configuration (SH7750, SH7750S)
544
Table 14.2 DMAC Pins in DDT Mode
544
Table 14.3 DMAC Registers
544

Section 14 Direct Memory Access Controller (DMAC)

539

Register Descriptions (SH7750, SH7750S)

546

Operation

560

Examples of Use

594

On-Demand Data Transfer Mode (DDT Mode)

595

Operation
595
Pins in DDT Mode
597
Transfer Request Acceptance on each Channel
600
Notes on Use of DDT Module
621

Configuration of the DMAC (SH7750R)

624

Register Descriptions (SH7750R)

629

Operation (SH7750R)

636

Usage Notes

641

Overview

643

Section 15 Serial Communication Interface (SCI)

643

Register Descriptions

647

Operation

671

SCI Interrupt Sources and DMAC

701

Table 15.12 SCI Interrupt Sources

701

Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data

702

Usage Notes

702

Overview

707

Section 16 Serial Communication Interface with FIFO (SCIF)

707

Register Descriptions

711

Receive Shift Register (SCRSR2)
711
Table 16.2 SCIF Registers
711
Receive FIFO Data Register (SCFRDR2)
712
Transmit Shift Register (SCTSR2)
712
Transmit FIFO Data Register (SCFTDR2)
713
Serial Mode Register (SCSMR2)
713
Serial Control Register (SCSCR2)
715
Serial Status Register (SCFSR2)
718
Bit Rate Register (SCBRR2)
724
FIFO Control Register (SCFCR2)
725
FIFO Data Count Register (SCFDR2)
728
Serial Port Register (SCSPTR2)
729
Line Status Register (SCLSR2)
734

Operation

735

SCIF Interrupt Sources and the DMAC

747

Table 16.6 SCIF Interrupt Sources

747

Usage Notes

748

Overview

753

Features
753
Block Diagram
754
Pin Configuration
755
Register Configuration
755
Table 17.1 Smart Card Interface Pins
755
Table 17.2 Smart Card Interface Registers
755

Section 17 Smart Card Interface

753

Register Descriptions

756

Operation

760

Usage Notes

775

Overview

781

Features
781
Block Diagrams
782
Pin Configuration
789
Table 18.1 20-Bit General-Purpose I/O Port Pins
789
Table 18.2 SCI I/O Port Pins
790
Table 18.3 SCIF I/O Port Pins
790
Register Configuration
791
Table 18.4 I/O Port Registers
791

Section 18 I/O Ports

781

Register Descriptions

792

Port Control Register a (PCTRA)
792
Port Data Register a (PDTRA)
793
Port Control Register B (PCTRB)
794
Port Data Register B (PDTRB)
795
GPIO Interrupt Control Register (GPIOIC)
795
Serial Port Register (SCSPTR1)
796
Serial Port Register (SCSPTR2)
798

Overview

801

Section 19 Interrupt Controller (INTC)

801

Interrupt Sources

804

Register Descriptions

811

INTC Operation

818

Interrupt Response Time

821

Table 19.9 Interrupt Response Time

821

Overview

823

Section 20 User Break Controller (UBC)

823

Register Descriptions

826

Access to UBC Control Registers
826
Break Address Register a (BARA)
827
Break ASID Register a (BASRA)
828
Break Address Mask Register a (BAMRA)
828
Break Bus Cycle Register a (BBRA)
829
Break Address Register B (BARB)
831
Break ASID Register B (BASRB)
831
Break Address Mask Register B (BAMRB)
831
Break Data Register B (BDRB)
831
Break Data Mask Register B (BDMRB)
832
Break Bus Cycle Register B (BBRB)
833
Break Control Register (BRCR)
833

Operation

835

User Break Debug Support Function

843

Examples of Use

845

User Break Controller Stop Function

847

Overview

849

Section 21 Hitachi User Debug Interface (H-UDI)

849

Register Descriptions

853

Operation

860

TAP Control
860
H-UDI Reset
861
H-UDI Interrupt
861
Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only)
862

Usage Notes

862

Absolute Maximum Ratings

863

Section 22 Electrical Characteristics

863

Table 22.1 Absolute Maximum Ratings

863

DC Characteristics

864

Table 22.2 DC Characteristics (HD6417750RBP240)

864

Table 22.3 DC Characteristics (HD6417750RF240)

866

Table 22.4 DC Characteristics (HD6417750RBP200)

868

Table 22.5 DC Characteristics (HD6417750RF200)

870

Table 22.6 DC Characteristics (HD6417750SBP200)

872

Table 22.7 DC Characteristics (HD6417750SF200)

874

Table 22.8 DC Characteristics (HD6417750BP200M)

876

Table 22.9 DC Characteristics (HD6417750SF167)

878

Table 22.10 DC Characteristics (HD6417750SF167I)

880

Table 22.11 DC Characteristics (HD6417750F167)

882

Table 22.12 DC Characteristics (HD6417750F167I)

884

Table 22.13 DC Characteristics (HD6417750SVF133)

886

Table 22.14 DC Characteristics (HD6417750SVBT133)

888

Table 22.15 DC Characteristics (HD6417750VF128)

890

Table 22.16 Permissible Output Currents

891

AC Characteristics

892

Table 22.17 Clock Timing (HD6417750RBP240)

892

Table 22.18 Clock Timing (HD6417750RF240)

892

Table 22.19 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200)

892

Table 22.20 Clock Timing (HD6417750RF200)

892

Table 22.21 Clock Timing (HD6417750SF200)

892

Table 22.22 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I)

893

Table 22.23 Clock Timing (HD6417750SVF133, HD6417750SVBT133)

893

Table 22.24 Clock Timing (HD6417750VF128)

893

Hd6417750Sf167, Hd6417750Sf167I)

906

Hd6417750Svbt133: V

908

Table 22.33 Clock and Control Signal Timing (HD6417750VF128)

910

Figure 22.1 EXTAL Clock Input Timing

912

Figure 22.2(1) CKIO Clock Output Timing

912

Figure 22.2(2) CKIO Clock Output Timing

912

Figure 22.3 Power-On Oscillation Settling Time

913

Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET)

913

Figure 22.5 Power-On Oscillation Settling Time

914

Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET)

914

Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI)

915

Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3-IRL0)

915

Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt

916

Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt

916

Figure 22.11 Manual Reset Input Timing

917

Figure 22.12 Mode Input Timing

917

Insertion, Ans = 1, Anh = 1)

930

Figure 22.19 Burst ROM Bus Cycle (no Wait)

931

Figure 22.20 Burst ROM Bus Cycle (1St Data: One Internal Wait + One External Wait; 2Nd/3Rd/4Th Data: One Internal Wait)

932

Figure 22.21 Burst ROM Bus Cycle (no Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1)

933

Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait)

934

Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)

935

Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)

937

Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD[1:0] = 01, CAS Latency = 3)

937

CAS Latency = 3)

938

Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3)

939

Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)

940

Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)

941

Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010)

942

Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)

943

Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL[2:0] = 010)

944

Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (TPC[2:0] = 001)

945

Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (tras = 1, TRC[2:0] = 001)

946

Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001)

947

Figure 22.36 (A) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL)

948

Figure 22.36 (B) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET)

949

Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 010

950

Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)

951

Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)

952

Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)

953

TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)

954

Figure 22.42 DRAM Burst Bus Cycle: RAS down Mode State (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000)

955

Figure 22.43 DRAM Burst Bus Cycle: RAS down Mode Continuation (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000)

956

Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)

957

Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)

958

Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)

959

Figure 22.47 DRAM Burst Bus Cycle: RAS down Mode State (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)

960

(Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)

961

(Tras[2:0] = 000, Trc[2:0] = 001)

962

(Tras[2:0] = 001, Trc[2:0] = 001)

963

Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)

964

Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, no Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait

965

Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, no Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait

966

Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing)

967

1St Data (One Internal Wait + One External Wait)

968

1St Data (One Internal Wait + One External Wait)

969

1St Data (One Internal Wait), 2Nd to 4Th Data (One Internal Wait + One External Wait)

970

Figure 22.58 MPX Bus Cycle: Burst Write (1) no Internal Wait (2) 1St Data (One Internal Wait), 2Nd to 4Th Data (no Internal Wait + External Wait Control)

971

Basic Read Cycle (One Internal Wait + One External Wait)

972

Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (no Wait, Address Setup/Hold Time Insertion, Ans[0] = 1, Anh[1:0] =01)

973

Appendix A Address List

987

Table A.1 Address List

988

Appendix B Package Dimensions

993

Appendix C Mode Pin Settings

997

Appendix D CKIO2ENB Pin Configuration

999

Appendix E Pin Functions

1001

Pin States

1001

Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State
1001

Handling of Unused Pins

1004

Appendix F Synchronous DRAM Address Multiplexing Tables

1005

Appendix G Prefetching of Instructions and Its Side Effects

1027

Hd6417750Sbp200

1029

Table I.1 SH7750 Series Product Code Lineup

1029

Hitachi SH7750 series Manuals

Hitachi SH7750 series Hardware Manual (1037 pages)

Table of Contents

Table of Contents

Table of Contents

Hitachi SH7750 series Hardware Manual (858 pages)

Table of Contents

Hitachi SH7750 series Programming Manual (412 pages)

Table of Contents

Section 1 Overview

Section 2 Programming Model

Section 3 Memory Management Unit (MMU)

Section 4 Caches

Section 5 Exceptions

Section 6 Floating-Point Unit

Section 7 Instruction Set

Section 8 Pipelining

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