Fujitsu MB86R02 Manuals

Manuals and User Guides for Fujitsu MB86R02. We have 2 Fujitsu MB86R02 manuals available for free PDF download: Hardware Manual, Application Note

Fujitsu MB86R02 Hardware Manual (892 pages)

Graphics Controller

Brand: Fujitsu | Category: Video Card | Size: 13.24 MB

Table of Contents
9
MB86R02 'Jade-D' Hardware Manual
24
1 Overview

25
- Features
  25
- Block Diagram
  27
  - Outline of each Functional Block
    28
- Function Summary of the Blocks
  30
- Package Dimensions
  33
- Pinning
  34
- Pin Assignment
  34
  - Pin Assignment Table
    36
  - Pin Multiplexing
    46
- Pin Functional Description
  55
2 System Configuration

74
- Typical Application
  74
3 Memory Map

75
- Memory Map of LSI
  75
- Register Access
  78
4 CPU (ARM926EJ-S Core)

79
5 Clock Reset Generator (CRG)

81
- Outline
  81
- Features
  81
- Overview
  82
- Location in the Device
  83
- Operation
  83
  - Reset Generation
    83
  - INITRAM Control
    84
  - Clock Generation
    87
- Registers
  96
6 Spread Spectrum Clock Generator (SSCG)

114
- Position of Block in Whole LSI
  114
- Features
  114
  - Functional
    114
  - Limitations
    114
- Software Interface
  116
  - Format of Register Description
    116
  - Global Address
    117
  - Register Summary
    117
- Register Description
  117
- Processing Mode
  121
  - Parameter Setting for 666Mhz PLL Clock
    121
    
    Parameter Setting for SSCG-Speed of 15Khz
    121
    
    Parameter Setting for SSCG-Speed of 20Khz
    122
    
    Parameter Setting for SSCG-Speed of 35Khz
    123
    
    Parameter Setting for SSCG-Speed of 50Khz
    123
- Control Flow
  124
  - Operation
    124
7 CCNT (Chip Control)

125
- Overview
  125
- Features
  126
- Supply Clock
  126
- Registers
  127
8 Remap Boot Controller (RBC)

160
- Outline
  160
- Features
  160
- Block Diagram
  160
- Supply Clock
  161
- Register
  161
  - Register List
    161
  - Remap Control Register (RBREMAP)
    163
  - VINITHI Control Register a (RBVIHA)
    164
  - INITRAM Control Register a (RBITRA)
    165
- Operation
  166
  - RBC Reset
    166
  - Remap Control
    166
  - VINITHI Control
    166
  - INITRAM Control
    168
9 Interrupt Request Controller (IRC)

169
- Overview
  169
- Features
  169
- Interrupt Map
  170
- Block Diagram
  175
- Register
  176
  - Register List
    176
  - IRQ Flag Register (IRQF)
    183
  - IRQ Mask Register (IRQM)
    184
  - Interrupt Level Mask Register (ILM)
    184
  - ICR Monitoring Register (ICRMN)
    186
  - Holding Request Cancellation Level Register (HRCL)
    187
  - Delay Interrupt Control Register (DICR)
    188
  - Interrupt Vector Register (VCT)
    190
  - IRQ Test Register (IRQTEST)
    191
  - FIQ Test Register (FIQTEST)
    192
  - Interrupt Control Register (ICR31-ICR00)
    193
- Operation Explanation
  195
  - Outline of Operation
    195
  - Initialization
    195
  - Multiple Interrupt Processing
    196
  - Example of IRQ Interrupt Handler
    196
  - Stop and Return from Sleep Mode
    198
  - Notes on Use of IRC
    199
10 External Interrupt Controller (EXIRC)

200
- Outline
  200
- Feature
  200
- Block Diagram
  201
- Supply Clock
  201
- Register
  202
- Operation
  207
- Operation Procedure
  207
- Instruction for Use
  207
11 External Bus Interface

208
- Outline
  208
- Features
  208
- Block Diagram
  208
- Related Pin
  209
- Supply Clock
  209
- Register
  210
- Connection Example
  219
- Example of Access Waveform
  220
- Operation
  224
12 Embedded SRAM

227
- Outline
  227
- Features
  227
- Block Diagram
  227
- Supply Clock
  227
13 DDR2 Controller

228
- Outline
  228
- Features
  228
- Limitation
  228
- Block Diagram
  229
- Supply Clock
  230
- Registers
  230
- Operation
  254
  - DRAM Initialization Sequence
    254
  - DRAM Initialization Procedure
    255
    
    SDRAM Initialization Procedure
    257
    
    OCD Adjustment Procedure
    260
    
    ODT Setting Procedure
    262
14 Timer (TIMER)

263
- Outline
  263
- Feature
  263
- Supply Clock
  263
- Specification
  263
15 DMA Controller (DMAC)

264
- Outline
  264
- Feature
  264
- Block Diagram
  265
- Related Pins
  266
- Supply Clock
  266
- Registers
  267
- Operation
  279
  - Transfer Modes
    279
    
    Block Transfer
    279
    
    Timing Chart
    281
    
    Limitations with I2S DMA
    283
    
    Burst Transfer
    284
    
    Demand Transfer
    288
  - Beat Transfer
    292
    
    Normal and Single Transfer
    292
    
    Increment and Lap Transfer
    293
  - Channel Priority Control
    294
    
    Fixed Priority
    294
    
    Rotate Priority
    295
  - Retry, Split, and Error
    296
    
    Retry and Split
    296
    
    Error
    297
- DMAC Configuration Examples
  298
  - DMA Start in Single Channel
    298
  - DMA Start in All Channels (in Demand Transfer Mode)
    299
16 Host Interface

300
- Outline
  300
- Features
  300
  - Limitations
    300
- Function
  301
  - Block Diagram
    301
  - SPI Interface
    301
    
    Write Access
    301
    
    Read Access
    303
  - Interrupt
    305
    
    AHB Slave Module Access Error Response
    305
  - Reset Request
    305
- External Interfaces
  306
  - Communication Protocols (Timing Diagrams)
    306
    
    SPI Protocol Stack
    306
  - Data Formats
    307
    
    Host Interface (Clock Timing and Phase)
    307
    
    Reset Frame
    307
    
    Signal Input Format from the Host CPU
    307
- Application Notes
  309
  - Processing Flow
    309
    
    Begin Timing of Protocol Sequence
    309
    
    Receive Operation and the STATUS Byte
    309
    
    Setting the Address
    309
    
    Handling of Irregular Operating Conditions
    310
17 APIX® Interface

314
- Outline
  314
- Features
  314
  - Apix® Phy
    314
  - APIX® Ashell
    314
  - Jade-D Restrictions
    315
  - Block Diagram
    316
- Software Interface
  317
  - Format of Register Description
    317
  - Global Address
    317
  - Register Summary
    318
  - Register Description
    319
- Description of APIX Ashell and APIX PHY Configuration Bytes
  329
- GPIO Interface Timing of Sideband Uplink and Downlink
  351
- Control Flow
  352
  - Use Cases
    353
    
    Use Case 1
    353
    
    Use Case 2
    355
  - Application Notes for PCB Designers
    357
18 Graphics Display Controller (GDC)

359
- Preface
  359
- Features
  359
- Functional Overview
  360
  - Display Controller
    360
  - Video Capture Function
    362
  - Geometry Processing
    362
  - Drawing
    363
  - Drawing
    365
  - Special Effects
    366
  - Others
    368
- Graphics Memory
  369
  - Memory Map
    369
  - Configuration
    370
  - Data Type
    370
  - Data Format
    371
- Frame Management
  373
  - Single Buffer
    373
  - Double Buffer
    373
- Display Controller
  374
  - Overview
    374
  - Display Function
    375
    
    Layer Configuration
    375
    
    Overlay
    376
    
    Display Parameters
    378
    
    Display Position Control
    379
  - Display Color
    381
    
    Direct Color (16 Bits/Pixel)
    381
    
    Direct Color (24 Bits/Pixel)
    381
    
    Indirect Color (8 Bits/Pixel)
    381
    
    Alpha Factor (8 Bits/Pixel)
    382
    
    Layer Dependence
    382
    
    Ycbcr Color (16 Bits/Pixel)
    382
  - Cursor
    383
    
    Cursor Control
    383
    
    Cursor Display Function
    383
  - Display Scan Control
    383
    
    Applicable Display
    383
    
    Interlace Display
    384
  - Programmable Ycbcr/Rgb Conversion for L1-Layer Display
    385
  - DCLKO Shift
    387
  - Synchronous Register Updates and Display
    387
  - Parallel Dual Display
    388
  - Multiplex Dual Display
    389
    
    Destination Control
    389
    
    Overview
    389
    
    Output Circuit Example
    390
    
    Output Signal Control
    390
    
    Display Clock and Timing
    392
    
    Dual Display Configuration Example
    392
    
    Limitations
    392
  - Video Output Limitation
    393
  - Interrupt
    393
- Video Capture
  395
  - Video Capture Function
    395
    
    Input Data Formats
    395
    
    Non-Interlace Transformation
    395
    
    Video Signal Capture
    395
  - Input Port Selection
    396
  - Video Buffer
    398
    
    Data Format
    398
    
    Area Allocation
    399
    
    Synchronization Control
    399
    
    Window Display
    399
    
    Interlaced Display
    400
  - Scaling
    401
    
    Downscaling Function
    401
    
    Upscaling Function
    401
    
    Flow of Image Processing
    403
  - External Video Signal Input Conditions
    406
    
    RTB656 YUV422 Input Format
    406
    
    RGB Input Format
    408
    
    Input Operation
    409
    
    Conversion Operation
    411
  - Display Controller / Video Capture Register Summary
    413
    
    Common Control Registers
    413
    
    Display Controller Registers
    413
    
    Video Capture Registers
    419
  - Explanation of Local Memory Registers
    421
  - Common Control Register
    422
  - Display Control Register
    424
  - Video Capture Registers
    479
- Timing Diagrams
  496
  - Display Timing Diagram
    496
    
    Non-Interlace Mode
    496
    
    Interlace Video Mode
    498
  - Composite Synchronous Signal
    499
- Geometry Engine
  500
  - Geometry Pipeline
    500
    
    Processing Flow
    500
    
    2D Transformation (CC→NDC Coordinate Transformation)
    501
    
    Model-View-Projection (MVP) Transformation
    501
    
    View Port Transformation (NDC→DC Coordinate Transformation)
    502
    
    View Volume Clipping
    502
    
    Back Face Culling
    504
  - Data Format
    505
    
    Setup Processing
    506
  - Log Output of Device Coordinates
    506
    
    Log Output Destination Address
    506
    
    Log Output Format
    506
    
    Log Output Mode
    506
- Drawing Processing
  507
  - Coordinate System
    507
    
    Drawing Coordinates
    507
    
    Frame Buffer
    508
    
    Texture Coordinates
    508
    
    Drawing Primitives
    509
    
    Figure Drawing
    509
    
    Polygon Drawing Function
    509
    
    Drawing Parameters
    510
    
    Anti-Aliasing Function
    511
  - Bit Map Processing
    512
    
    Blt
    512
    
    Pattern Data Format
    512
  - Texture Mapping
    513
    
    Texture Color
    513
    
    Texture Size
    513
    
    Texture Wrapping
    514
    
    Filtering
    515
    
    Perspective Correction
    515
    
    Bi-Linear High-Speed Mode
    516
    
    Texture Blending
    516
  - Rendering
    518
    
    Alpha Blending
    518
    
    Tiling
    518
    
    Hidden Plane Management
    519
    
    Logic Operation
    519
  - Drawing Attributes
    520
    
    Line Drawing Attributes
    520
    
    Triangle Drawing Attributes
    520
    
    Texture Attributes
    521
    
    BLT Attributes
    522
    
    Character Pattern Drawing Attributes
    522
  - Bold Line
    522
    
    Starting and Ending Points
    522
    
    Broken Line Pattern
    523
    
    Edging
    524
    
    Interpolation of Bold Line Joint
    525
  - Shadowing
    526
- Overview
  526
- Display Lists
  526
  - Header Format
    528
  - Parameter Format
    528
  - Geometry Commands
    529
    
    Geometry Command List
    529
    
    Explanation of Geometry Commands
    533
  - Rendering Commands
    542
    
    Command List
    542
    
    Details of Rendering Commands
    547
  - Drawing Engine / Geometry Engine Register Summary
    557
    
    Drawing Engine Register List
    557
    
    Geometry Engine Register List
    564
  - Drawing Control Registers
    565
  - Drawing Mode Registers
    568
  - Triangle Drawing Registers
    586
  - Line Drawing Registers
    589
  - Pixel Drawing Registers
    590
  - Rectangle Drawing Registers
    590
  - Blt Registers
    591
  - High-Speed 2D Line Drawing Registers
    592
  - High-Speed 2D Triangle Drawing Registers
    593
  - Geometry Control Register
    594
  - Geometry Mode Registers
    596
  - Display List FIFO Registers
    603
  - Display List DMA Contol Registers
    604
    
    Display List DMA Contol Register List
    604
    
    Interrupt Register List
    607
    
    Interrupt Registers
    607
19 Color Lookup Table (CLUT)

610
- Color LUT
  610
  - Software Interface
    612
  - Limitations
    613
- Initialization Procedure
  613
20 Dither Unit

614
- Features
  614
- Overview
  614
- Position
  615
- Timing Chart
  616
  - Format of Register Description
    617
  - Global Address
    617
  - Register Summary
    617
  - Software Interface
    617
- Initialization Procedure
  618
- Limitations
  618
21 Signature Generator (SIG)

619
- Feature List
  619
- Overview
  619
- Position of Block in Whole LSI
  619
- Automatic Monitoring and Interrupt
  620
- Interrupts for Control Flow
  620
- Programmable Evaluation Window (Position and Size)
  620
- Programmable Evaluation Window Mask
  620
- Programmable Input Picture Source
  620
- Self Restoring Error Counter
  620
- Signature A: CRC-32 Signature
  620
- Signature B: Summation Signature
  620
- Limitations
  621
- Software Interface
  621
  - Format of Register Description
    621
  - Global Address
    622
  - Register Summary
    622
  - Register Description
    623
    
    Processing Algorithm
    630
    
    Processing Flow
    630
    
    Processing Mode
    630
    
    Example Control Flow
    631
  - Signature Generation with Every Incoming Frame
    633
  - Cyclic Signature Generation with Every Incoming Frame
    633
  - Cyclic Signature Generation with Every Incoming Frame, Limiting Read Accesses
    634
  - Limitation of Cyclic Signature Generation
    634
22 Timing Controller (TCON)

635
- Position of Block in Whole LSI
  635
- Overview
  635
- Feature List
  635
- Software Interface
  637
  - Processing Algorithm
    663
    
    Operation Modes
    663
    
    Processing Flow
    663
    
    Processing Mode
    663
    
    RSDS Bitmap Mdule (RBM)
    664
    
    SW Reset
    664
    
    Timing Signal Module (TSIG)
    666
    
    Inversion Signal Generation
    671
    
    Bypass-Mode
    672
- AC Characteristics
  673
  - Limitations
    675
  - Application Note
    676
  - Channel to Pin Mapping
    676
  - Pin Mapping RSDS
    676
  - Pin Mapping TTL
    676
  - Example Control Flow
    683
23 Run-Length Decompression (RLD)

685
- Position of Block in Whole LSI
  685
  - Data Flow in the LSI
    685
- Feature List
  686
  - Configuration Bus Interface
    686
    
    Interrupt
    686
    
    Data Formats
    687
    
    Input Data Format
    687
    
    Format of Register Description
    688
    
    Output Data Format
    688
    
    Software Interface
    688
    
    Global Address
    689
    
    Register Summary
    689
    
    Register Description
    690
    
    Processing Modes
    693
  - Integration and Application Hints
    686
    
    Communication Protocols (Timing Diagrams)
    686
    
    Usage of RLD with Jade-D
    686
  - Overview
    686
  - References
    686
  - Result Interface
    686
  - Example Control Flow
    693
  - Processing Algorithm
    693
  - Processing Flow
    693
  - Ahbmtransferwidth Setup
    694
- Limitations
  694
24 General-Purpose Input/Output Port (GPIO)

695
- Outline
  695
  - Feature
    695
- Block Diagram
  695
- Supply Clock
  696
- Limitations
  696
  - Register List
    697
  - Port Data Register 0-2 (GPDR0-2)
    699
  - Data Direction Register 0-2 (GPDDR0-2)
    701
  - Direction Control
    703
  - Operation
    703
  - Data Transfer
    703
25 Pulse Width Modulator (PWM)

704
- Outline
  704
- Feature
  704
- Clock Supply
  705
  - Block Diagram
    705
  - Interrupts
    705
  - Related Pins
    705
  - Register List
    706
  - Registers
    706
  - Pwmx Base Clock Register (Pwmxbcr)
    708
  - Pwmx Pulse Width Register (Pwmxtpr)
    709
  - Pwmx Phase Register (Pwmxpr)
    710
  - Pwmx Duty Register (Pwmxdr)
    711
  - Pwmx Status Register (Pwmxcr)
    712
  - Pwmx Start Register (Pwmxsr)
    713
  - Pwmx Current Count Register (Pwmxccr)
    714
  - Pwmx Interrupt Register (Pwmxir)
    715
- Example of Setting a Register
  716
26 A/D Converter

717
- Features
  717
- Outline
  717
- Block Diagram
  718
- Related Pins
  718
- Supply Clock
  718
- Channel Mapping Table
  719
- Output Truth Value List
  719
- Analog Pin Equivalent Circuit
  720
  - Register List
    721
  - Registers
    721
  - Format of Register Descriptions
    722
  - Adcx Data Register (Adcxdata)
    723
  - Adcx Mode Register (Adcxmode)
    723
  - Adcx Power down Control Register (Adcxxpd)
    723
  - Adcx Clock Selection Register (Adcxcksel)
    724
  - Adcx Status Register (Adcxstatus)
    726
- Basic Operation Flow
  727
27 Serial Audio Interface (I2S)

728
- Features
  728
- Outline
  728
- Block Diagram
  729
- Related Pins
  730
- Supply Clock
  730
- Register List
  731
- Registers
  731
- Description Format of Registers
  732
- I2Sxrxfdat Register
  733
- I2Sxtxfdat Register
  734
- I2Sxcntreg Register
  735
- I2Sxmcr0Reg Register
  738
- I2Sxmcr1Reg Register
  739
- I2Sxmcr2Reg Register
  740
- I2Sxoprreg Register
  741
- I2Sxsrst Register
  742
- I2Sxintcnt Register
  743
- I2Sxstatus Register
  746
- I2Sxdmaact Register
  748
  - Operation
    749
  - Outline
    749
- Transfer Start, Stop, and Malfunction
  750
- Frame Construction
  756
  - Sub Frame Construction
    756
  - Sub Frame Construction
    757
  - Bit Alignment
    758
  - FIFO Construction and Description
    760
28 UART Interface

763
- Block Diagram
  763
- Feature
  763
- Outline
  763
- Related Pin
  764
- Supply Clock
  764
- Register List
  765
- Registers
  765
- Reception FIFO Register (Urtxrfr)
  768
- Transmission FIFO Register (Urtxtfr)
  768
- Interrupt Enable Register (Urtxier)
  769
- Interrupt ID Register (Urtxiir)
  770
- FIFO Control Register (Urtxfcr)
  771
- Line Control Register (Urtxlcr)
  772
- Modem Control Register (Urtxmcr)
  773
- Line Status Register (Urtxlsr)
  774
- Modem Status Register (Urtxmsr)
  775
- Divider Latch Register (Urtxdll&Urtxdlm)
  776
- UART Operation
  778
  - Example of Initial Setting
    778
  - Example of Transfer Procedure
    779
  - Example of Reception Procedure
    780
  - Basic Transmission Operation
    781
  - Basic Reception Operation
    782
  - Line Status
    783
  - Character Time-Out Interrupt
    787
29 I2C Bus Interface

788
- Features
  788
- Outline
  788
- Block Diagram
  789
- Block Functions
  790
  - Related Pins
    791
  - Supply Clock
    791
  - Register
    792
  - Register List
    792
  - Bus Status Register (I2Cxbsr)
    794
  - Bus Control Register (I2Cxbcr)
    796
  - Clock Control Register (I2Cxccr)
    799
  - Address Register (I2Cxadr)
    802
  - Data Register (I2Cxdar)
    803
  - Two Bus Control Registers (I2Cxbc2R)
    804
  - Expansion CS Register (I2Cxecsr)
    805
  - Bus Clock Frequency Register (I2Cxbcfr)
    807
  - Operation
    808
  - Start Condition
    808
  - Stop Condition
    809
  - Addressing
    810
  - Synchronous Arbitration of SCL
    812
  - Arbitration
    813
  - Acknowledge/Negative Acknowledge
    814
  - Bus Error
    815
  - Initialization
    816
  - One Byte Transfer from Master to Slave
    817
  - One Byte Transfer from Slave to Master
    818
  - Resume from Bus Error
    819
    
    Interrupt Process and Wait Request Operation to Master
    820
    
    Notes
    820
30 Serial Peripheral Interface (SPI)

822
- Features
  822
- Outline
  822
- Block Diagram
  823
- Supply Clock
  823
- Transition State
  824
  - Register List
    825
  - Registers
    825
  - SPI Control Register (Spincr)
    827
  - SPI Slave Control Register (Spinscr)
    829
  - SPI Data Register (Spindr)
    832
  - SPI Status Register (Spinsr)
    833
- Setup Procedure Flow
  834
31 CAN Interface (CAN)

835
- Outline
  835
- Block Diagram
  835
- Supply Clock
  836
- Registers
  836
32 Medialb Interface

837
- Block Diagram
  837
- Outline
  837
- Registers
  838
- Supply Clock
  838
33 SD Memory Controller (SDMC)

839
34 Electrical Characteristics

840
- Maximum Ratings
  840
- Recommended Operating Conditions
  841
- Precautions at Power on
  842
  - Recommended Power On/Off Sequence
    842
  - Power on Reset
    843
- DC Characteristics
  844
  - V Standard CMOS I/O
    844
    
    V Standard CMOS I/O V-I Characteristic (Driving Capability 1)
    846
    
    V Standard CMOS I/O V-I Characteristic (Driving Capability 2)
    847
    
    V Standard CMOS I/O V-I Characteristics (Driving Capability 3)
    848
  - Ddr2Sdram if I/O (Sstl_18)
    849
  - I2C Bus Fast Mode I/O
    853
  - I2C IO V-1 Characteristic Figure
    854
  - Memory Controller Signal Timing
    855
  - AC Characteristics
    855
  - DDR2SDRAM Interface
    859
    
    DDR2SDRAM Interface Timing Diagram
    860
  - GPIO Signal Timing
    863
  - PWM Signal Timing
    864
    
    Output Signal
    864
  - GDC Display Signal Timing
    865
    
    Clock
    865
    
    Input Signal
    865
    
    Output Signal
    867
  - TCON Active Display Timing DISP0 Interface
    869
  - RSDS Characteristics
    871
  - GDC Video Capture Signal Timing
    871
    
    Clock
    871
    
    Input Signal
    871
  - I2S Signal Timing
    874
  - UART Signal Timing
    876
  - I2C Bus Timing
    877
  - SPI Signal Timing
    878
  - CAN Signal Timing
    879
  - Medialb Signal Timing
    880
    
    Medialb AC Spec Type a
    880
    
    Medialb AC Spec Type B
    881
  - SD Signal Timing
    883
    
    Clock
    883
    
    Input/Output Signal
    883
  - ETM9 Trace Port Signal Timing
    885
  - EXIRC Signal Timing
    886
  - Apix Characteristics
    887
    
    Power Supply
    887
    
    Transmitter Drive Current
    887
    
    Receiver Common Mode
    888
    
    Receiver Input Sensitivity
    888
    
    Transmitter De-Emphasis
    888
    
    Transmitter Serial Data Signal Characteristics
    888
  - OSC Characteristics
    889
    
    Crystal and Clock Buffer Frequencies
    889
    
    Internal Feedback Resistor
    889
    
    Power Supply
    889
35 Addendum: Differences ES1 / ES2

890
- Multiplex (2)
  890
- PU/PD Added
  891
- SSCG (Spread-Spectrum Modulation)
  892
- Polarity of JTAGSEL
  892
- APIX Initialization
  892

Fujitsu MB86R02 Application Note (17 pages)

EMI Optimization using SSCG

Brand: Fujitsu | Category: Microcontrollers | Size: 0.56 MB

Table of Contents
3
1 Document Revision History

4
2 Spread-Spectrum Clocking Introduction

5
3 Clock Tree Overview

6
4 Clock Signals that Can be Modulated

7
5 The SSCG Unit in MB86R02 'Jade-D

8
- Operating Frequency Ranges
  8
- Modulation Parameters
  8
  - Modulation Period
    8
  - Modulation Period Delta (Jitter)
    9
  - Modulation Type
    9
  - Modulation Peak
    11
  - Modulation Shape
    12
- Using Frequency Offset (SSCG_FOFFSET)
  13
6 Selecting the SSCG Operating Frequency

13
7 How to Configure the SSCG Unit

14
8 Enabling the SSCG Unit

16
9 Checking the SSCG Unit Is Operating

16
10 Important Notes During Operation

16
11 Disabling the SSCG Unit

17

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Fujitsu MB86R02 Manuals

Fujitsu MB86R02 Hardware Manual (892 pages)

Table of Contents

1 Overview

2 System Configuration

3 Memory Map

4 CPU (ARM926EJ-S Core)

5 Clock Reset Generator (CRG)

6 Spread Spectrum Clock Generator (SSCG)

7 CCNT (Chip Control)

8 Remap Boot Controller (RBC)

9 Interrupt Request Controller (IRC)

10 External Interrupt Controller (EXIRC)

11 External Bus Interface

12 Embedded SRAM

13 DDR2 Controller

14 Timer (TIMER)

15 DMA Controller (DMAC)

16 Host Interface

17 APIX® Interface

18 Graphics Display Controller (GDC)

19 Color Lookup Table (CLUT)

20 Dither Unit

21 Signature Generator (SIG)

22 Timing Controller (TCON)

23 Run-Length Decompression (RLD)

24 General-Purpose Input/Output Port (GPIO)

25 Pulse Width Modulator (PWM)

26 A/D Converter

27 Serial Audio Interface (I2S)

28 UART Interface

29 I2C Bus Interface

30 Serial Peripheral Interface (SPI)

31 CAN Interface (CAN)

32 Medialb Interface

33 SD Memory Controller (SDMC)

34 Electrical Characteristics

35 Addendum: Differences ES1 / ES2

Fujitsu MB86R02 Application Note (17 pages)

Table of Contents

1 Document Revision History

2 Spread-Spectrum Clocking Introduction

3 Clock Tree Overview

4 Clock Signals that Can be Modulated

5 The SSCG Unit in MB86R02 'Jade-D

6 Selecting the SSCG Operating Frequency

7 How to Configure the SSCG Unit

8 Enabling the SSCG Unit

9 Checking the SSCG Unit Is Operating

10 Important Notes During Operation

11 Disabling the SSCG Unit

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