Emerson CPCI-6200 Manuals

Manuals and User Guides for Emerson CPCI-6200. We have 1 Emerson CPCI-6200 manual available for free PDF download: Installation Manual

Emerson CPCI-6200 Installation Manual (196 pages)

Brand: Emerson | Category: PCI Card | Size: 4.26 MB

Table of Contents
3
About this Manual
15
Introduction
21
Features
21
Table 1-1 Summary of Features
21
Standard Compliances
24
Figure 1-1 Declaration of Conformity
25
Mechanical Data
26
Ordering Information
26
Supported Board Models
26
Board Accessories
26
Table 1-2 Order Numbers for Baseboard Variants
26
Table 1-3 Order Numbers for Related Products
26
Product Identification
27
Figure 1-2 Location of the Product Serial Number
27
Hardware Preparation and Installation
29
Overview
29
Unpacking the CPCI Baseboard
29
Environmental Requirements
30
Table 2-1 CPCI-6200 Environmental Requirements
30
Power Requirements
31
Table 2-2 Baseboard Power Requirements
31
Installing Accessories
32
Installing a PMC Module on the CPCI Baseboard
32
Installing the Rear Transition Module
34
Preparing the Baseboard for Installation
34
Inspecting the CPCI Baseboard
34
Equipment Required for Installation
35
Hardware Configuration
35
Board Configuration Switch, S1
36
Figure 2-1 Location of Configuration Switches
36
Table 2-3 S1 Switch Settings
37
IPMI Configuration Switch, S2
38
Table 2-4 S2 Switch Settings
38
Installing the CPCI Baseboard
39
Removing the CPCI Baseboard
41
Connecting to a Console Port
42
Factory-Installed Linux
42
Controls, Leds, and Connectors
45
Board Layout
45
Front Panel
46
Connectors and Headers
47
Table 3-1 Onboard Connectors
47
CPCI Bus Connector, J1
48
Table 3-2 CPCI Bus Connector Pinout, J1
48
CPCI Bus Connector, J2
49
Table 3-3 CPCI Bus Connector Pinout, J2
49
CPCI User I/O Connector, J3
50
Table 3-4 CPCI User I/O Connector Pinout, J3
50
CPCI Connector, J4
51
CPCI User I/O Connector, J5
51
PCI Mezzanine Card (PMC) Connectors
52
Table 3-5 CPCI User I/O Connector Pinout, J5
52
Table 3-6 PMC Connector Pinout, J11/J21
54
Table 3-7 PMC Connector Pinout, J12/J22
55
Table 3-8 PMC Connector Pinout, J13/J23
55
Table 3-9 PMC Connector Pin Assignments , J14/J24
57
Ethernet Connector
58
USB Connector
58
Figure 3-2 USB Connector Pinout
58
Serial Port Connector, J16
59
Board Insertion/Extraction Connector, P1
59
Table 3-10 Front Panel Latch Pinout, P1
59
Figure 3-3 Serial Port Connector Pinout, J16
59
DDR3 SO-DIMM Connectors, XJ1 and XJ2
60
Table 3-11 DDR3 SO-Dimms Pinout, XJ1 and XJ2
60
PCI Express Expansion Connector, J17
62
Table 3-12 PCI Express Expansion Connector Pinout, J17
62
IPMI Debug and FW Programming Header, P3
64
Processor Debug Header, P4
64
Table 3-13 IPMI Debug Pinout, P3
64
Table 3-14 Processor Debug Header Pinout, P4
64
Boundary Scan Header, P5
65
Processor COP Header, P6
65
Table 3-15 Boundary Scan Header Pinout, P5
65
Table 3-16 COP Header Pinout, P6
65
PCI Express Switch Header, P7
66
Switches
66
Onboard Switches
66
Table 3-17 PCI Express Switch Header Pinout, P7
66
Reset/Abort Switch, P2
67
Front Panel Leds
67
Table 3-18 Front Panel Reset Switch Pinout, P2
67
Status Indicators
68
Table 3-19 CPCI-6200 Status Indicators
68
Functional Description
71
Overview
71
Figure 4-1 CPCI-6200 Block Diagram
72
MPC8572 Integrated Processor
73
I2C Serial Interface and Devices
73
I2C Bus 0
73
I2C Bus 1
73
I2C Bus 2
73
I2C Bus 3
74
I2C Bus 4
74
I2C Bus 5
74
System Memory
74
Timers
75
Ethernet Interfaces
75
Local Bus Interface
75
Flash Memory
75
MRAM (Magnetoresistive Random Access Memory)
77
Control and Timers PLD
77
Serial COM Ports
78
DUART Interface
78
PCI Express Port
79
Figure 4-4 PCI Express Bus Topology
79
PCI/PCI-X Bus
80
PCI Mezzanine Card Sites (PCI-X Bus 1 and 2)
80
PCI 6466 Universal Bridge (PCI Bus 3)
80
USB (PCI Bus 4)
81
PCI Bus Frequency
81
Operation Modes
81
Table 4-1 PCI Buses 1 and 2 Frequency Requirements
81
System Controller Mode
82
Peripheral Mode
82
Figure 4-5 System Controller Mode
82
Stand Alone Mode
83
Figure 4-6 Peripheral Mode
83
PCI Express Expansion
84
Figure 4-7 Stand Alone Mode
84
System Interrupts
85
Figure 4-8 Routing of Interrupt Sources
85
Clock Distribution
86
Figure 4-9 CPCI-6200 Clock Distribution Diagram
86
MPC8572 System Clock
87
Reset Control Logic
87
Table 4-2 System Clock Frequencies
87
Abort/Reset Switch
89
Reset Timing
90
Table 4-5 Reset Timing Requirements
90
RTC Battery
91
IPMI Controller
91
Programming the IPMI Firmware
92
Programmable Devices
93
Table 4-6 Programming Devices
93
Local Bus Control CPLD
94
Reset CPLD
94
CPCI Control CPLD
94
Serial Multiplexer CPLD
94
Motload Firmware
95
Overview
95
Motload Description
95
Motload Implementation and Memory Requirements
95
Motload Commands
96
Motload Utility Applications
96
Motload Tests
96
Using Motload
97
Command Line Interface
97
Command Line Help
99
Command Line Rules
99
Motload Command List
100
Table 5-1 Motload Commands
100
Control Via IPMI
107
Standard IPMI Commands
107
Global IPMI Commands
107
Watchdog Commands
107
Table 6-1 Supported Global IPMI Commands
107
Table 6-2 Supported Watchdog Commands
107
IPMI Messaging Commands
108
SEL Device Commands
108
Table 6-3 Supported Watchdog Commands
108
Table 6-4 Supported SEL Device Commands
108
SDR Repository Commands
109
FRU Inventory Commands
109
Table 6-5 Supported SDR Repository Commands
109
Table 6-6 Supported FRU Inventory Commands
109
Sensor Device Commands
110
Table 6-7 Supported Sensor Device Commands
110
Chassis Device Commands
111
PICMG 2.9 Commands
111
Table 6-8 Supported Chassis Device Commands
111
Table 6-9 Supported PICMG 2.9 Commands
111
Emerson Specific Commands
112
Firmware Upgrade Commands
112
Start Firmware Upgrade
113
Table 6-10 Firmware Upgrade Commands
113
Table 6-11 Response Data of Start Firmware Upgrade
113
Continue Firmware Upgrade
114
Finish Firmware Upgrade
114
Table 6-12 Request Data of Continue Firmware Upgrade
114
Table 6-13 Response Data of Continue Firmware Upgrade
114
OEM Commands
115
Table 6-14 Request Data of Finish Firmware Upgrade
115
Table 6-15 Response Data of Finish Firmware Upgrade
115
BMC/PM Change Role
116
Get Geographical Address
116
Table 6-17 Request Data of BMC/PM Change Role
116
Table 6-18 Response Data of BMC/PM Change Role
116
Table 6-19 Request Data of Get Geographical Address
117
Table 6-20 Response Data of Get Geographical Address
117
FRU Information
118
Sensor Description
118
Table 6-21 FRU Information CPCI-6200
118
Table 6-22 IPMI Sensors Overview
118
Table 4-3 Table
119
Table 6-26 Table
119
Table 6-30 Table
119
Table 6-34 Table
119
Table 6-36 Table
119
Table 6-38 Table
119
Table 6-24 Aggregate V Sensor
121
Table 6-28 Ejector Switch Sensor
124
Table 6-29 Max1617Temp Sensor
125
Table 6-32 Signal Status Sensor
128
Memory Maps and Addresses
137
Default Processor Memory Map
137
Table 7-1 Default Processor Address Map
137
CPCI-6200 Memory Map
138
Table 7-2 CPCI-6200 Address Memory Map
138
Figure 7-1 CPCI-6200 Memory Map Diagram
138
Local Bus Controller Memory Map
139
Table 7-3 LBC Memory Map and Chip Select Assignments
139
System I/O Memory Map
140
Table 7-4 System I/O Memory Map
140
System Status Register
143
Table 7-5 System Status Register, 0Xf200_0000
143
Table 7-6 System Status Register Field Definition
143
System Control Register
144
Table 7-7 System Control Register, 0Xf200_0001
144
Front Panel Leds Control and Status Register
145
Table 7-8 System Control Register Field Definition
145
Table 7-9 Front Panel LED Control/Status Register, 0Xf200_0002
145
NOR Flash Control and Status Register
146
Table 7-10 Front Panel LED Control/Status Register Field Definition
146
Table 7-11 nor Flash Control/Status Register, 0Xf200_0003
146
Table 7-12 nor Flash Control/Status Register Field Definition
146
Interrupt Register 1
148
Table 7-13 Interrupt Register 1, 0Xf200_0004
148
Table 7-14 Interrupt Register 1 Field Definition
148
Interrupt Register 2
149
Table 7-15 Interrupt Register 2, 0Xf200_0005
149
Table 7-16 Interrupt Register 2 Field Definition
149
Interrupt Mask Register
150
Table 7-17 Interrupt Mask Register, 0Xf200_0006
150
Table 7-18 Interrupt Mask Register
150
Presence Detect Register
151
Table 7-19 Presence Detect Register, 0Xf200_0008
151
Table 7-20 Presence Detect Register Field Definition
152
NAND Flash Chip 1 Control Register
153
Table 7-21 NAND Flash Chip 1 Control Register, 0Xf200_0010
153
Table 7-22 NAND Flash Chip 1 Control Register Field Definition
153
NAND Flash Chip 1 Select Register
154
Table 7-23 NAND Flash Chip 1 Select Register, 0Xf200_0011
154
Table 7-24 NAND Flash Chip 1 Select Register Field Definition
154
NAND Flash Chip 1 Presence Register
155
Table 7-25 NAND Flash Chip 1 Presence Register, 0Xf200_0012
155
NAND Flash Chip 1 Status Register
156
Table 7-26 NAND Flash Chip 1 Presence Register Field Definition
156
Table 7-27 NAND Flash Chip 1 Status Register, 0Xf200_0013
156
Table 7-28 NAND Flash Chip 1 Status Register Field Definition
156
NAND Flash Chip 2 Control Register
157
Table 7-29 NAND Flash Chip 2 Control Register, 0Xf200_0014
157
Table 7-30 NAND Flash Chip 2 Control Register Field Definition
157
NAND Flash Chip 2 Select Register
158
Table 7-31 NAND Flash Chip 2 Select Register, 0Xf200_0015
158
Table 7-32 NAND Flash Chip 2 Select Register
158
NAND Flash Chip 2 Presence Register
159
Table 7-33 NAND Flash Chip 2 Presence Register, 0Xf200_0016
159
Table 7-34 NAND Flash Chip 2 Presence Register Field Definition
159
NAND Flash Chip 2 Status Register
160
Table 7-35 NAND Flash Chip 2 Status Register, 0Xf200_0017
160
Table 7-36 NAND Flash Chip 2 Status Register Field Definition
160
CPCI Control and Status Register
161
Table 7-37 CPCI Control/Status Register, 0Xf200_0018
161
Table 7-38 CPCI Control/Status Register Field Definition
161
Geographic Address Read Register
162
Table 7-39 Geographic Address Read Register, 0Xf200_0019
162
Watchdog Timer Load Register
163
Table 7-40 Geographic Address Read Register Field Definition
163
Table 7-41 Watchdog Timer Load Register, 0Xf200_0020
163
Watchdog Timer Control Register
164
Table 7-42 Watchdog Timer Control Register, 0Xf200_0024
164
Table 7-43 Watchdog Timer Control Register Field Definition
164
Watchdog Timer Resolution Register
165
Table 7-44 Watchdog Timer Resolution Register, 0Xe200_0025
165
Table 7-45 Watchdog Timer Resolution Register
165
Watchdog Timer Count Register
166
Table 7-46 Watchdog Timer Counter Register, 0Xf200_0026
166
PLD Revision Register
167
Table 7-47 PLD Revision Register, 0Xf200_0030
167
Table 7-48 PLD Revision Register Field Definition
167
PLD Date Code Register
168
Test Register 1
168
Table 7-49 PLD Date Code Register, 0Xf200_0034
168
Table 7-50 PLD Date Code Register Field Definition
168
Table 7-51 Test Register 1, 0Xf200_0038
168
Test Register 2
169
External Timer Registers
169
Prescaler Register
169
Table 7-52 Test Register 2, 0Xf200_003C
169
Table 7-53 Prescaler Register, 0Xe202_0000
169
Control Registers
170
Table 7-54 Tick Timer Control Registers
170
Table 7-55 Tick Timer Control Field Definition
170
Compare Registers
171
Table 7-56 Tick Timer Compare Registers
171
Counter Registers
172
Table 7-57 Tick Timer Counter Register
172
Interrupt Controller
173
Table 7-58 Interrupt Assignments
173
I2C Device Addresses
174
Figure 7-2 PCI Interrupt Mapping to Processor
174
PCI/PCI-X Configuration
175
Table 7-59 I2C Bus Device Addressing
175
PCI IDSEL and Interrupt Assignment
176
PCI Vendor and Device Ids
176
Table 7-60 IDSEL and Interrupt Mapping for PCI Devices
176
Table 7-61 Planar PCI Device Identification
176
PCI Arbitration Assignments
177
A Replacing the Battery
179
Battery Location
179
Replacing the Battery
180
B Related Documentation
181
Emerson Network Power - Embedded Computing Documents
181
Table B-1 Related Publications
181
Manufacturer's Publications
182
Manufacturers' Publications
182
Related Specifications
183
Safety Notes
185
Sicherheitshinweise
189
Index
193

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