Page 1 DesignWare ARC AXC003 CPU Card User Guide Version 6323-018 May 2017...
Page 2 © 2017 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Page 3: Table Of Contents
List of Tables ............................9 1 Package Contents ..........................10 1.1 DesignWare ARC AXS103 Software Development Platform ........... 10 1.2 DesignWare ARC AXC003 CPU Card (Standalone) ..............11 2 Getting Started ..........................12 2.1 Mounting the CPU Card ......................12 2.2 Performing a Self-Test ......................
Page 4 DesignWare ARC AXC003 CPU Card User Guide Contents Debug ..........................49 Control Registers ......................50 GPIO Registers ......................... 52 DIP Switches for FPGA Image Selection ................55 ARC HS34 Emulation ......................56 6.8 Memories on the AXC003 CPU Card ..................57 6.9 Power Supply ...........................
Page 5 Contents DesignWare ARC AXC003 CPU Card User Guide Executing the Linux Image with U-Boot ................100 8.8 ARCv2 Instruction Set: Usage Limitations ................107 9 Software Interfaces ........................108 9.1 Clock-Generation Registers ....................108 TUNNEL PLL ........................108 ARC PLL ......................... 111 9.2 AXI Tunnel Address Decoder Registers .................
Page 6 DesignWare ARC AXC003 CPU Card User Guide Contents Glossary and References ......................... 144 Glossary ............................144 References ............................ 145 Synopsys, Inc. Version 6323-018 May 2017...
Page 7: List Of Figures
List of Figures DesignWare ARC AXS103 Software Development Platform ............10 DesignWare ARC AXC003 CPU Card .................... 11 Location of the ARC SDP Mainboard Power Supply and Power Switch ......... 13 ARC SDP Mainboard Status LEDs After Power-On ............... 13 AXC003 CPU Card Power-Control LEDs After Power-On ..............
Page 8 DesignWare ARC AXC003 CPU Card List of Figures Creating a New Process ......................... 90 Debugger options – Command-Line Options .................. 91 Debugger Options – Target Selection ..................... 92 Specifying a Path to the .elf File ...................... 92 Debugger Status ..........................93 HyperTerminal Output ........................
Page 9: List Of Tables
GPIO port A Output Register (GPIO_SWPORTA_DR) ..............127 Table 42 GPIO port B output Register (GPIO_SWPORTB_DR) ..............128 Table 43 GPIO Port A Input Register (GPIO_EXT_PORTA) ............... 129 Table 44 GPIO Port B Input Register (GPIO_EXT_PORTB) ............... 130 Version 6323-018 Synopsys, Inc. May 2017...
Page 10: Package Contents
Platform The DesignWare ARC AXS103 Software Development Platform package contains the following items: DesignWare ARC AXC003 CPU Card mounted on ARC SDP Mainboard 100-240V AC power adapter (including power cables for U.S., UK, and EU outlets) USB cable Pen-sized plastic dipstick for actuating DIP switches...
Page 11: Designware Arc Axc003 Cpu Card (Standalone)
DesignWare ARC AXC003 CPU Card (Standalone) DesignWare ARC AXC003 CPU Card User Guide 1.2 DesignWare ARC AXC003 CPU Card (Standalone) The DesignWare ARC AXC003 CPU Card package contains the DesignWare ARC AXC003 CPU Card printed circuit board. DesignWare ARC AXC003 CPU Card Warning The AXC003 CPU Card contains static-sensitive devices.
Page 12: Getting Started
3. Connect the ARC SDP Mainboard to your PC by connecting the USB cable to the USB data port of the Mainboard and the PC. 4. Connect the power supply to the ARC SDP Mainboard and switch on the Mainboard. Synopsys, Inc. Version 6323-018 May 2017...
Page 13: Location Of The Arc Sdp Mainboard Power Supply And Power Switch
Performing a Self-Test DesignWare ARC AXC003 CPU Card User Guide Location of the ARC SDP Mainboard Power Supply and Power Switch 5. Install PuTTY on your computer as described in Appendix The FPGA on the ARC SDP Mainboard is now configured automatically and the Mainboard executes the reset sequence.
Page 14: Axc003 Cpu Card Power-Control Leds After Power-On
DesignWare ARC AXC003 CPU Card User Guide Performing a Self-Test AXC003 CPU Card Power-Control LEDs After Power-On “Self-Tests” 8. Perform the self-test for one or both CPU cores as described in the section on page 19. “Bare-Metal For the next steps, see Package”...
Page 15: Default Board Settings
3.1 Default Jumper Settings on the AXC003 CPU Card The jumpers on the AXC003 CPU Card must be set according to Figure 6. Default Jumper Settings on the AXC003 CPU Card JP801 SW802 JP120x JP1314 JP1307 Version 6323-018 Synopsys, Inc. May 2017...
Page 16: Default Boot-Mode Settings On The Arc Sdp Mainboard
DesignWare ARC AXC003 CPU Card User Guide Default Boot-Mode Settings on the ARC SDP Mainboard 3.2 Default Boot-Mode Settings on the ARC SDP Mainboard The DIP switches on the ARC SDP Mainboard are set according to Figure 7. All cores are configured to boot from the internal ROM and automatically start the pre- bootloader application after reset.
Page 17: Cpu Core Selection
Emulation” on page 56. Bits 1 to 3 of SW2503 select a dual-core configuration ARC HS38x2. “Usage of the For the detailed description of DIP switches used for configuration, see Mainboard DIP Switches” on page 59. Version 6323-018 Synopsys, Inc. May 2017...
Page 18: Arc Hs36 Cpu
DesignWare ARC AXC003 CPU Card User Guide Core Selection ARC HS36 CPU To select ARC HS36 use following settings: SW802 – Bit 6 of SW2501 – Bits 1 to 2 of SW2503 – ARC HS34 CPU To select ARC HS34, use following settings: SW802 –...
Page 19: Self-Tests
SPI flash and runs it if found. Bit 7 “Boot start mode”: Start ARC core manually. Run the self-test for a particular CPU by pushing the corresponding CPU Start button listed in Table 1. Version 6323-018 Synopsys, Inc. May 2017...
Page 20: Table 1 Self-Test Start Buttons
DesignWare ARC AXC003 CPU Card User Guide Self-Test Overview Table 1 Self-Test Start Buttons CPU Core CPU Start Button Location ARC HS36 SW2504 ARC HS38x2 Reserved SW2506 Reserved SW2505 Reserved SW2507 The self-test accesses the peripherals of the peripheral subsystem that is implemented in the FPGA on the ARC SDP Mainboard.
Page 21: Location Of The Cpu Leds On The Arc Sdp Mainboard
Self-Test Overview DesignWare ARC AXC003 CPU Card User Guide Location of the CPU LEDs on the ARC SDP Mainboard Location of the LED121x on the AXC003 CPU Card The seven-segment displays on the ARC SDP Mainboard show the characters listed in Table The number indicates the ARC core that is currently running.
Page 22: Executing The Self-Test Of The Arc Hs36 Core
DesignWare ARC AXC003 CPU Card User Guide Executing the Self-Test of the ARC HS36 Core The expected results for each test are described in Executing the Self-Test of the ARC HS36 Core and Executing the Self-Test of the ARC HS38x2 Core on page 23.
Page 23: Executing The Self-Test Of The Arc Hs38X2 Core
Executing the Self-Test of the ARC HS38x2 Core DesignWare ARC AXC003 CPU Card User Guide 6. Observe the output in the console, which should look similar to the console output shown in Figure 12. ARC HS36 Self-Test 7. Observe the walking patterns shown by the CPU LEDs and the LED0121x LEDs.
Page 24: Location Of The Arc Sdp Mainboard's Power Supply And Power Switch
DesignWare ARC AXC003 CPU Card User Guide Executing the Self-Test of the ARC HS38x2 Core Location of the ARC SDP Mainboard’s Power Supply and Power Switch 3. Launch PuTTY on your computer 4. Push the CPU Start button SW2504 on the ARC SDP Mainboard.
Page 25: Restoring The Self-Tests In The Spi Flash
Restoring the Self-Tests in the SPI Flash DesignWare ARC AXC003 CPU Card User Guide 6. Observe the output in the console, which should be similar to the console output shown in Figure 16. Screen-Shot of ARC HS38x2 Self-Test 7. Observe the walking patterns shown by the CPU LEDs and the LED0121x LEDs.
Page 26 DesignWare ARC AXC003 CPU Card User Guide Restoring the Self-Tests in the SPI Flash 1. If have done earlier, download unzip axs103_software_.zip file from the ARC SDP download webpage install the axs_comm tool as described in the ARC SDP Mainboard User Guide [5].
Page 27: Hardware Functional Description
The AXS103 Software Development Platform is HAPS compliant and enables the use of high- frequency ARC CPU cores as a daughter card for HAPS, allowing full SoC prototyping. Figure 18 Figure 19 show the hardware block diagrams of the AXC003 CPU card. Version 6323-018 Synopsys, Inc. May 2017...
Page 28: Hardware Block Diagram (Hs36)
DesignWare ARC AXC003 CPU Card User Guide Board Overview Hardware Block Diagram (HS36) AXC003 CPU Card FPGA (Mictor38) Real-Time Ashling / Lauterbach ARC HS36 Trace Mode core Jumpers Data Instr. FPGA Flash AXI - Interconnect 16 MByte Tunnel SRAM AXI / APB...
Page 29: Hardware Block Diagram (Hs38X2)
Board Overview DesignWare ARC AXC003 CPU Card User Guide Hardware Block Diagram (HS38x2) AXC003 CPU Card FPGA (Mictor38) Real-Time ARC HS38x2 Ashling / Lauterbach Trace Mode core Jumpers 512kByte L2 FPGA Flash AXI - Interconnect 16 MByte Tunnel SRAM AXI / APB...
Page 30: Board Interface Overview
DesignWare ARC AXC003 CPU Card User Guide Board Interface Overview 6.2 Board Interface Overview The AXC003 CPU Card has two female HapsTrak II connectors and a female 18-pin power- supply connector on the bottom of the card. These connectors are provided for mounting the AXC003 CPU Card on the ARC SDP Mainboard.
Page 31: Hapstrak Ii Connectors (Top)
Jumpers DesignWare ARC AXC003 CPU Card User Guide HapsTrak II Connectors (Top) A HAPS logic analyzer card can be connected to the HapsTrak II connectors at the top side of the AXC003 Processor FPGA. This setup can be used to observe the signals of the AXI tunnel between the AXC003 CPU Card and the ARC SDP Mainboard, for example.
Page 32: Leds
DesignWare ARC AXC003 CPU Card User Guide LEDs Jumper Setting Description Name JP1206 Normal Operation JP1205 JP1204 JP1203 JP1202 JP1201 Others Reserved 6.4 LEDs The AXC003 CPU Card features six green power control LEDs and eight green LEDs for user applications.
Page 33: Pushbutton
Pushbutton DesignWare ARC AXC003 CPU Card User Guide segment is 0xF000_0000 such that the default address of the register is 0xF000_300C (see “System Memory Map After Pre-Bootloader Execution”). Table 4 LED Control Bits Control Bit Description SWPORTB_DR[8] Connected to LED0 on the AXC003 CPU Card.
Page 34: Seven-Segment Displays
DesignWare ARC AXC003 CPU Card User Guide Seven-Segment Displays Normally you do not need to do this step manually. The FPGA configuration is initialized automatically at power-on. Location of the Pushbutton on the AXC003 CPU Card FPGA Configuration 6.6 Seven-Segment Displays...
Page 35: Axc003 Processor Fpga Overview
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Table 5 Control Bits of the Seven-Segment Displays Control Bit Description SWPORTB_DR[23:16] Controls the upper seven-segment display. A segment of the display is ON when its control bit is set to 1.
Page 36: Table 6 Main Features Of The Arc Cores
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview Table 6 Main Features of the ARC Cores Feature ARC HS36 ARC HS38x2 Number of cores I-Cache (bytes) Associativity 2-way 4-way Cache-line size 32 bytes 64 bytes D-Cache (bytes)
Page 37: Pae
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Feature ARC HS36 ARC HS38x2 Maximum 100 MHz 100 MHz CPU frequency The ARC HS38x2 core supports Physical Address Extension (PAE). PAE extends the physical address range beyond the core’s native 32-bit, 4GByte address range. In the AXC003, the PAE functionality is used to extend the physical address range from 4 to 8 GByte.
Page 38: I/O Coherency
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview I/O Coherency AXC003 I/O Coherency Architecture HS38 HS38 coherent DMA traffic ICCM DCCM ICCM DCCM filtering of coherent and non-coherent DMA ICACHE DCACHE ICACHE DCACHE traffic based its on...
Page 39: Interrupts
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide I/O Coherency and PAE 0x1_FFFF_FFFF 0x1_8000_0000 0x1_0000_0000 slv = ioc / offset = 15 slv = ioc / offset = 15 2GByte slv = ioc / offset = 14...
Page 40 DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview The ICTL module combines the interrupt requests from the on-chip interrupt sources into a single interrupt request for each ARC processor. Dual-core HS38x2 has cross-core interrupts between the cores instantiated in the inter-core interrupt unit.
Page 41: Hs36 Interrupt Architecture
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide HS36 Interrupt Architecture Version 6323-018 Synopsys, Inc. May 2017...
Page 42: Hs38X2 Interrupt Architecture
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview HS38x2 Interrupt Architecture Each ARC core is configured with 8 external interrupt inputs. The interrupt mapping of the two ARC cores is listed in Table 7 on page 43 and Table 8 on page 44.
Page 43: Table 7 Interrupt Mapping For Arc Hs36
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Table 7 Interrupt Mapping for ARC HS36 Interrupt Interrupt source Remarks ARC internal interrupt reset memory error instruction error timer0 timer1 Reserved Combined interrupt The interrupt request is received by the ICTL...
Page 44: Table 8 Interrupt Mapping For Arc Hs38
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview Table 8 Interrupt Mapping for ARC HS38 Interrupt Interrupt source Remarks ARC internal interrupt reset memory error instruction error timer0 timer1 Reserved Cross-core Interrupt The interrupt request from Inter-core Interrupt...
Page 45: Table 9 Mainboard Ictl Interrupt Mapping
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide In each core of HS38x2, interrupts 24…27 are controlled by the interrupt distribution unit. For more information about the interrupt distribution unit, see the ARConnect Databook provided with the ARConnect IP.
Page 46: Clock
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview Interrupt Source ICTL_MB INT_STATUS Register Bit HAPS Extension 1 interrupt (signal HE_intr[1] at connector) Clock The AXC003 CPU Card has two clock inputs from which all other clocks are derived internally:...
Page 47: Clock Architecture
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Clock Architecture Version 6323-018 Synopsys, Inc. May 2017...
Page 48: Reset
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview Table 10 Clock Frequencies Clock Clk Frequency (MHz) Run-Time Programmable Maximu After Reset After Pre- Boot AMBA apb_clk axi_clk ddr_ref_clk TUNNEL tunnel_clk UART uart_ref_clk arc_clk 100 / 1) Fmax for HS36 and HS38x2...
Page 49: Debug
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide The AXC003 Processor FPGA includes a pushbutton labeled SW801 CONF. This Note pushbutton is for reconfiguring the CPU card FPGA. Pushing this button forces loading the ARC CPU image to the FPGA, depending on the SW802 dipswitch settings Debug The ARC cores provide debug access using an IEEE 1149.1 JTAG port.
Page 50: Control Registers
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview Control Registers The CREG peripheral inside the AXC003 Processor FPGA provides software registers to control the following features: System memory map (see System Memory Map on page 65) Boot mode (see...
Page 51 AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Name Address Offset Description ARC CPU Address Decoder Registers CPU_A_SLV_SEL0 0x0000_1020 Slave select register for ARC CPU_A_SLV_SEL1 0x0000_1024 Slave select register for ARC CPU_A_SLV_OFFSET0 0x0000_1028 Address offset register for...
Page 52: Gpio Registers
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview Name Address Offset Description AXI Tunnel Registers TUN_CTRL 0x0000_14A0 AXI tunnel control register TUN_STAT 0x0000_14A4 AXI tunnel status register GPIO Registers The GPIO peripheral in the AXC003 Processor FPGA uses DesignWare dw_apb_gpio IP and provides two GPIO ports.
Page 53: Table 15 Gpio Port A Input Register Function (Ext_Porta)
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Description Connected to LED2502 of the ARC SDP Mainboard The LED is ON when this bit is set to 1. Reserved Connected to LED2503 of the ARC SDP Mainboard.
Page 54: Table 16 Gpio Port B Output Register Function (Swportb_Dr)
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview Table 16 GPIO port B Output Register Function (SWPORTB_DR) Description Reserved Connected to LED0 on the AXC003 CPU Card. The LED is ON when this bit is set to 1.
Page 55: Dip Switches For Fpga Image Selection
AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Description 31:24 Controls the lower seven-segment display on the AXC003 CPU Card. A segment of the display is ON when its control bit is set to 1. Table 17...
Page 56: Arc Hs34 Emulation
DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview 10 – Reserved 11 – Reserved ARC HS34 Emulation The HS36 configurations on the AXC003 CPU card also have closely coupled memories: 256k ICCM and 256k DCCM. This configuration can be used for an emulation of HS34 cores and for working with software packages built and compiled for HS34.
Page 57: Memories On The Axc003 Cpu Card
Memories on the AXC003 CPU Card DesignWare ARC AXC003 CPU Card User Guide Table 19 Memory mapping for HS34 Emulation 0xFFFF_FFFF AXI2APB on AXC003 CPU Card (CREG) 0xF000_0000 0xEFFF_FFFF AXI2APB on Mainboard 0xE000_0000 0xDFFF_FFFF AXI Tunnel Slave for HAPS System...
Page 58: Power Supply
DesignWare ARC AXC003 CPU Card User Guide Power Supply The ARC SDP Mainboard provides additional global memories. 6.9 Power Supply Power is supplied to the AXC003 CPU Card by the ARC SDP Mainboard using the power supply connector on the bottom side of the AXC003 CPU Card. The following voltage levels are provided: 1.1V, 1.8V, 2.5V, 3.3V, and 12.0V.
Page 59: Audio Support
Audio Support DesignWare ARC AXC003 CPU Card User Guide Pinout of the Power Supply Connector (Bottom View) For each supply voltage of the AXC003 CPU Card a power-control LED indicates that the supply voltage is present. In normal operation all six LEDs shine green. The location of these LEDs is shown in Figure 32.
Page 60: Table 21 Arc Core Boot Configuration (Mainboard Dip Switch Sw2501)
DesignWare ARC AXC003 CPU Card User Guide Usage of ARC SDP Mainboard Resources Note When a DIP switch is in the right position ( ), the corresponding bit in the control register is When a DIP switch is in the left position (...
Page 61: Table 22 Multicore Configuration (Mainboard Dip Switch Sw2503)
Usage of ARC SDP Mainboard Resources DesignWare ARC AXC003 CPU Card User Guide Table 22 Multicore Configuration (Mainboard DIP Switch SW2503) Description Boot core select Switch Position Boot Core HS38x2_0 or HS36 HS38x2_1 Reserved Reserved Multicore mode Switch Position Multicore mode...
Page 62: Usage Of The Mainboard Pushbuttons
DesignWare ARC AXC003 CPU Card User Guide Usage of ARC SDP Mainboard Resources Figure 33 shows the function and default settings of the DIP Switches on the ARC SDP Mainboard, which are used by the AXC003 CPU Card. Function and Default Settings of the DIP Switches on the ARC SDP Mainboard.
Page 63: Usage Of The Mainboard Leds
Usage of ARC SDP Mainboard Resources DesignWare ARC AXC003 CPU Card User Guide Table 23 shows the usage of the CPU Start buttons of the ARC SDP Mainboard to start code execution on the individual cores. Figure 34 shows the location of the CPU Start buttons on the ARC SDP Mainboard.
Page 64: Location Of The Cpu Leds On The Arc Sdp Mainboard
DesignWare ARC AXC003 CPU Card User Guide Usage of ARC SDP Mainboard Resources Table 24 Control Bits of the CPU LEDs on the ARC SDP Mainboard Control Bit Description SWPORTA_DR[0] Controls LED2501 SWPORTA_DR[1] Controls LED2502 SWPORTA_DR[5] Controls LED2503 SWPORTA_DR[6] Controls LED2504...
Page 65: System Memory Map
ARC CPU Memory Map After Pre-Bootloader Execution Master Address Selected Slave Slave Address AXI2APB 0xFFFF_FFFF 0x0FFF_FFFF on AXC003 CPU Card 0xF000_0000 0x0000_0000 AXI2APB 0xEFFF_FFFF 0x0FFF_FFFF on Mainboard 0xE000_0000 0x0000_0000 AXI Tunnel Slave 0xDFFF_FFFF 0xDFFF_FFFF for HAPS System 0xD000_0000 0xD000_0000 Version 6323-018 Synopsys, Inc. May 2017...
Page 66 DesignWare ARC AXC003 CPU Card User Guide System Memory Map After Pre-Bootloader Execution Master Address Selected Slave Slave Address 0xCFFF_FFFF 256K DCCM 0xC000_0000 0xBFFF_FFFF 0x3FFF_FFFF DDR3 SDRAM 0x8000_0000 0x0000_0000 0x7FFF_FFFF0 Unused x4000_0000 0x3FFF_FFFF 0x0FFF_FFFF 0x3000_0000 on AXC003 CPU Card 0x0000_0000...
Page 67: Controlling The Memory Map
Controlling the Memory Map DesignWare ARC AXC003 CPU Card User Guide Table 26 AXI Tunnel Memory Map After Pre-Bootloader Execution (ARC HS34 / HS36) Master Address Selected Slave Slave Address 0xFFFF_FFFF 0x7FFF_FFFF DDR3 SDRAM 0x8000_0000 0x0000_0000 0x7FFF_FFFF 0x7FFF_FFFF DDR3 SDRAM...
Page 68: Setting Up The Axi Masters On The Arc Sdp Mainboard
DesignWare ARC AXC003 CPU Card User Guide Controlling the Memory Map Table 28 AXC003 CPU Card Target Slaves Slave Number Target Slave No slave selected (default slave provides response) DDR controller SRAM controller AXI tunnel AXI2APB bridge Internal ROM controller...
Page 69: Example Register Settings For The Default Memory Map
Controlling the Memory Map DesignWare ARC AXC003 CPU Card User Guide AXC003 CPU Card. For TUNNEL1 the address issued by the AXI tunnel master on the HAPS system is decoded according to your custom design. Example Register Settings for the Default Memory Map...
Page 70: Table 31 Memory Map Pre-Boot Programming For All Masters On The Arc Sdp Mainboard
DesignWare ARC AXC003 CPU Card User Guide Controlling the Memory Map address 0xE000_0000 the AXI tunnel is selected. The AXI Master on the other side of the tunnel issues the address 0xE000_0000 and thus selects the AXI2APB bridge of the Mainboard’s peripheral area.
Page 71: Memory Map Of The Local Peripherals
Memory Map of the Local Peripherals DesignWare ARC AXC003 CPU Card User Guide Likewise, the slave address of the AXI TUNNEL1 slave on the ARC SDP Mainboard is forwarded to the AXI Tunnel master on the HAPS system. It is then decoded according to your custom design.
Page 72: Programmer's Reference
For this purpose, each 256 MB aperture of the memory map can be designated as a boot mirror. the reset vector address is programmable at run time through the INT_VECTOR_BASE register, and may be set to any 1KB aligned address. Synopsys, Inc. Version 6323-018 May 2017...
Page 73: Arc Hs36 Booting From Iccm0
Boot Modes DesignWare ARC AXC003 CPU Card User Guide The boot-mirror configuration options are described in Usage of the Mainboard DIP Switches on page 59. The default values of the boot-mirror switches are listed in Default Boot-Mode Settings on the ARC SDP Mainboard on page 16.
Page 74: Pre-Boot
DesignWare ARC AXC003 CPU Card User Guide Pre-Boot boot from ICCM0 with debugger 1) Select boot mode and boot mirror via the CPU DIP switches on the Mainboard Boot mode is “start ARC core with the debugger” Boot mirror is arbitrary...
Page 75: Default Settings Of The Dip Switches On The Arc Sdp Mainboard
Pre-Boot DesignWare ARC AXC003 CPU Card User Guide Default settings of the DIP Switches on the ARC SDP Mainboard During the board initialization, the pre-bootloader programs the clock dividers and the system memory map and initializes the DDR3 SDRAM. The pre-bootloader supports loading an application image from the SPI-flash on the ARC SDP Mainboard into the SRAM or the DDR3 SDRAM memory of the AXC003 CPU Card.
Page 76: Pre-Boot Mechanism
DesignWare ARC AXC003 CPU Card User Guide Pre-Boot As an example Figure 37 shows how the pre-bootloader loads an image from the SPI-flash on the ARC SDP Mainboard to the DDR3 SDRAM on the AXC003 CPU Card. Pre-Boot Mechanism The pre-bootloader uses the seven-segment displays on the Mainboard to show status information.
Page 77: Drivers
Drivers DesignWare ARC AXC003 CPU Card User Guide . (dot) Pre-Bootloader not yet executed. Check the DIP switch settings and press a CPU start button. Table 34 Meaning of the Right Character of the Seven-Segment Display Error Code Description No error...
Page 78: Drivers For Mqx
DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package Within the /io directory: Subdirectories with the _axs1xx postfix contain specific drivers for IP located in the peripheral subsystem on the ARC SDP Mainboard. Subdirectories with the _axc003 postfix contain specific drivers for peripherals on the AXC003 CPU Card.
Page 79: Building Bare-Metal Applications Using The Metaware Ide
Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide /apps This folder contains individual subdirectories for all application examples. See the release notes on the ARC SDP download webpage for an overview of the available application examples. /board This folder contains board-specific header files. Also, it contains linker files that specify the definition of the memory map, located in the /board/axs103/src/ folder.
Page 80: Metaware Ide - Select Workspace Directory
DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package MetaWare IDE - Select Workspace Directory 2. Open the workspace, and select “File – Import” from the top menu. 3. Expand the General folder, then select Existing Projects into Workspace and click the Next button MetaWare IDE –...
Page 81: Metaware Ide - Set Active Build Configurations
Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide 5. Select all projects available there for import, and click Finish. The IDE loads and displays the example projects in your workspace. 6. Right-click one or multiple projects (excluding the common project).
Page 82: Metaware Ide - Build Results In Console Window
DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package Variable Value Description AXS_CONSOLE_TYPE uart0 Debug console is connected to the UART0 interface at the DB9 connector or at the Pmod 1) 2) connector Debug console is connected to the UART1...
Page 83: Building Bare-Metal Applications Using Gmake
Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide Building Bare-Metal Applications Using gmake The batch script build.bat can be used to build the applications. This script is based on gmake. It executes gmake, passing variables according to the command line options provided.
Page 84 DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package 1) This connector is located on the ARC SDP Mainboard. 2) In order to use the Pmod connectors, the PMOD_MUX_CTRL register (see the ARC SDP Mainboard User Guide [5]) needs to be modified.
Page 85: Hardware Setup For Debugging
Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide selftest_axs103_ram_uart0_archs36.* selftest_axs103_ram_uart0_archs36_hostlink.* Hardware Setup for Debugging Follow the steps below to execute a sample application in a debugger: 1. Set the jumpers to their default settings (see Jumpers on page 31). The JTAG interface is in daisy-chained mode.
Page 86: Location Of The Debug Interfaces And The Corresponding Jumpers
DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package the ARC SDP Mainboard. If you are using a Lauterbach probe, also remove the jumpers JP2309 and JP2310. Location of the Debug Interfaces and the Corresponding Jumpers 4. Switch on the power supply or push the RESET button.
Page 87: Running A Bare-Metal Application In The Metaware Ide Debugger
Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide bootloader then automatically initializes the DDR3 SDRAM memory and sets the ARC core frequency correctly, but bypasses loading an image from the SPI Flash. Location of the CPU Start Buttons on the ARC SDP Mainboard.
Page 88 DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package 6. Double click C/C++ Application to create a new debug configuration for the project or select an existing debug configuration. 7. Select the Main tab and enter a name of your choice in the Name field. It is best to compose the name from the project name and the ARC core.
Page 89 Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide 11. In Command-line Options > Debugger Options, set a property to select the correct core and device: -prop=cpunum=1 Select ARC HS34 core -prop=cpunum=1 Select ARC HS36 core -prop=cpunum=1 Select ARC HS38x2 core 1...
Page 90: Running A Bare-Metal Application In The Metaware Debugger
DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package -prop=dig_device=JtagHs2 depending on the type of your probe. 12. Click the Debug button in the Debug configurations dialog. The IDE switches to the Debug perspective and initiates the debug session. Running a Bare-Metal Application in the MetaWare Debugger This section describes how to execute an image with the MetaWare debugger.
Page 91: Debugger Options - Command-Line Options
Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide 6. In Command-line Options > Debugger Options, enter a property to select the correct core and device: -prop=cpunum=1 select the ARC CPU (see Table 39). –prop=dig_device=AXS selects the USB data port...
Page 92: Debugger Options - Target Selection
DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package Debugger Options – Target Selection 8. Back in the Debug a process or processes window, select the correct .elf file and press OK: Specifying a Path to the .elf File The debugger is now ready for executing the image. In the auxiliary register AUX0004, the ARC HS36 ID is visible (red ellipse, 0x553).
Page 93: Debugger Status
Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide Debugger Status Version 6323-018 Synopsys, Inc. May 2017...
Page 94: Storing An Image In The Spi Flash And Running The Application
DesignWare ARC AXC003 CPU Card User Guide Bare-Metal Package 9. Execute the program by clicking run button in the debugger. 10. Observe the output in the console, which should be similar to the screenshot shown in Figure 52: HyperTerminal Output...
Page 95 Bare-Metal Package DesignWare ARC AXC003 CPU Card User Guide archs36.bin For images built for the SRAM use the following command instead: axs_comm -c 0553 -a 00000000 -p 20000000 -f hello_uart_axs103_ram_archs36.bin The parameters used here have the following meanings: 0553 ARC ID of the ARC HS36 processor...
Page 96: Mqx Package
DesignWare ARC AXC003 CPU Card User Guide MQX Package DIP Switch Settings for Autonomous Code Execution on the ARC Core 3. Push the RESET button on the ARC SDP Mainboard The Pre-Bootloader detects a valid image in sector 0 of the SPI flash, loads this image in DDR3 SDRAM and executes it.
Page 97: Building Mqx Applications Using Gmake
MQX Package DesignWare ARC AXC003 CPU Card User Guide Unzip the software package and change to the directory /software/mqx. The directory structure of the mqx folder is shown in Table 40. Table 40 MQX folder Contents Folder Description Root folder path: /software/mqx...
Page 98: Hardware Setup For Debugging
DesignWare ARC AXC003 CPU Card User Guide MQX Package Building the grtc Application for HS38x2 set MQX_ROOT=C:\AXS103\software\mqx set MQX_CONFIG=%MQX_ROOT%\build\axs103\hs38x2_config.mk cd %MQX_ROOT%\examples\axs103\hs38x2\grtc gmake all See the DesignWare MQX RTOS Getting Started manual for more information on how to build MQX applications...
Page 99: Linux And U-Boot Packages
Linux and U-Boot Packages DesignWare ARC AXC003 CPU Card User Guide executables on the corresponding HS38x2cores. To debug the dual-core example application in the GUI, pass debug as an argument to run.bat Running the leds Application Built for HS34 cd %MQX_ROOT\examples\axs103\leds gohs34.bat test...
Page 100: Hardware Setup For Debugging
DesignWare ARC AXC003 CPU Card User Guide Linux and U-Boot Packages If you program the u-boot_axs103.bin file to SPI flash on AXS 103 hardware, set bit 3 on the SW2501 switch to off so that the pre-bootloader looks for the U-Boot in SPI flash. By default, this switch is on and bypasses loading the U-Boot or any application in SPI flash.
Page 101 Linux and U-Boot Packages DesignWare ARC AXC003 CPU Card User Guide serial0@e0022000 Out: serial0@e0022000 Err: serial0@e0022000 Net: Warning: ethernet@e0018000 (eth0) using random MAC address - d2:83:38:6d:af:37 eth0: ethernet@e0018000 AXS# Depending on the bootcmd variable, U-Boot may automatically execute the boot sequence.
Page 102 DesignWare ARC AXC003 CPU Card User Guide Linux and U-Boot Packages OF: fdt:Machine model: snps,axs103-smp earlycon: uart8250 at MMIO32 0xe0022000 (options '115200n8') bootconsole [uart8250] enabled Freq is 100MHz AXS: AXC003 CPU Card FPGA Date: 13-4-2017 AXS: MainBoard v3 FPGA Date: 14-4-2017...
Page 103 Linux and U-Boot Packages DesignWare ARC AXC003 CPU Card User Guide Timers : Timer0 Timer1 ISA Extn : atomic ll64 unalign (not used) : mpy[opt 9] div_rem norm barrel-shift swap minmax swape : full match, cache:512, Predict Table:8192 MMU [v4]...
Page 104 DesignWare ARC AXC003 CPU Card User Guide Linux and U-Boot Packages io scheduler deadline registered io scheduler cfq registered (default) Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled f0005000.dw-apb-uart: ttyS0 at MMIO 0xf0005000 (irq = 6, base_baud = 2083312) is a 16550A e0020000.uart: ttyS1 at MMIO 0xe0020000 (irq = 17, base_baud = 2083333) is a 16550A...
Page 105 Linux and U-Boot Packages DesignWare ARC AXC003 CPU Card User Guide usbhid: USB HID core driver NET: Registered protocol family 17 NET: Registered protocol family 15 ttyS3 - failed to request DMA Freeing unused kernel memory: 10112K This architecture does not have kernel memory protection.
Page 106 DesignWare ARC AXC003 CPU Card User Guide Linux and U-Boot Packages The batch file uses the axs_comm utility described in the ARC SDP Mainboard User Guide [5]. After the flashing process is completed do the following: 1. Set the third pin on dip switch SW2501 in to OFF (otherwise the image from SPI flash is not read).
Page 107: Arcv2 Instruction Set: Usage Limitations
ARCv2 Instruction Set: Usage Limitations DesignWare ARC AXC003 CPU Card User Guide serial0@e0022000 Out: serial0@e0022000 Err: serial0@e0022000 Net: Warning: ethernet@e0018000 (eth0) using random MAC address - b2:80:7f:24:64:c4 eth0: ethernet@e0018000 AXS# Running The following commands run Linux after U-Boot autostart on power-on: setenv bootcmd fatload mmc 0\;...
Page 108: Software Interfaces
HIGHTIME[5:0] sets the amount of time in input cycles that the divided input clock remains high IDIV = LOWTIME + HIGHTIME EDGE chooses the edge that the High Time counter transitions on (0=rising, 1=falling) Synopsys, Inc. Version 6323-018 May 2017...
Page 109 Clock-Generation Registers DesignWare ARC AXC003 CPU Card User Guide BYPASS bypass the input divider NOUPDATE prevent update of the PLL with new settings. Debug only; can be used for register RW test To obtain a 50% duty-cycle the divider shall be programmed as follows: even divider ratio =>...
Page 110 DesignWare ARC AXC003 CPU Card User Guide Clock-Generation Registers 9.1.1.3 TUN_PLL_ODIV Register Reserved NOUPDATE BYPASS EDGE HIGHTIME LOWTIME Address offset: 0x0048 Reset Value: 0x0001_028A (0x0000_0145 after pre-boot) Access: Register for controlling the clock setting for AXI tunnel. LOWTIME[5:0] sets the amount of time in VCO cycles that the output clock remains low...
Page 111: Arc Pll
Clock-Generation Registers DesignWare ARC AXC003 CPU Card User Guide LOCK PLL lock indication 0 = PLL is unlocked 1 = PLL is locked ERROR PLL error indication. Asserted high to to indicate that PLL was programmed with an illegal value. PLL can be re-programmed after the ERROR status...
Page 112 DesignWare ARC AXC003 CPU Card User Guide Clock-Generation Registers odd divider ratio => LOWTIME = HIGHTIME + 1 EDGE = 1 9.1.2.2 ARC_PLL_FBDIV Register Reserved NOUPDATE BYPASS EDGE HIGHTIME LOWTIME Address offset: 0x0084 Reset Value: 0x0000_03CF (0x0000_03CF after pre-boot) Access:...
Page 113 Clock-Generation Registers DesignWare ARC AXC003 CPU Card User Guide Register for controlling the clock setting for the ARC CPU LOWTIME[5:0] sets the amount of time in VCO cycles that the output clock remains low HIGHTIME[5:0] sets the amount of time in VCO cycles that the output clock remains high...
Page 114: Axi Tunnel Address Decoder Registers
DesignWare ARC AXC003 CPU Card User Guide AXI Tunnel Address Decoder Registers 9.2 AXI Tunnel Address Decoder Registers The AXI Tunnel Address Decoder Registers described below are re-programmed by the pre- bootloader. the reset values mentioned here are the reset values prior to running the pre- bootloader.
Page 115: Tun_A_Offset0: Axi Tunnel Address Offset Register 0
AXI Tunnel Address Decoder Registers DesignWare ARC AXC003 CPU Card User Guide Table 2 TUN_A_SLV1 Register Legend: * reset value Name Access Value Description SLV_SEL8 1 / 6* Slave select for address aperture[8] no slave selected slave 1 selected (=> DDR controller) slave 2 selected (=>...
Page 116: Tun_A_Offset1: Axi Tunnel Address Offset Register 1
DesignWare ARC AXC003 CPU Card User Guide AXI Tunnel Address Decoder Registers SLV_OFFSET5 23:20 Address offset for address aperture[5] SLV_OFFSET6 27:24 Address offset for address aperture[6] SLV_OFFSET7 31:28 Address offset for address aperture[7] 1) Same encoding as SLV_OFFSET0 TUN_A_OFFSET1: AXI Tunnel Address Offset Register 1...
Page 117: Arc Cpu Address Decoder Registers
ARC CPU Address Decoder Registers DesignWare ARC AXC003 CPU Card User Guide 0x0* 31:1 Reserved 9.3 ARC CPU Address Decoder Registers The ARC CPU Address Decoder Registers are re-programmed by the pre-bootloader. The reset values mentioned here are the reset values prior to running the pre-bootloader. See the...
Page 118: Cpu_A_Offset0: Arc Cpu Address Offset Register 0
DesignWare ARC AXC003 CPU Card User Guide ARC CPU Address Decoder Registers Table 7 CPU_A_SLV1 Register Legend: * reset value Name Access Value Description SLV_SEL8 Slave select for address aperture[8] no slave selected slave 1 selected (=> DDR controller) slave 2 selected (=> SRAM controller) slave 3 selected (=>...
Page 119: Cpu_A_Offset1: Arc Cpu Address Offset Register 1
ARC CPU Address Decoder Registers DesignWare ARC AXC003 CPU Card User Guide SLV_OFFSET5 23:20 Address offset for address aperture[5] SLV_OFFSET6 27:24 Address offset for address aperture[6] SLV_OFFSET7 31:28 Address offset for address aperture[7] 1) Same encoding as SLV_OFFSET0 CPU_A_OFFSET1: ARC CPU Address Offset Register 1...
Page 120: Arc Rtt Address Decoder Registers
DesignWare ARC AXC003 CPU Card User Guide ARC RTT Address Decoder Registers 9.4 ARC RTT Address Decoder Registers RTT_A_SLV0: ARC RTT Slave Select Register 0 0x1040 Address offset: 0x1111_1111 Reset value: Table 11 RTT_A_SLV0 Register Legend: * reset value Name...
Page 121: Rtt_A_Offset0: Arc Rtt Address Offset Register 0
ARC RTT Address Decoder Registers DesignWare ARC AXC003 CPU Card User Guide SLV_SEL8 no slave selected slave 1 selected (=> DDR controller) slave 2 selected (=> SRAM controller) slave 3 selected (=> AXI tunnel) slave 4 selected (=> AXI2APB bridge) slave 5 selected (=>...
Page 122: Rtt_A_Offset1: Arc Rtt Address Offset Register 1
DesignWare ARC AXC003 CPU Card User Guide ARC RTT Address Decoder Registers RTT_A_OFFSET1: ARC RTT Address Offset Register 1 0x104C Address offset: 0x7654_3210 Reset value: Table 14 RTT_A_OFFSET1 Register Legend: * reset value Name Access Value Description SLV_OFFSET8 Address offset for address aperture[8]...
Page 123: Pae Registers
PAE Registers DesignWare ARC AXC003 CPU Card User Guide 9.5 PAE Registers PAE: PAE Register 0x1060 Address offset: 0x5500_0000 Reset value: Table 16 PAE Register Legend: * reset value Name Access Value Description PAE_0 Physical address extension bits. These bits can be used to remap...
Page 124: Cpu Start Registers
DesignWare ARC AXC003 CPU Card User Guide CPU Start Registers Table 17 PAE_UPDATE Register Legend: * reset value Name Access Value Description UPDATE RW1C The PAE configuration registers is double-buffered. The newly programmed value will be only be forwarded to the IOC port after writing a ‘1’...
Page 125: Cpu_0_Entry: Arc Cpu-0 Kernel Entry Point Register
CPU Start Registers DesignWare ARC AXC003 CPU Card User Guide 1) Reset value for START_MODE is sampled from SW2501[7] pin during power-on-reset on the ARC SDP Mainboard 2) Reset value for CORE_SEL is sampled from SW2503[2:1] pins during power-on-reset 3) Reset value for MULTI_CORE is sampled from SW2503[5:4] pins during power-on-reset...
Page 126: Axi Tunnel Registers
DesignWare ARC AXC003 CPU Card User Guide AXI Tunnel Registers IMAGE_SRC bypass (i.e. ARC core will enter HALT state after pre-boot) SPI FLASH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MODE_HS34 HS36 (Cache enabled) HS34 emulation (Cache disabled) 1) Reset value for MIRROR[1:0] is sampled from SW2501[2:1] pin during power-on-reset 2) Reset value for IMAGE_SRC[1:0] is sampled from SW2501[4:3] pin during power-on-reset 3) Reset value for MODE_HS34 is sampled from SW2501[6] pin during power-on-reset.
Page 127: Gpio Registers
GPIO Registers DesignWare ARC AXC003 CPU Card User Guide Address offset: 0x1_14A4 Reset Value: 0x0000_0000 Access: STAT[3:0] reflects the status of the tunnel after reset completion → initialization sequence done (1=done, 0=not yet done) STAT[0] → initialization sequence error (1=error, 0=no error) STAT[1] →...
Page 128: Gpio_Swportb_Dr: Gpio Port B Output Register
DesignWare ARC AXC003 CPU Card User Guide GPIO Registers MB_LED2507 0x0* LED2507 on the ARC SDP Mainboard is OFF LED2507 on the ARC SDP Mainboard is ON MB_LED2508 0x0* LED2508 on the ARC SDP Mainboard is OFF LED2508 on the ARC SDP Mainboard is ON...
Page 129: Gpio_Ext_Porta: Gpio Port A Input Register
GPIO Registers DesignWare ARC AXC003 CPU Card User Guide UPPER_7SEG 23:16 Controls the upper seven-segment display on the AXC003 CPU Card. A segment of the display is on when its control bit is set to 1. LOWER_7SEG 31:24 Controls the lower seven-segment display. A segment of the display is on when its control bit is set to 1.
Page 130: Gpio_Ext_Portb: Gpio Port B Input Register
DesignWare ARC AXC003 CPU Card User Guide GPIO Registers 0xD* 19:16 Reserved MB_SW2504 CPU Start button SW2504 on the ARC SDP Mainboard pressed 0x1* CPU Start button SW2504 on the ARC SDP Mainboard not pressed MB_SW2506 CPU Start button SW2506 on the ARC SDP...
Page 131 GPIO Registers DesignWare ARC AXC003 CPU Card User Guide Reserved JP1207 Default setting Reserved 31:8 Reserved 1) Reset value depends on jumper settings on the AXC003 CPU Card. Version 6323-018 Synopsys, Inc. May 2017...
Page 132: Mounting The Axc003 Cpu Card
Power Supply Connector and the HapsTrak II connectors for the CPU Card are connected properly. 3. Make sure that the CPU Card specific DIP switches on the ARC SDP Mainboard are set according to Figure 54 on page 133. Version 6323-018 Synopsys, Inc. May 2017...
Page 133: Default Settings Of The Dip Switches On The Arc Sdp Mainboard
GPIO Registers DesignWare ARC AXC003 CPU Card User Guide Default Settings of the DIP Switches on the ARC SDP Mainboard. SW2501 SW2401 ‘1’ ‘0’ ‘1’ ‘0’ Boot Mirror Select Bypass loading Reserved For application purposes Cache mode (HS34/HS36 only) Boot start mode SW2503 ‘1'...
Page 134: Installing And Configuring Putty
The Digilent Adept USB Device Properties windows opens. Select the Hardware tab and take note of the COM port assigned to the USB Serial Port. The example in Figure 55 on page 135 uses the COM6 port: Version 6323-018 Synopsys, Inc. May 2017...
Page 135: Identification Of Com Port
GPIO Registers DesignWare ARC AXC003 CPU Card User Guide Identification of COM Port 5. Execute putty.exe The PuTTY Configuration window appears. 6. Set the Connection type to Serial. 7. Enter the name of the COM port in the Serial line field 8.
Page 136: Putty Configuration
DesignWare ARC AXC003 CPU Card User Guide Installing and Configuring PuTTY PuTTY Configuration 9. Click on Open to launch the PuTTY terminal. Synopsys, Inc. Version 6323-018 May 2017...
Page 137: Detailed Core Configurations
A mechanism for checking stack accesses ll64_option true true Support for load and store instructions that transfer register pairs to/from memory intvbase_preset The upper 22 bits of the interrupt vector base configuration register Synopsys, Inc. Version 6323-018 May 2017...
Page 138 DesignWare ARC AXC003 CPU Card User Guide Detailed Core Configurations Configuration Description HS36 HS38x2 Option rgf_num_regs Size (in 32b registers) of the processor register file rgf_num_banks Number of register banks infer_alu_adder infer infer Datapath infer/instantiate infer_mpy_wtree infer infer Datapath infer/instantiate...
Page 139 Detailed Core Configurations DesignWare ARC AXC003 CPU Card User Guide Configuration Description HS36 HS38x2 Option Timer 0 timer_0_int_level Interrupt level (and implicitly the priority: level 0 is highest) Timer 1 timer_1_int_level Interrupt level (and implicitly the priority: level 0 is highest)
Page 140 DesignWare ARC AXC003 CPU Card User Guide Detailed Core Configurations Configuration Description HS36 HS38x2 Option ARC RTT has_nexus_if true true Nexus interface to offload the data from RTT has_on_chip_mem true true On-chip memory option to store the trace data in shared memory...
Page 141 Detailed Core Configurations DesignWare ARC AXC003 CPU Card User Guide Configuration Description HS36 HS38x2 Option dc_bsize Cache-line length in bytes dc_bus_data_width Cache-bus width for refills and evictions dc_mem_cycles Number of cycles dedicated to the data cache data memories dc_mem_posedge true...
Page 142 DesignWare ARC AXC003 CPU Card User Guide Detailed Core Configurations Configuration Description HS36 HS38x2 Option Bus Interface Unit biu_mem_bus_num Number of memory busses (ignored if system-level cache is present) biu_mem_bus_ Protocol to connect to external memory option biu_mem_bus_data_ Data width of the memory busses...
Page 143 Detailed Core Configurations DesignWare ARC AXC003 CPU Card User Guide Configuration Description HS36 HS38x2 Option slc_clock_gating false Inserts architectural clock-gating elements in the design. Set to false for certain FPGA tools slc_mem_bus_width Width of data connection to external memory slc_ecc_option...
Page 144 GPIO General Purpose Input/Output Hardware HAPS High performance ASIC Prototyping System; FPGA based prototyping system of Synopsys HapsTrak II Standard (SAMTEC) connector type used on HAPS Integrated Circuit Inter-IC Sound, serial bus interface standard for the transfer of audio data...
Page 145 Glossary and References DesignWare ARC AXC003 CPU Card User Guide Software Development Platform SPDIF Sony/Philips Digital Interface SDRAM Synchronous Dynamic Random Access Memory SRAM Static Random Access Memory Software References HapsTrak II standard C/C++ Programmer's Guide for the MetaWare Compiler Synopsys DesignWare dw_apb_gpio Databook http://www.synopsys.com...