Table of Contents
10.2.2
PWM Mode Control Registers
PWM mode control registers are used to set various modes for the motor control block.
PWM0 Mode Control Register (PWMMD0: 0x0000A300) [8,16-bit Access Register]
bp
15
14
Flag
SYN
-
EN0
At reset
0
0
Access
R
R/W
bp
Flag
Description
15
-
-
Simultaneous starting function of PWM0
14
SYNEN0
and PWM1 enable
Output timing varying function enable
13
SFTEN0
Count clock switch
12
CLKSEL0
TMSTAEN
TM12 external trigger activation enable
11
0
(PWM binary counter underflow)
TMSTBEN
TM12 external trigger activation enable
10
0
(PWM binary counter overflow)
OUTMD0 buffer mode
9
SDSELA0
PWMSEL0 buffer mode.
8
SDSELB0
Double buffer load timing enable (PWM
7
PCRAEN0
binary counter underflow)
Double buffer load timing enable (PWM
6
PCRBEN0
binary counter overflow)
Timer interrupt timing enable (PWM
5
INTAEN0
binary counter underflow).
Timer interrupt timing enable (PWM
4
INTBEN0
binary counter overflow).
Dead Time insertion
3
DTEN0
Dead Time insertion logic
2
ORMD0
PWM counting operation enable
1
TCEN0
PWM waveform mode
0
WAVEMD0
13
12
11
10
CLK
TMS
TMS
SFT
SEL
TA
TB
EN0
0
EN0
EN0
0
0
0
0
R/W
R/W
R/W
R/W
9
8
7
6
SDS
SDS
PCR
PCR
ELA
ELB
A
B
0
0
EN0
EN0
0
0
0
0
R/W
R/W
R/W
R/W
Setting condition
-
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: IOCLK
1: Setting prohibited
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Single-buffer mode
1: Double-buffer mode
0: Single-buffer mode
1: Double-buffer mode
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: No dead time
1: Dead Time
0: Positive logic (H active)
1: Negative logic ( L active)
0: Disabled
1: Enabled
0: Triangular wave
1: Saw-tooth wave
5
4
3
2
INTA
INTB
DT
OR
EN0
EN0
EN0
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Control Registers
Chapter 10
Motor Control PWM
1
0
WAV
TC
E
EN0
MD0
0
0
R/W
R/W
X - 5
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