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ValentFX Mark 1 FPGA Starter Manual

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Valent F(x) Logi Family
A brief beginner's guide to the Mark 1 FPGA platform
By Andy Gikling ([email protected])
v1.0 - 6/1/2013
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Summary of Contents for ValentFX Mark 1 FPGA

  • Page 1 Valent F(x) Logi Family A brief beginner’s guide to the Mark 1 FPGA platform By Andy Gikling ([email protected]) v1.0 - 6/1/2013...

  • Page 2: Table Of Contents

    Table of Contents 1. Forward .................................... 1 2. Background ..................................1 3. Getting Started .................................. 2 3.1. Running a Pre-Compiled Design on the Mark 1 ......................3 4. Developing Your Own Design ............................4 4.1. Setup Your Development Environment ........................5 4.2.

  • Page 3: Forward

    In an effort to ease this FPGA learning curve and get exposure to a wider audience of electronics practitioners, both hobbyist and professional alike, ValentF(X) has developed the Mark 1 FPGA board. It is a part of the Logi family of boards and is a fantastic platform to start out on for anyone who wants to learn about FPGA technology.

  • Page 4: Getting Started

    Indeed, the current trend in the electronics industry is moving toward more and more the part consolidation on circuit boards. This new breed of IC technology has been driven primarily by the mobile computing markets where size and power consumption are of (or SoC) integrated circuit.

  • Page 5: Running A Pre-Compiled Design On The Mark 1

    17. U4 - Abracon Corporation - 50MHz Oscillator (ASDMB-50.000MHZ-LC-T) 18. Push Button PB0 19. Push Button PB1 20. Push Button PB2 21. Push Button PB3 22. P1C Arduino Uno Header 23. LEDs - LED0 through LED7 24. Switches - SW0 through SW4 25.

  • Page 6: Developing Your Own Design

    The board will come alive and you will see little green LEDs glowing on it. After a few seconds you will see LED DC17 start flashing if the board already has a configuration file setup on it. This means the NPX microcontroller is configuring the FPGA.

  • Page 7: Setup Your Development Environment

    4.1. Setup Your Development Environment Software development for the Spartan 6 target is done in Xilinx’s development environment (ISE loosely means Integrated Software Environment). As of this writing, Xilinx is on ISE version 14.5. Go here to start downloading it. If you have a slow or unreliable, connection you might want to download the file in parts.

  • Page 8: Create Your First Project

    Figure 6 – Unique Computer Info Tied to WebPack License At this point the software will open your web browser and bring you to the Xilinx site. It will ask you to login with your user account. Do it and follow the on screen instructions. Once you complete the on screen steps Xilinx will email you a license file with the file extension .lic.

  • Page 9: Add Some Logic To Your Project

    After clicking next you will find the project’s settings page. You can use the settings shown below for the Mark 1 board. These settings can be changed at any time later on. This wizard page is designed to let you choose important software environment settings from lists of possibilities.
  • Page 10 Figure 9 – An Empty Design in the Hierarchy View To add a top level HDL file, right click the target chip in the Hierarchy view (denoted by the model, xc6slx9…) and choose New Source. This will bring up a view that allows you to add a design file to your project. There are many different types of files you can choose here but for this instruction we will have you load a new “Verilog Module.”...
  • Page 11 Figure 11 – A Top-Level Verilog Module’s IO Definition In the Hierarchy view you will see a new Verilog source file called “Mark1Starter_TopLevel.v.” “.v” is the file extension for Verilog files. Double click it and its contents will be shown in the text editor on the pane to the right. Here is what you should see: Figure 12 –...

  • Page 12: So What Does This Simple Program Do

    The “Btn0” input represents the wire coming from PushButton0 on the PCB. Similarly, “LEDOutput0” and “LEDOutput1” represent the wires going out to LED0 and LED1 on the PCB. What we’re going to do with these signals is ground breaking… The goal is when the button is not pushed, LED0 will be illuminated and LED1 will not be illuminated.

  • Page 13: Constraining The Design

    IO point is true). And second, the LEDs on the PCB are electrically connected in a positive logic manner (or “active high” – when the LEDOuput0 changes to true, a positive voltage is put on the output pin and current will flow through the LED and illuminate it). For these reasons, the initial condition for this circuit has LED0 on and LED1 off when PushButton0 is not pressed.
  • Page 14 This is where the “Implementation Constrains File” comes in. These files have a .ucf file extension and describe the design’s “user constraints.” Design constrains are a set of rules the compilation process needs to take into account when building the design’s binary output file.

  • Page 15: Build Your Project

    As is tradition, the green denotes comments and the language syntax are highlighted appropriately. Thank goodness for modern IDE’s… and remember to end each statement with a semicolon! The 4 line defines a “net” called OSC_FPGA and its TNM_NET parameter gets the name clk50_grp. TNM_NET is a keyword used for defining a design’s clock signals. Again, there are many keywords that can be used in an infinite number of ways in these constraints files.
  • Page 16 Translate – The NGDBUILD software tool is used to translate the netlist from using the UNISIM library to the SIMPRIM library. Map – the MAP software tool is used to take the SIMPRIM primitives and decide how the chip’s physical resources (flip-flops, BRAMs, Multipliers, LUTs etc.) will be used.

  • Page 17: Errors

    Figure 21 – Console Output at the End of a Successful Build 4.6.1. Errors! Chances are you’re going to make a mistake at some point along the way. If not in this tutorial, someday, you will make a mistake and get a compiler error, sorry. In this case one of your build steps will have a red X next to it. The X isn’t entirely helpful to a beginner.

  • Page 18: Where To Go From Here

    Here’s a short list of open source projects where a computing platform has been integrated with the Mark 1: • Bitcoin Miner – An FPGA based Bitcoin miner design for the Mark 1 and Beaglebone http://valentfx.com/logi-blog/item/fpga-logi-family-bitcoin-mining-application • Autonomous Vehicle Platform – A design to drive a car through a course. Integrates sensors and the Raspberry Pi http://valentfx.com/logi-blog/item/logi-bot-autonomous-vehicle-project-for-logi-boards •...

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