Table of Contents
MNEMONIC
OPERAND
BEV
M
BOD
M
SPECIAL INSTRUCTIONS
DIF
NIS
LDF
I
DIF 1
DIF 2
DIF
3
DIF 4
DIF 5-6
DIF 7
DIF
8
DIF
9
DIF
0
I
NIS 1
NIS 2
NIS 3
NIS 4
NIS 5-6
NIS 7
NIS 8
NIS 9
NIS 0
M
WORD TIMES
1
1
1
1
2
DESCRIPTION
BRANCH ON EVEN.
If
the Even Flip-Flop
is even, control is transferred to M.
BRANCH ON ODD.
If
the Even Flip-Flop is
odd, control is transferred to M.
DRIVE INTERNAL FUNCTION. A signal will
be sent to those Internal Function Drivers
which correspond to ones in I.
Function
Reset Control Bit Flip-Flops 1 and 2, and
reset the Parity bit Flip-Flop.
Reset the Buzzer Flip-Flop.
Set the Buzzer Flip-Flop.
Initiate the Hardware Load process.
Not assigned.
This is the SEL instruction.
Set Control Bit Flip-Flop 1.
Set Control Bit Flip-Flop 2.
Set the Parity Bit Flip-Flop.
AND INTERNAL STATUS LINES TO Z.
A
logical "AND" is performed with 1
(1-10)
and
the Internal Status Lines.
The only results
are the new states of the Plus, Zero, and Even
Flip-Flops.
Function
The character parity output of the parity
network is a 1.
The word parity output of the parity network
is a 1.
Control Bit Flip-Flop 2 and the word parity
output of the parity network are identical.
This is intended for use when transmitting
data with error correcting techniques.
The
Operating Mode/Maintenance
Mode
switch is in the Maintenance Mode position.
Not Assigned.
Controller Selector is ready.
Control Bit Flip-Flop 1 is a 1.
Control Bit Flip-Flop 2 is a 1.
The Parity Bit Flip-Flop is a 1.
LOAD SPECIAL FLIP-FLOPS. Selected bits
from the contents of M are used to restore
the conditions (saved by an STF instruction)
of the Plus,
Zero, Even, Control Bit 1,
Control Bit 2, and Parity Flip-Flops.
Bit
position 1 goes to the Even Flip-Flop. Bit
[ID/A\lf/A\~~llc:) ~@------------
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