Sharp Blue Treak LH75410 Manuals

Manuals and User Guides for Sharp Blue Treak LH75410. We have 1 Sharp Blue Treak LH75410 manual available for free PDF download: User Manual

Sharp Blue Treak LH75410 User Manual (502 pages)

System-on-Chip Preliminary

Brand: Sharp | Category: Controller | Size: 8.3 MB

Table of Contents
3
Multiplexed Pins
31
Preface
31
Supplemental Documentation
31
Terms and Conventions
31
Peripheral Devices
32
Pin Names
32
Register Addresses
32
Register Names
32
Register Tables
33
Table 1. Register Name
33
Table 2. Bit Definitions
33
Figure 1. Multiplexer
34
Figure 2. Register with Bit Field Named
34
Figure 3. Register with Multiple Bit Fields Named
35
Figure 4. Register with Bit Field Named
35
Chapter 1 - Introduction

36
Chapter 12 - Direct Memory Access Controller

36
Chapter 13 - Color Liquid Crystal Display Controller

36
Chapter 14 - Liquid Crystal Display Controller

36
Chapter 16 - Watchdog Timer

36
Chapter 17 - Real-Time Clock

36
Chapter 18 - Synchronous Serial Port

36
Chapter 7 - Static Memory Controller

36
- Product Overview
  36
- Table 1-1. Feature Summary
  36
- ARM and Thumb State
  37
- Bus Architecture
  37
- Operating Modes
  38
- Table 1-3. Device Operating Modes
  38
- Embedded ICE Mode
  39
- Normal Mode
  39
- PLL Bypass Mode
  39
- Power Supplies
  39
- Linear Regulator Power
  40
- PCB Mounted Analog Power Supply Filter for PLL Usage
  40
- PLL Power
  40
- Table 1-4. Linear Regulator Ramp-Up Time
  40
- Real-World Component Selection
  41
- Clocking Strategy
  42
- Crystal Oscillator Usage
  42
- Figure 1-1. Crystal Oscillator
  42
- Reset Strategy
  43
Chapter 2 - LH75401 Soc

44
Chapter 3 - LH75411 Soc

57
Chapter 4 - LH75400 Soc

70
Chapter 5 - LH75410 Soc

83
Chapter 6 - Memory Interface Architecture

96
- Table 6-1. Memory Mapping
  97
- Table 6-2. External Memory Section Mapping
  98
- Table 6-3. Primary AHB Peripheral Register Mapping
  98
- Table 6-4. APB Peripheral Register Mapping
  99
- Chapter 7 - Static Memory Controller
  100
- SMC Features
  100
- Table 7-1. Address Bus Organization
  100
- SMC Theory of Operation
  101
- SMC Write Process
  101
- Figure 7-1. SMC Write Access
  102
- SMC Burst Mode Read Process
  103
- SMC Read Process
  103
- Figure 7-2. SMC Write, Ncsx De-Asserted Early
  104
- Figure 7-3. SMC Read Access
  105
- Figure 7-4. SMC Burst Read Access
  106
- External Memory Bus Cycle
  107
- Table 7-2. SMC Bus Turnaround Usage
  107
- External Bus Read/Write Operations
  108
- Table 7-3. 8-Bit External Bus Read
  108
- Table 7-4. 16-Bit External Bus Read
  108
- Table 7-5. 8-Bit External Bus Write
  109
- Table 7-6. 16-Bit External Bus Write
  109
- Figure 7-5. Typical Memory Connection Diagram
  110
- SMC Memory Connection Diagram
  110
- SMC Programmer's Model
  111
- SMC Register Summary
  111
- Table 7-7. SMC Memory Bank Address Space
  111
- Table 7-8. SMC Register Summary
  111
- Configuration Register for Memory Bank 0
  112
- SMC Register Definitions
  112
- Table 7-10. BCR0 Register (8-Bit Mode)
  112
- Table 7-9. BCR0 Register (16-Bit Mode)
  112
- Table 7-11. BCR0 Register Definitions
  113
- Configuration Register for Memory Bank 1
  114
- Table 7-12. BCR1 Register
  114
- Table 7-13. BCR1 Register Definitions
  114
- Configuration Register for Memory Bank 2
  116
- Table 7-14. BCR2 Register
  116
- Table 7-15. BCR2 Register Definitions
  116
- Configuration Register for Memory Bank 3
  118
- Table 7-16. BCR3 Register
  118
- Table 7-17. BCR3 Register Definitions
  118
- SMC Default Memory Widths
  120
- Table 7-18. SMC System Reset Default Memory Width
  120
Chapter 8 - Static Random Access Memory Controller

121
Chapter 9 - Reset, Clock, and Power Controller

122
- Figure 9-1. RCPC Block Diagram
  122
- RCPC Features
  123
- RCPC Theory of Operation
  123
- Reset Generation
  124
- Clock Generation
  125
- RCPC Power Modes
  125
- Table 9-1. Clock and Enable States for Different Power Modes
  125
- Active Mode
  126
- Sleep Mode
  126
- Standby Mode
  126
- Stop1 Mode
  126
- Stop2 Mode
  126
- RCPC Programmer's Model
  127
- RCPC Register Summary
  127
- Table 9-2. RCPC Register Summary
  127
- Control Register
  128
- RCPC Register Definitions
  128
- Table 9-3. Ctrl Register
  128
- Table 9-4. Ctrl Register Definitions
  128
- Identification Register
  129
- Remap Control Register
  129
- Table 9-5. ID Register
  129
- Table 9-6. ID Register Definitions
  129
- Table 9-7. Remap Register
  129
- Table 9-8. Remap Register Definitions
  129
- Soft Reset Register
  130
- Table 9-10. Softreset Register Definitions
  130
- Table 9-9. Softreset Register
  130
- Reset Status Register
  131
- Table 9-11. Resetstatus Register
  131
- Table 9-12. Resetstatus Register Definitions
  131
- Reset Status Clear Register
  132
- Table 9-13. Resetstatusclr Register
  132
- Table 9-14. Resetstatusclr Register Definitions
  132
- Chapter 9 - Reset, Clock, and Power Controller
  133
- HCLK Prescaler Register
  133
- Table 9-15. Sysclk Prescaler Register
  133
- Table 9-16. Sysclk Prescaler Register Definitions
  133
- Table 9-17. Sysclkprescaler Register Values
  133
- Peripheral Clock Control Register 0
  134
- Table 9-18. Apbperiphclkctrl0 Register
  134
- Table 9-19. Apbperiphclkctrl0 Register Definitions
  134
- Peripheral Clock Control Register 1
  135
- Table 9-20. Apbperiphclkctrl1 Register
  135
- Table 9-21. Apbperiphclkctrl1 Register Definitions
  135
- AHB Clock Control Register
  136
- Table 9-22. Ahbclkctrl Register
  136
- Table 9-23. Ahbclkctrl Register Definitions
  136
- LCD Clock Prescaler Register
  137
- Table 9-24. Lcdprescaler Register
  137
- Table 9-25. Lcdprescaler Register Definitions
  137
- Table 9-26. Lcdprescaler Register Values
  137
- SSP Clock Prescaler Register
  138
- Table 9-27. Sspprescaler Register
  138
- Table 9-28. Sspprescaler Register Definitions
  138
- Table 9-29. Sspprescaler Register Values
  138
- External Interrupt Configuration Register
  139
- Table 9-30. Intconfig Register
  139
- Table 9-31. Intconfig Register Definitions
  139
- External Interrupt Clear Register
  141
- Table 9-32. Intclear Register
  141
- Table 9-33. Intclear Register Definitions
  141
Chapter 10 - Vectored Interrupt Controller

142
- Interrupts
  142
- Theory of Operation
  142
- Table 10-1. Interrupt Assignments
  143
- VIC Interrupt Listing
  143
- External Interrupts
  144
- Vectored Interrupts
  144
- Clearing Interrupts
  145
- Priority
  145
- Sequencing
  146
- External Level-Sensitive Interrupts
  148
- Software Guidelines
  148
- VIC Programmer's Model
  148
- Table 10-2. VIC Register Summary
  149
- VIC Register Summary
  149
- IRQ Status Register
  150
- Table 10-3. Irqstatus Register
  150
- Table 10-4. Irqstatus Register Definitions
  150
- VIC Register Definitions
  150
- FIQ Status Register
  151
- Table 10-5. Fiqstatus Register
  151
- Table 10-6. Fiqstatus Register Definitions
  151
- Raw Interrupt Status Register
  152
- Table 10-7. Rawintr Register
  152
- Table 10-8. Rawintr Register Definitions
  152
- Interrupt Select Register
  153
- Table 10-10. Intselect Register Definitions
  153
- Table 10-9. Intselect Register
  153
- Interrupt Enable Register
  154
- Table 10-11. Intenable Register
  154
- Table 10-12. Intenable Register Definitions
  154
- Interrupt Enable Clear Register
  155
- Table 10-13. Intenclear Register
  155
- Table 10-14. Intenclear Register Definitions
  155
- Software Interrupt Register
  156
- Table 10-15. Softint Register
  156
- Table 10-16. Softint Register Definitions
  156
- Software Interrupt Clear Register
  157
- Table 10-17. Softintclear Register
  157
- Table 10-18. Softintclear
  157
- Table 10-19. Vectaddr Register
  158
- Table 10-20. Vectaddr Register Definitions
  158
- Vector Address Register
  158
- Default Vector Address Register
  159
- Table 10-21. Defvectaddr Register
  159
- Table 10-22. Defvectaddr Register Definitions
  159
- Table 10-23. Vectaddr Registers
  160
- Table 10-24. Vectaddr Register Definitions
  160
- Vector Address Registers
  160
- Table 10-25. Vectctrl Registers
  161
- Table 10-26. Vectctrl Register Definitions
  161
- Vector Control Registers
  161
Chapter 11 - I/O Configuration

162
- IOCON Theory of Operation
  162
- IOCON Programmer's Model
  163
- IOCON Register Summary
  163
- Table 11-1. IOCON Register Summary
  163
- EBI Interface Muxing Register
  164
- IOCON Register Definitions
  164
- Table 11-2. EBI_MUX Register (16-Bit Mode)
  164
- Table 11-3. EBI_MUX Register (8-Bit Mode)
  164
- Table 11-4. EBI_MUX Register Definitions
  165
- Pins PD6/INT6 to PD0/INT0 Muxing Register
  166
- Table 11-6. PD_MUX Register Definitions
  166
- Pins PE7/SSPRM to PD0/INT0 Muxing Register
  167
- Table 11-7. PE_MUX Register (LH75401 and LH75400)
  167
- Table 11-8. PE_MUX Register (LH75410 and LH75411)
  167
- Table 11-9. PE_MUX Register Definitions
  168
- Table 11-11. TIMER_MUX Register Definitions
  169
- Timer Muxing Register
  169
- LCD Mode Muxing Register
  171
- Table 11-13. LCD_MUX Register Definitions (LH75401 and LH75411 Soc Devices)
  171
- Table 11-14. LCD_MUX Register Definitions (LH75400 and LH75410 Soc Devices)
  171
- Pins PA7/D15 to PA0/D8 Resistor Muxing Register
  172
- Table 11-16. PA_RES_MUX Register Definitions
  172
- Pins Pb5/Nwait to Pb0/Ncs1 Resistor Muxing Register
  174
- Table 11-18. PB_RES_MUX Register Definitions
  174
- Pins PC7/A23 to PC0/A16 Resistor Muxing Register
  175
- Table 11-20. PC_RES_MUX Register Definitions
  175
- Pins PD6/INT6 to PD0/INT0 Resistor Muxing Register
  177
- Table 11-22. PD_RES_MUX Register Definitions
  177
- Pins PE7/SSPRM to PE0/UARTRX2 Resistor Muxing Register
  179
- Table 11-24. PE_RES_MUX Register Definitions
  179
- Pins AN7/PJ7 to AN0/PJ0
  181
- Chapter 12 - Direct Memory Access Controller
  182
- DMA Controller Features
  182
- Table 12-1. DMA Controller Stream Assignments and Request Priority
  182
- DMA Theory of Operation
  183
- DMA Controller Timing Diagrams
  185
- Interrupt, Error, and Status Registers
  185
- Figure 12-1. Peripheral-To-Memory Data-Transfer Timing
  186
- Figure 12-2. Memory-To-Peripheral Data-Transfer Timing
  187
- DMA Controller Register Summary
  188
- DMA Programmer's Model
  188
- Table 12-2. DMA Register Summary
  188
- Table 12-3. Data Stream Register Summary
  188
- Destination Base Register
  189
- DMA Controller Register Definitions
  189
- Maximum Count Register
  189
- Source Base Registers
  189
- Control Register
  190
- Table 12-4. CTRL Register
  190
- Table 12-5. CTRL Register Definitions
  190
- Table 12-6. DMA Data Width
  191
- Table 12-7. DMA Burst Size
  191
- Current Destination Registers
  192
- Current Source Registers
  192
- Terminal Count Register
  192
- Interrupt Mask Register
  193
- Table 12-8. Interrupt Mask Register
  193
- Table 12-9. Interrupt Mask Register Definitions
  193
- Interrupt Clear Register
  194
- Table 12-10. CLR Register
  194
- Table 12-11. CLR Register Definitions
  194
- Status Register
  195
- Table 12-12. Status Register
  195
- Table 12-13. Status Register Definitions
  195
- Chapter 13 - Color Liquid Crystal Display Controller
  197
- Figure 13-1. Color LCD Controller Block Diagram (LH75401 and LH75411 Only)
  198
- CLCDC Features
  199
- CLCDC Theory of Operation
  200
- LCD DMA Fifos
  200
- Pixel Serializer
  200
- How Pixels Are Stored in Memory
  201
- Table 13-1. Pixel Display Arrangement
  201
- Table 13-2. Frame Buffer Pixel Storage Format [31:16]
  201
- Table 13-3. Frame Buffer Pixel Storage Format [15:0]
  201
- Palette RAM
  202
- Table 13-4. Palette Data Storage
  202
- Grayscale Algorithm
  203
- LCD Panel Resolutions
  203
- Table 13-5. Supported TFT, HR-TFT, and AD-TFT LCD Panels
  204
- Table 13-6. Supported Color STN LCD Panels
  204
- Table 13-7. Supported Mono-STN LCD Panels
  204
- Table 13-8. Color STN Intensities from Gray-Scale Modulation
  205
- CLCDC Programmer's Model
  206
- CLCDC Register Summary
  206
- Table 13-9. CLCDC Register Summary
  206
- CLCDC Register Definitions
  207
- Horizontal Timing Panel Control Register
  207
- Table 13-10. Timing0 Register
  207
- Table 13-11. Timing0 Register Definitions
  207
- Horizontal Timing Restrictions
  208
- Table 13-12. Timing1 Register
  209
- Table 13-13. Timing1 Register Definitions
  209
- Vertical Timing Panel Control Register
  209
- Clock and Signal Polarity Control Register
  210
- Table 13-14. Timing2 Register
  210
- Table 13-15. Timing2 Register Definitions
  210
- Table 13-16. UPBASE Register
  211
- Table 13-17. UPBASE Register Definitions
  211
- Upper Panel Frame Buffer Base Address Register
  211
- Lower Panel Frame Buffer Base Address Register
  212
- Table 13-18. LPBASE Register
  212
- Table 13-19. LPBASE Register Definitions
  212
- Interrupt Enable Register
  213
- Table 13-20. INTRENABLE Register
  213
- Table 13-21. INTRENABLE Register Definitions
  213
- LCD Panel Parameters, LCD Panel Power, and CLCDC Control Register
  214
- Raw Interrupt Status Register
  216
- Table 13-24. Status Register
  216
- Table 13-25. Status Register Definitions
  216
- Final Masked Interrupts Register
  217
- Table 13-26. Interrupt Register
  217
- Table 13-27. Interrupt Register Definitions
  217
- LCD Upper Panel Frame Buffer Current Address Register
  218
- Table 13-28. UPCURR Register
  218
- Table 13-29. UPCURR Register Definitions
  218
- Table 13-30. LPCURR Register
  218
- Table 13-31. LCDLPCURR Register Definitions
  218
- 16-Bit Color Palette Register
  219
- Table 13-32. Palette Register
  219
- Table 13-33. Palette Register Use for TFT and STN
  219
- Bypass Mode
  220
- CLCDC Interrupts
  220
- HRTFTC Operating Modes
  220
- TFT Controller
  220
- TFT Mode
  220
- HRTFTC Programmer's Model
  221
- HRTFTC Register Summary
  221
- HRTFTC Theory of Operation
  221
- Table 13-34. HRTFTC Register Summary
  221
- HRTFTC Register Definitions
  222
- Setup Register
  222
- Table 13-35. Setup Register
  222
- Table 13-36. Setup Register Definitions
  222
- Control Register
  223
- Table 13-37. CTRL Register
  223
- Table 13-38. CTRL Register Definitions
  223
- Table 13-39. Timing1 Register
  224
- Table 13-40. Timing1 Register Definitions
  224
- Timing1 Register
  224
- Table 13-41. Timing2 Register
  225
- Table 13-42. Timing2 Register Definitions
  225
- Timing2 Register
  225
- STN Horizontal Timing
  226
- STN Vertical Timing
  226
- TFT Horizontal Timing
  226
- TFT Horizontal Timing Waveforms
  226
- TFT Vertical Timing
  226
- TFT Vertical Timing Waveforms
  226
- Timing Waveforms
  226
- Figure 13-2. STN Horizontal Timing Diagram
  227
- Figure 13-3. STN Vertical Timing Diagram
  228
- Figure 13-4. TFT Horizontal Timing Diagram
  229
- Figure 13-5. TFT Vertical Timing Diagram
  230
- Figure 13-6. HR-TFT Horizontal Timing Diagram
  231
- Figure 13-7. HR-TFT Vertical Timing Diagram
  231
- Chapter 14 - Liquid Crystal Display Controller
  232
- Figure 14-1. LCD Controller Block Diagram (LH75400 and LH75410 Only)
  233
- LCDC Features
  234
- LCDC Theory of Operation
  234
- How Pixels Are Stored in Memory
  235
- LCD DMA Fifos
  235
- Pixel Serializer
  235
- Table 14-1. DMA FIFO Output Bits [31:16]
  235
- Table 14-2. DMA FIFO Output Bits [15:0]
  235
- Grayscale Algorithm
  236
- Palette RAM
  236
- Table 14-3. Palette Data Storage
  236
- Supported Grayscale
  237
- Table 14-4. STN Intensities from Grayscale Modulation
  237
- Table 14-5. LCD Controller Grayscale Support
  237
- LCDC Programmer's Model
  238
- LCDC Register Summary
  238
- Table 14-6. LCDC Register Summary
  238
- Horizontal Timing Panel Control Register
  239
- LCDC Register Definitions
  239
- Table 14-7. Timing0 Register
  239
- Table 14-8. Timing0 Register Definitions
  239
- Horizontal Timing Restrictions
  240
- Table 14-10. Timing1 Register Definitions
  241
- Table 14-9. Timing1 Register
  241
- Vertical Timing Panel Control Register
  241
- Clock and Signal Polarity Control Register
  242
- Table 14-11. Timing2 Register
  242
- Table 14-12. Timing2 Register Definitions
  242
- Table 14-13. UPBASE Register
  243
- Table 14-14. UPBASE Register Definitions
  243
- Upper Panel Frame Buffer Base Address Register
  243
- Lower Panel Frame Buffer Base Address Register
  244
- Table 14-15. LPBASE Register
  244
- Table 14-16. LPBASE Register Definitions
  244
- Interrupt Enable Register
  245
- Table 14-17. INTRENABLE Register
  245
- Table 14-18. INTRENABLE Register Definitions
  245
- LCD Panel Parameters, LCD Panel Power, and LCDC Control Register
  246
- Table 14-19. CTRL Register
  246
- Table 14-20. CTRL Register Definitions
  246
- Raw Interrupt Status Register
  248
- Table 14-21. Status Register
  248
- Table 14-22. Status Register Definitions
  248
- Final Masked Interrupts Register
  249
- Table 14-23. Interrupt Register
  249
- Table 14-24. Interrupt Register Definitions
  249
- LCD Upper Panel Frame Buffer Current Address Register
  250
- Table 14-25. UPCURR Register
  250
- Table 14-26. UPCURR Register Definitions
  250
- Table 14-27. LPCURR Register
  250
- Table 14-28. LCDLPCURR Register Definitions
  250
- LCD Palette Register
  251
- LCDC Interrupts
  251
- Table 14-29. Palette Register
  251
- Table 14-30. Palette Register Definitions
  251
Chapter 15 - Timers

252
- Figure 15-1. Overall Timer Block Diagram
  253
- Figure 15-2. Timer 0 Block Diagram
  254
- Figure 15-3. Timers 1 and 2 Block Diagram
  255
- Count Timing
  256
- Figure 15-4. Count Clock Timing (System Clock in Phase with CTCLK)
  256
- Figure 15-5. Count Clock Timing (System Clock Not in Phase with CTCLK)
  256
- Timer Theory of Operation
  256
- Counter Clear Upon Compare Match
  257
- Figure 15-6. Compare Match and Counter Clear
  257
- Capture Signal Sampling
  258
- Figure 15-7. Capture Signal Synchronization Timing
  258
- PWM Mode
  258
- Figure 15-8. PWM Output Signal Timing
  259
- Table 15-1. Timer 0 Register Summary
  260
- Table 15-2. Timer 1 Register Summary
  260
- Table 15-3. Timer 2 Register Summary
  260
- Timer Programmer's Model
  260
- Timer Register Summary
  260
- Table 13-22. Ctrl Register
  261
- Table 13-23. Ctrl Register Definitions
  261
- Timer 0 Control Register
  261
- Timer Register Definitions
  261
- Table 15-6. CMP_CAP_CTRL Register
  262
- Table 15-7. CMP_CAP_CTRL Register Definitions
  262
- Timer 0 Compare/Capture Control Register
  262
- Table 15-8. INT_CTRL Register
  264
- Table 15-9. INT_CTRL Register Definitions
  264
- Timer 0 Interrupt Control Register
  264
- Table 15-10. Status Register
  265
- Table 15-11. Status Register Definitions
  265
- Timer 0 Status Register
  265
- Table 15-12. CNT Register
  266
- Table 15-13. CNT Register Definitions
  266
- Timer 0 Counter Register
  266
- Table 15-14. CMP(N) Registers
  267
- Table 15-15. CMP(N) Register Definitions
  267
- Timer 0 Compare Registers
  267
- Table 15-16. CAP(N) Register
  268
- Table 15-17. CAP(N) Register Definitions
  268
- Timer 0 Capture Registers
  268
- Table 15-18. CTRL Register
  269
- Table 15-19. CTRL Register Definitions
  269
- Timer 1 Control Register
  269
- Table 15-20. INT_CTRL Register
  271
- Table 15-21. INT_CTRL Register Definitions
  271
- Timer 1 Interrupt Control Register
  271
- Table 15-22. Status Register
  272
- Table 15-23. Status Register Definitions
  272
- Timer 1 Status Register
  272
- Table 15-24. CNT Register
  273
- Table 15-25. CNT Register Definitions
  273
- Timer 1 Counter Register
  273
- Table 15-26. CMP(N) Registers
  274
- Table 15-27. CMP(N) Register Definitions
  274
- Timer 1 Compare Registers
  274
- Table 15-28. CAP(N) Register
  275
- Table 15-29. CAP(N) Register Definitions
  275
- Timer 1 Capture Registers
  275
- Table 15-30. CTRL Register
  276
- Table 15-31. CTRL Register Definitions
  276
- Timer 2 Control Register
  276
- Table 15-32. INT_CTRL Register
  278
- Table 15-33. INT_CTRL Register Definitions
  278
- Timer 2 Interrupt Control Register
  278
- Table 15-34. Status Register
  279
- Table 15-35. Status Register Definitions
  279
- Timer 2 Status Register
  279
- Table 15-36. CNT Register
  280
- Table 15-37. CNT Register Definitions
  280
- Timer 2 Counter Register
  280
- Table 15-38. CMP(N) Registers
  281
- Table 15-39. CMP(N) Register Definitions
  281
- Timer 2 Compare Registers
  281
- Table 15-40. CAP(N) Register
  282
- Table 15-41. CAP(N) Register Definitions
  282
- Timer 2 Capture Registers
  282
- Timer Interrupts
  283
- Chapter 16 - Watchdog Timer
  284
- Figure 16-1. Watchdog Timer Block Diagram
  284
- WDT Features
  284
- Table 16-1. WDT Register Summary
  285
- WDT Programmer's Model
  285
- WDT Register Summary
  285
- WDT Theory of Operation
  285
- Control Register
  286
- Table 16-2. CTRL Register
  286
- Table 16-3. CTRL Register Definitions
  286
- WDT Register Definitions
  286
- Counter Reset Register
  287
- Table 16-4. CNTR Register
  287
- Table 16-5. CNTR Register Definitions
  287
- Status Register
  288
- Table 16-6. STR Register
  288
- Table 16-7. STR Register Definitions
  288
- Counter Section 0 Register
  289
- Counter Section 1 Register
  289
- Table 16-10. CNT1 Register
  289
- Table 16-11. CNT1 Register Definitions
  289
- Table 16-8. CNT0 Register
  289
- Table 16-9. CNT0 Register Definitions
  289
- Counter Section 2 Register
  290
- Counter Section 3 Register
  290
- Table 16-12. CNT2 Register
  290
- Table 16-13. CNT2 Register Definitions
  290
- Table 16-14. CNT3 Register
  290
- Table 16-15. CNT3 Register Definitions
  290
- Chapter 17 - Real-Time Clock
  291
- Figure 17-1. RTC Block Diagram
  291
- RTC Features
  291
- RTC Theory of Operation
  292
- RTC Programmer's Model
  293
- RTC Register Summary
  293
- Table 17-1. RTC Register Summary
  293
- Data Register 0
  294
- RTC Register Definitions
  294
- Table 17-2. DR0 Register
  294
- Table 17-3. DR0 Register Definitions
  294
- Data Register 1
  295
- Table 17-4. DR1 Register
  295
- Table 17-5. DR1 Register Definitions
  295
- Match Register 0
  296
- Match Register 1
  296
- Table 17-6. MR0 Register
  296
- Table 17-7. MR0 Register Definitions
  296
- Table 17-8. MR1 Register
  296
- Table 17-9. MR1 Register Definitions
  296
- Interrupt Status/Clear
  297
- Table 17-10. STAT/EOI Register (Write Operations)
  297
- Table 17-11. STAT/EOI Register Definitions (Write Operations)
  297
- Table 17-12. STAT/EOI Register (Read Operations)
  297
- Table 17-13. STAT/EOI Register Definitions (Read Operations)
  297
- Read/Write Load Register 0
  298
- Table 18. LR0 Register
  298
- Table 19. LR0 Register Definitions
  298
- Read/Write Load Register 1
  299
- Table 20. LR1 Register
  299
- Table 21. LR1 Register Definitions
  299
- Control Register
  300
- Table 22. CTRL Register
  300
- Table 23. CTRL Register Definitions
  300
- Chapter 18 - Synchronous Serial Port
  301
- SSP Features
  301
- Figure 18-1. Synchronous Serial Port Block Diagram
  302
- SSP Theory of Operation
  303
- Table 18-1. Feature Comparison
  303
- Figure 18-2. SSP Timing Waveform
  304
- SSP Timing Waveforms
  304
- Motorola SPI Frame Format
  305
- Figure 18-7. Texas Instruments Synchronous Serial Frame Format (Single Transfer)
  307
- Figure 18-8. Texas Instruments Synchronous Serial Frame Format (Continuous Transfers)
  307
- Texas Instruments Frame Format
  307
- Clock Generation
  308
- National Semiconductor Frame Format
  308
- Figure 18-9. Microwire Frame Format (Single Transfer)
  309
- Figure 18-10. Microwire Frame Format (Continuous Transfers)
  310
- SSP Programmer's Model
  311
- SSP Register Summary
  311
- Table 18-2. Register Summary
  311
- Control Register 0
  312
- SSP Register Definitions
  312
- Table 18-3. CTRL0 Register
  312
- Table 18-4. CTRL0 Register Definitions
  312
- Control Register 1
  313
- Table 18-5. CTRL1 Register
  313
- Table 18-6. CTRL1 Register Definitions
  313
- Receive / Transmit FIFO Register
  314
- Table 18-7. DR Register
  314
- Table 18-8. DR Register Definitions
  314
- Status Register
  315
- Table 18-10. SR Register Definitions
  315
- Table 18-9. SR Register
  315
- Clock Prescale Register
  316
- Table 18-11. CPSR Register
  316
- Table 18-12. CPSR Register Definitions
  316
- Interrupt Identification/Clear Register
  317
- Table 18-13. IIR/ICR Register (Read Characteristic)
  317
- Table 18-14. IIR/ICR Register Definitions (Read Operation)
  317
- Receive Timeout Register
  318
- Table 18-15. IIR/ICR Register (Write Characteristic)
  318
- Table 18-16. IIR/ICR Register Definitions (Write Characteristic)
  318
- Table 18-17. RXTO Register
  318
- Table 18-18. RXTO Register Definitions
  318
- Receive Interrupt
  319
- Receive Overrun Interrupt
  319
- Transmit Interrupt
  319
- Receive Timeout Interrupt
  320
- Sspintr
  320
Chapter 19 - UART0 and UART1

321
- Figure 19-1. UART0 and UART1 Block Diagram
  321
- UART0 and UART1 Features
  322
- UART0 and UART1 Receiver Data Frame
  322
- UART0 and UART1 Theory of Operation
  322
- Status Conditions
  323
- On-Chip DMA Capabilities
  324
- Programming Control Registers
  324
- Table 19-1. UART0 and UART1 Register Summary
  325
- UART0 and UART1 Programmer's Model
  325
- UART0 and UART1 Register Summary
  325
- Data Register
  326
- Table 19-2. DR Register
  326
- UART0 and UART1 Register Definitions
  326
- Table 19-3. DR Register Definitions
  327
- Receive Status/Error Clear Register
  328
- Table 19-4. RSR/ECR Register (Write Operations)
  328
- Table 19-5. RSR/ECR Register Definitions (Write Operations)
  328
- Table 19-6. RSR/ECR Register (Read Operations)
  329
- Table 19-7. RSR/ECR Register Definitions (Read Operations)
  329
- Flag Register
  330
- Table 19-8. FR Register
  330
- Table 19-9. FR Register Definitions
  330
- Table 19-10. Updating Register Contents
  331
- UART Line Control Register
  331
- Integer Baud Rate Divisor Register
  332
- Table 19-11. IBRD Register
  332
- Table 19-12. IBRD Register Definitions
  332
- Fractional Baud Rate Divisor Register
  333
- Table 19-13. FBRD Register
  333
- Table 19-14. FBRD Register Definitions
  333
- Calculating the Divisor Value
  334
- Table 19-15. Bit Rates and Their Corresponding Divisors
  334
- Typical Bit Rates and Their Corresponding Divisor
  334
- Line Control Register
  335
- Table 19-17. LCTRL_H Register Definitions
  336
- Table 19-19. CTRL Register
  337
- Table 19-20. CTRL Register Definitions
  337
- UART Control Register
  337
- Interrupt FIFO Level Select Register
  338
- Table 19-21. IFLS Register
  338
- Table 19-22. IFLS Register Definitions
  338
- Interrupt Mask Set/Clear Register
  339
- Table 19-23. IMSC Register
  339
- Table 19-24. IMSC Register Definitions
  339
- Raw Interrupt Status Register
  341
- Table 19-25. RIS Register
  341
- Table 19-26. RIS Register Definitions
  341
- Masked Interrupt Status Register
  342
- Table 19-27. MIS Register
  342
- Table 19-28. MIS Register Definitions
  342
- Icr
  343
- Table 19-29. ICR Register
  343
- Table 19-30. ICR Register Definitions
  343
- Dmactrl
  344
- Table 19-31. DMACTRL Register Definitions
  344
- Table 19-32. UARTRXINTR State
  345
- Table 19-33. UARTTXINTR State
  345
- UART0 and UART1 Interrupts
  345
- Uartintr
  345
- Uartrxintr
  345
- Uarttxintr
  345
Chapter 20 - UART2

346
- Figure 20-1. UART2 Block Diagram
  346
- UART2 Features
  347
- UART2 Theory of Operation
  347
- UART Receiver Data Frame
  348
- Disabling the Loading of Incoming Characters
  350
- Status Conditions
  350
- Baud Rate Generators
  351
- Table 20-1. Register Bank 0 (Default on Reset)
  352
- UART2 Programmer's Model
  352
- UART2 Register Summary
  352
- Register Bank 0
  353
- Table 20-5. TXD Register
  355
- Table 20-6. TXD Register Definitions
  355
- Transmit Buffered Data Register
  355
- UART2 Register Definitions
  355
- Receive Buffered Data Register
  356
- Table 20-7. RXD Register
  356
- Table 20-8. RXD Register Definitions
  356
- BRGA Divisor Least Significant Byte Register
  357
- Table 20-10. BAL Register Definitions
  357
- Table 20-9. BAL Register
  357
- BRGA Divisor most Significant Byte Register
  358
- Table 20-11. BAH Register
  358
- Table 20-12. BAH Register Definitions
  358
- General Enable Register
  359
- Table 20-13. GER Register
  359
- Table 20-14. GER Register Definitions
  359
- General Interrupt/Bank Register
  360
- Table 20-15. GIR Register
  360
- Table 20-16. GIR Register Definitions
  360
- Table 20-17. Bank Select Bits [6:5]
  361
- Table 20-18. Pending Interrupt Status Bits [3:1]
  361
- Line Control Register
  362
- Table 20-19. LCR Register
  362
- Table 20-20. LCR Register Definitions
  362
- Table 20-21. Parity Modes
  363
- Table 20-22. Stop Bit Lengths
  363
- Table 20-23. Character Bit Lengths
  363
- Loopback Control Register
  364
- Table 20-24. MCTRL Register (Bank 0)
  364
- Table 20-25. MCTRL Register (Bank 1)
  364
- Table 20-26. MCTRL Register Definitions
  364
- Line Status Register
  365
- Table 20-27. LSR Register
  365
- Table 20-28. LSR Register Definitions
  365
- Address/Control Character Register0
  366
- Table 20-29. ACTRL0 Register
  366
- Table 20-30. ACTRL0 Register Definitions
  366
- Table 20-31. TXF Register
  367
- Table 20-32. TXF Register Definitions
  367
- Transmit Character Flag Register
  367
- Received Character Flags Register
  368
- Table 20-33. RXF Register
  368
- Table 20-34. RXF Register Definitions
  368
- Table 20-35. TMCTRL Register
  369
- Table 20-36. TMCTRL Register Definitions
  369
- Timer Control Register
  369
- Table 20-37. TMST Register
  370
- Table 20-38. TMST Register Definitions
  370
- Timer Status Register
  370
- FIFO Level Register
  371
- Table 20-39. FLR Register
  371
- Table 20-40. FLR Register Definitions
  371
- Receive Command Register
  372
- Table 20-41. RCM Register
  372
- Table 20-42. RCM Register Definitions
  372
- Receive Machine Status Register
  373
- Table 20-43. RST Register
  373
- Table 20-44. RST Register Definitions
  373
- Table 20-45. TCM Register
  374
- Table 20-46. TCM Register Definitions
  374
- Transmit Command Register
  374
- Internal Command Register
  375
- Table 20-47. ICM Register
  375
- Table 20-48. ICM Register Definitions
  375
- General Status Register
  376
- Table 20-49. GSR Register
  376
- Table 20-50. GSR Register Definitions
  376
- FIFO Mode Register
  377
- Table 20-51. FMD Register
  377
- Table 20-52. FMD Register Definitions
  377
- Table 20-53. TMD Register
  378
- Table 20-54. TMD Register Definitions
  378
- Transmit Machine Mode Register
  378
- Internal Mode Register
  379
- Table 20-55. IMD Register
  379
- Table 20-56. IMD Register Definitions
  379
- Address/Control Character Register 1
  380
- Table 20-57. ACTRL1 Register
  380
- Table 20-58. ACTRL1 Register Definitions
  380
- Receive Interrupt Enable Register
  381
- Table 20-59. RIE Register
  381
- Table 20-60. RIE Register Definitions
  381
- Receive Machine Mode Register
  382
- Table 20-61. RMD Register
  382
- Table 20-62. RMD Register Definitions
  382
- Clocks Configure Register
  383
- Table 20-63. CLCF Register
  383
- Table 20-64. CLCF Register Definitions
  383
- BRGA Configuration Register
  384
- Table 20-65. BACF Register
  384
- Table 20-66. BACF Register Definitions
  384
- BRGB Divisor Least Significant Byte Register
  385
- Table 20-67. BBL Register
  385
- Table 20-68. BBL Register Definitions
  385
- BRGB Divisor most Significant Byte Register
  386
- Table 20-69. BBH Register
  386
- Table 20-70. BBH Register Definitions
  386
- BRGB Configuration Register
  387
- Table 20-71. BBCF Register
  387
- Table 20-72. BBCF Register Definitions
  387
- Table 20-73. TMIE Register
  388
- Table 20-74. TMIE Register Definitions
  388
- Timer Interrupt Enable Register
  388
- Acknowledge Modes
  389
- UART2 Interrupts
  389
- Interrupt Service
  390
- Table 20-75. Interrupt Service Requirements
  390
- Figure 20-2. Interrupt and Status Reporting Structure
  391
Chapter 21 - General Purpose Input/Output

392
- Figure 21-1. GPIO Block Diagram
  392
- GPIO Features
  393
- GPIO Theory of Operation
  393
- Table 21-1. GPIO Ports
  393
- GPIO Programmer's Model
  394
- GPIO Registers Summary
  394
- Table 21-2. GPIO Register Summary
  394
- GPIO Register Definitions
  395
- Port a Data Register
  395
- Table 21-3. PADR Register
  395
- Table 21-4. PADR Register Definitions
  395
- Port B Data Register
  396
- Table 21-5. PBDR Register
  396
- Table 21-6. PBDR Register Definitions
  396
- Port a Data Direction Register
  397
- Table 21-7. PADDR Register
  397
- Table 21-8. PADDR Register Definitions
  397
- Port B Data Direction Register
  398
- Table 21-10. PBDDR Register Definitions
  398
- Table 21-9. PBDDR Register
  398
- Port C Data Register
  399
- Table 21-11. PCDR Register
  399
- Table 21-12. PCDR Register Definitions
  399
- Port D Data Register
  400
- Table 21-13. PDDR Register
  400
- Table 21-14. PDDR Register Definitions
  400
- Port C Data Direction Register
  401
- Table 21-15. PCDDR Register
  401
- Table 21-16. PCDDR Register Definitions
  401
- Port D Data Direction Register
  402
- Table 21-17. PDDDR Register
  402
- Table 21-18. PDDDR Register Definitions
  402
- Port E Data Register
  403
- Table 21-19. PEDR Register
  403
- Table 21-20. PEDR Register Definitions
  403
- Port F Data Register
  404
- Table 21-21. PFDR Register
  404
- Table 21-22. PFDR Register Definitions
  404
- Port E Data Direction Register
  405
- Table 21-23. PEDDR Register
  405
- Table 21-24. PEDDR Register Definitions
  405
- Port F Data Direction Register
  406
- Table 21-25. PFDDR Register
  406
- Table 21-26. PFDDR Register Definitions
  406
- Port G Data Register
  407
- Table 21-27. PGDR Register
  407
- Table 21-28. PGDR Register Definitions
  407
- Port H Data Register
  408
- Table 21-29. PHDR Register
  408
- Table 21-30. PHDR Register Definitions
  408
- Port G Data Direction Register
  409
- Table 21-31. PGDDR Register
  409
- Table 21-32. PGDDR Register Definitions
  409
- Port H Data Direction Register
  410
- Table 21-33. PHDDR Register
  410
- Table 21-34. PHDDR Register Definitions
  410
- Port I Data Register
  411
- Table 21-35. PIDR Register
  411
- Table 21-36. PIDR Register Definitions
  411
- Port J Data Register
  412
- Table 21-37. PJDR Register
  412
- Table 21-38. PJDR Register Definitions
  412
- Port I Data Direction Register
  413
- Table 21-39. PIDDR Register
  413
- Table 21-40. PIDDR Register Definitions
  413
Chapter 22 - Controller Area Network

414
- Figure 22-1. CAN Controller Block Diagram
  414
- CAN 2.0B Features
  415
- CAN Theory of Operation
  415
- Frame Types
  416
- Message Frame
  416
- Protocols
  416
- Acknowledgement Errors
  417
- Bit Errors
  417
- Message Errors
  417
- Remote Frame
  417
- Transmitted and Received Data
  417
- Bus Arbitration
  418
- Bus Timing
  418
- Time Delays
  418
- CAN Programmer's Model
  419
- Error Handling
  419
- CAN Register Summary
  420
- Table 22-1. CAN Register Summary
  420
- CAN Register Definitions
  421
- Mode Register
  421
- Table 22-2. MOD Register
  421
- Table 22-3. MOD Register Definitions
  421
- Command Register
  422
- Table 22-4. CMR Register
  422
- Table 22-5. CMR Register Definitions
  422
- Status Register
  423
- Table 22-6. SR Register
  423
- Table 22-7. SR Register Definitions
  424
- Interrupt Register
  425
- Table 22-8. IR Register
  425
- Table 22-9. IR Register Definitions
  425
- Interrupt Enable Register
  426
- Table 22-10. IER Register
  426
- Table 22-11. IER Register Definitions
  426
- Bus Timing Register 0
  427
- Table 22-12. BTR0 Register
  427
- Table 22-13. BTR0 Register Definitions
  427
- Bus Timing Register 1
  428
- Figure 22-2. General Structure of a Bit Period
  428
- Table 22-14. BTR1 Register
  428
- Table 22-15. BTR1 Register Definitions
  428
- Arbitration Lost Capture Register
  429
- Table 22-16. ALC Register
  429
- Table 22-17. ALC Register Definitions
  429
- Table 22-18. Arbitration Losses
  430
- Error Code Capture Register
  431
- Table 22-19. ECC Register
  431
- Table 22-20. ECC Register Definitions
  431
- Table 22-22. Segment Code
  432
- Error Warning Limit Register
  433
- Table 22-23. EWLR Register
  433
- Table 22-24. EWLR Register Definitions
  433
- Receive Error Counter Register
  434
- Table 22-25. RXERR Register
  434
- Table 22-26. RXERR Register Definitions
  434
- Transmit Error Counter Register
  435
- Table 22-27. CAN Transmit Buffer
  436
- Transmit Buffer
  436
- Table 22-28. Transmit Frame (SFF)
  437
- Table 22-29. Transmit Frame (EFF)
  437
- Transmit Buffer Descriptor Field
  437
- Table 22-30. Transmit Frame/Receive Frame Definitions
  438
- CAN Receive Buffer
  439
- Table 22-31. CAN Receive Buffer
  439
- Acceptance Code Registers
  440
- Acceptance Mask Registers (AMR0 - AMR3)
  440
- Receive Buffer Descriptor Field
  440
- Table 22-32. Receive Frame (SFF)
  440
- Table 22-33. Receive Frame (EFF)
  440
- Receive Message Counter Register
  441
- Table 22-34. RMC Register
  441
- Table 22-35. RMC Register Definitions
  441
- Receive Buffer Start Address Register
  442
- Table 22-36. RBSA Register
  442
- Table 22-37. RBSA Register Definitions
  442
- CAN Reset Mode
  443
- Table 22-38. Effect of Reset on CAN Controller Registers
  443
- Table 22-21. Error Code
  444
- CAN Acceptance Filtering
  445
- Table 22-39. Standard Frame Format, Single Filter: Receive Buffer and Filter
  446
- Table 22-40. Standard Frame Format, Dual Filters: Receive Buffer and Filters
  446
- Table 22-41. Extended Frame Format, Single Filter: Receive Buffer and Filter
  446
- Table 22-42. Extended Frame Format, Dual Filters: Receive Buffer
  446
Chapter 23 - Analog-To-Digital Converter/Brownout Detector 23.1 ADC Features

447
- Clock Generator
  448
- Figure 23-1. ADC Block Diagram
  448
- Brownout Detector
  450
- Figure 23-2. Bias-And-Control Network Block Diagram
  450
- Figure 23-3. Simplified N-Bit SAR Architecture
  451
- SAR Architecture
  451
- Figure 23-4. Example of a 4-Bit SAR ADC Operation
  452
- ADC Theory of Operation
  453
- ADC Programmer's Model
  454
- ADC Registers Summary
  454
- Table 23-1. Summary of ADC Registers
  454
- ADC Register Definitions
  455
- High Word Register
  455
- Table 23-2. HW Register
  455
- Table 23-3. HW Register Definitions
  455
- Table 23-4. in + Mux Definition
  456
- Control Bank Low Word Register
  457
- Table 23-5. LW Register
  457
- Table 23-6. LW Register Definitions
  457
- Results Register
  458
- Table 23-7. RR Register
  458
- Table 23-8. RR Register Definitions
  458
- Interrupt Masking/Enabling Register
  459
- Table 23-10. IM Register Definitions
  459
- Table 23-9. IM Register
  459
- Power Configuration Register
  460
- Table 23-11. PC Register
  460
- Table 23-12. PC Register Definitions
  460
- Table 23-13. Touch Screen Controller Power Modes
  461
- General Configuration Register
  462
- Table 23-14. GC Register
  462
- Table 23-15. GC Register Definitions
  462
- Sequence Start Mode Issues
  463
- General Status Register
  464
- Table 23-16. GS Register
  464
- Table 23-17. GS Register Definitions
  464
- Interrupt Status Register
  465
- Table 23-18. IS Register
  465
- Table 23-19. IS Register Definitions
  465
- FIFO Status Register
  466
- Table 23-20. FS Register
  466
- Table 23-21. FS Register Definitions
  466
- Control Bank Registers
  467
- Table 23-22. Sample Entries for Control Bank
  467
- Idle High Word Register
  468
- Table 23-23. IHWCTRL Register
  468
- Table 23-24. IHWCTRL Register Definitions
  468
- Idle Low Word Register
  469
- Table 23-25. ILWCTRL Register
  469
- Table 23-26. ILWCTRL Register Definitions
  469
- Masked Interrupt Status Register
  470
- Table 23-27. MIS Register
  470
- Table 23-28. MIS Register Definitions
  470
- Interrupt Clear Register
  471
- Table 23-29. IC Register
  471
- Table 23-30. IC Register Definitions
  471
- ADC Interrupts
  472
- ADC Timing Formulas
  472
- Brownout Interrupt
  473
- End-Of-Sequence Interrupt
  473
- FIFO Watermark Interrupt
  473
- Pen Interrupt
  473
- FIFO Overrun Interrupt
  474
- Figure 23-5. Bias-And-Control Network Block Diagram
  474
Chapter 24 - LCD Pin Multiplexing

475
Chapter 25 - Recommended Layout Practices

478
- Figure 25-1. ESD Filter Circuit Example
  478
- Protecting against Electrostatic Discharge
  478
- Special ESD Considerations
  478
- Figure 25-1. VDD_PLL, VSSA_PLL Filter Circuit
  479
- Printed Circuit Board Layout Practices
  479
- Required VDDA_PLL, VSSA_PLL Filter
  479
- Other Circuit Board Layout Practices
  480
- Unused Input Signal Conditioning
  480
- SMC Registers
  481
- Table 26-1. SMC Register Summary
  481
- RCPC Registers
  482
- Table 26-2. RCPC Register Summary
  482
- Table 26-3. VIC Register Summary
  483
- VIC Registers
  483
- DMA Controller Registers
  485
- IOCON Registers
  485
- Table 26-4. IOCON Register Summary
  485
- Table 26-5. DMA Controller Register Summary
  485
- DMA Stream Registers
  486
- Table 26-6. DMA Stream Register Summary
  486
- CLCDC Registers
  487
- Table 26-7. CLCDC Register Summary
  487
- Table 26-8. HRTFTC Register Summary
  487
- TFTC Registers
  487
- LCDC Registers
  488
- Table 26-9. LCDC Register Summary
  488
- Table 26-10. Timer 0 Register Summary
  489
- Table 26-11. Timer 1 Register Summary
  489
- Table 26-12. Timer 1 Register Summary
  489
- Timer Registers
  489
- RTC Registers
  490
- Table 26-13. WDT Register Summary
  490
- Table 26-14. RTC Register Summary
  490
- WDT Registers
  490
Chapter 26 - Register Map

491

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Sharp Blue Treak LH75410 User Manual (502 pages)

Table of Contents

Chapter 1 - Introduction

Chapter 12 - Direct Memory Access Controller

Chapter 13 - Color Liquid Crystal Display Controller

Chapter 14 - Liquid Crystal Display Controller

Chapter 16 - Watchdog Timer

Chapter 17 - Real-Time Clock

Chapter 18 - Synchronous Serial Port

Chapter 7 - Static Memory Controller

Chapter 2 - LH75401 Soc

Chapter 3 - LH75411 Soc

Chapter 4 - LH75400 Soc

Chapter 5 - LH75410 Soc

Chapter 6 - Memory Interface Architecture

Chapter 8 - Static Random Access Memory Controller

Chapter 9 - Reset, Clock, and Power Controller

Chapter 10 - Vectored Interrupt Controller

Chapter 11 - I/O Configuration

Chapter 15 - Timers

Chapter 19 - UART0 and UART1

Chapter 20 - UART2

Chapter 21 - General Purpose Input/Output

Chapter 22 - Controller Area Network

Chapter 23 - Analog-To-Digital Converter/Brownout Detector 23.1 ADC Features

Chapter 24 - LCD Pin Multiplexing

Chapter 25 - Recommended Layout Practices

Chapter 26 - Register Map

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