Mitsubishi Electric M32170F3VFP Manuals

Manuals and User Guides for Mitsubishi Electric M32170F3VFP. We have 1 Mitsubishi Electric M32170F3VFP manual available for free PDF download: User Manual

Mitsubishi Electric M32170F3VFP User Manual (850 pages)

Mitsubishi 32-bit RISC Single-chip Microcomputers

Brand: Mitsubishi Electric | Category: Computer Hardware | Size: 3.35 MB

Table of Contents
5
Chapter 1 Overview

19
- Outline of the 32170
  19
- M32R Family CPU Core
  20
- Built-In Multiply-Accumulate Operation Function
  21
- Built-In Flash Memory and RAM
  21
- Built-In Clock Frequency Multiplier
  22
- Built-In Powerful Peripheral Functions
  22
- Built-In Full-CAN Function
  24
- Built-In Debug Function
  24
- Block Diagram
  25
- Pin Function
  28
- Pin Layout
  36
- CPU Registers
  43
- General-Purpose Registers
  43
- Control Registers
  45
- Processor Status Word Register: PSW (CR0)
  46
- Condition Bit Register: CBR (CR1)
  47
- Interrupt Stack Pointer: SPI (CR2)
  47
- User Stack Pointer: SPU (CR3)
  47
- Backup PC: BPC (CR6)
  47
- Accumulator
  48
- Program Counter
  48
- Data Formats
  49
- Data Types
  49
- Data Formats
  50
Chapter 3 Address Space

57
- Outline of Address Space
  57
- Operation Modes
  57
- Internal ROM Area and Extended External Area
  57
- Internal ROM Area
  58
- Extended External Area
  58
- Internal RAM Area and SFR Area
  65
- Internal RAM Area
  65
- Special Function Register (SFR) Area
  65
- EIT Vector Entry
  84
- ICU Vector Table
  85
- Note about Address Space
  87
Chapter 4 Eit

89
- Outline of EIT
  89
- EIT Event
  91
- Exception
  91
- Interrupt
  91
- Trap
  91
- EIT Processing Procedure
  92
- EIT Processing Mechanism
  94
- Acceptance of EIT Event
  95
- Saving and Restoring the PC and PSW
  96
- EIT Vector Entry
  98
- Exception Processing
  99
- Reserved Instruction Exception (RIE)
  99
- Address Exception (AE)
  101
- Interrupt Processing
  103
- Reset Interrupt (RI)
  103
- System Break Interrupt (SBI)
  104
- External Interrupt (EI)
  106
- Trap Processing
  108
- Trap (TRAP)
  108
- EIT Priority Levels
  110
- Example of EIT Processing
  111
Chapter 5 Interrupt Controller (Icu)

113
Chapter 6 Internal Memory

135
- Outline of the Internal Memory
  135
- Internal RAM
  135
- Internal Flash Memory
  135
- Registers Associated with the Internal Flash Memory
  135
- Flash Mode Register
  138
- Flash Status Registers
  139
- Flash Controle Registers
  142
- Virtual Flash L Bank Registers
  148
- Virtual Flash S Bank Registers
  149
- Programming of the Internal Flash Memory
  150
- Outline of Programming Flash Memory
  150
- Controlling Operation Mode During Programming Flash
  156
- Programming Procedure to the Internal Flash Memory
  159
- Flash Write Time (for Reference)
  174
- Boot ROM
  176
- Virtual Flash Emulation Function
  177
- Virtual Flash Emulation Area
  179
- Entering Virtual Flash Emulation Mode
  186
- Application Example of Virtual Flash Emulation Mode
  187
- Connecting to a Serial Programmer
  189
- Precautions to be Taken When Rewriting Flash Memory
  191
- Outline of Reset
  193
- Reset Operation
  193
- Reset at Power-On
  194
- Reset During Operation
  194
- Reset Vector Relocation During Flash Rewrite
  194
- Internal State Immediately after Reset Release
  195
- Things to be Considered after Reset Release
  196
- Outline of Input/Output Ports
  197
- Selecting Pin Functions
  197
- Input/Output Port Related Registers
  197
- Port Data Registers
  204
- Port Direction Registers
  206
- Port Operation Mode Registers
  208
- Port Peripheral Circuits
  227
Chapter 9 Dmac

231
- Outline of the DMAC
  231
- DMAC Related Registers
  231
- DMA Channel Control Register
  236
- DMA Software Request Generation Registers
  247
- DMA Source Address Registers
  248
- DMA Destination Address Registers
  249
- DMA Transfer Count Registers
  250
- DMA Interrupt Request Status Registers
  251
- DMA Interrupt Mask Registers
  253
- Functional Description of the DMAC
  257
- Cause of DMA Request
  257
- DMA Transfer Processing Procedure
  261
- Starting DMA
  262
- Channel Priority
  262
- Gaining and Releasing Control of the Internal Bus
  262
- Transfer Counts
  263
- Address Space
  263
- Transfer Operation
  266
- End of DMA and Interrupt
  267
- Status of each Register after Completion of DMA Transfer
  267
- Precautions about the DMAC
  268
Chapter 10 Multijunction Timers

271
Chapter 11 A-D Converters

499
- Outline of A-D Converter
  500
- Conversion Modes
  504
- Operation Modes
  505
- Special Operation Modes
  509
- A-D Converter Interrupt and DMA Transfer Requests
  512
- A-D Converter Related Registers
  513
- A-D Single Mode Register 0
  517
- A-D Single Mode Register 1
  521
- A-D Scan Mode Register 0
  524
- A-D Scan Mode Register 1
  528
- A-D Successive Approximation Register
  531
- A-D0 Comparate Data Register
  533
- 10-Bit A-D Data Registers
  535
- 8-Bit A-D Data Registers
  537
- Functional Description of A-D Converters
  539
- How to Find Along Input Voltages
  539
- A-D Conversion by Successive Approximation Method
  540
- Comparator Operation
  542
- Calculation of the A-D Conversion Time
  543
- Definition of the A-D Conversion Accuracy
  546
- Precautions on Using A-D Converters
  549
Chapter 12 Serial I/O

551
- Outline of Serial I/O
  551
- Serial I/O Related Registers
  551
- SIO Interrupt Related Registers
  557
- SIO Interrupt Control Registers
  559
- SIO Transmit Control Registers
  566
- SIO Transmit/Receive Mode Registers
  568
- SIO Receive Buffer Registers
  572
- SIO Receive Control Registers
  573
- SIO Baud Rate Registers
  576
- Transmit Operation in CSIO Mode
  578
- Setting the CSIO Baud Rate
  578
- Initial Settings for CSIO Transmission
  579
- Starting CSIO Transmission
  581
- Successive CSIO Transmission
  581
- Processing at End of CSIO Transmission
  582
- Transmit Interrupt
  582
- Transmit DMA Transfer Request
  582
- Typical CSIO Transmit Operation
  584
- Receive Operation in CSIO Mode
  586
- Initial Settings for CSIO Reception
  586
- Starting CSIO Reception
  588
- Processing at End of CSIO Reception
  588
- About Successive Reception
  589
- Flags Indicating the Status of CSIO Receive Operation
  590
- Typical CSIO Receive Operation
  591
- Precautions on Using CSIO Mode
  593
- Transmit Operation in UART Mode
  595
- Setting the UART Baud Rate
  595
- UART Transmit/Receive Data Formats
  596
- Initial Settings for UART Transmission
  598
- Starting UART Transmission
  600
- Successive UART Transmission
  600
- Processing at End of UART Transmission
  601
- Transmit Interrupt
  603
- Typical UART Transmit Operation
  603
- Receive Operation in UART Mode
  605
- Initial Settings for UART Reception
  605
- Starting UART Reception
  607
- Processing at End of UART Reception
  607
- Typical UART Receive Operation
  609
- Fixed Period Clock Output Function
  611
- Precautions on Using UART Mode
  612
Chapter 13 Can Module

615
- Outline of the CAN Module
  615
- CAN Module Related Registers
  615
- CAN Control Register
  622
- CAN Status Register
  625
- CAN Extended ID Register
  629
- CAN Configuration Register
  630
- CAN Time Stamp Count Register
  633
- CAN Error Count Registers
  634
- CAN Baud Rate Prescaler
  635
- CAN Interrupt Related Registers
  636
- CAN Mask Registers
  644
- CAN Message Slot Control Registers
  648
- CAN Message Slots
  652
- CAN Protocol
  667
- CAN Protocol Frame
  667
- Initializing the CAN Module
  670
- Initialization of the CAN Module
  670
- Transmitting Data Frames
  673
- Data Frame Transmit Procedure
  673
- Data Frame Transmit Operation
  675
- Transmit Abort Function
  676
- Receiving Data Frames
  677
- Data Frame Receive Procedure
  677
- Data Frame Receive Operation
  679
- Reading out Received Data Frames
  681
- Transmitting Remote Frames
  683
- Remote Frame Transmit Procedure
  683
- Remote Frame Transmit Operation
  685
- Reading out Received Data Frames When Set for Remote Frame Transmission
  688
- Receiving Remote Frames
  690
- Remote Frame Receive Procedure
  690
- Remote Frame Receive Operation
  692
Chapter 14 Real-Time Debugger (Rtd)

695
Chapter 15 External Bus Interface

711
- External Bus Interface Related Signals
  711
- Read/Write Operations
  711
- Bus Arbitration
  711
- Typical Connection of External Extension Memory
  711
Chapter 16 Wait Controller

727
Chapter 17 Ram Backup Mode

747
- Outline
  747
- Example of RAM Backup When Power Is down
  747
- Normal Operating State
  749
- RAM Backup State
  750
- Example of RAM Backup for Saving Power Consumption
  751
- Normal Operating State
  752
- RAM Backup State
  753
- Precautions to be Observed at Power-On
  754
- Exiting RAM Backup Mode (Wakeup)
  755
Chapter 18 Oscillation Circuit

757
- Oscillator Circuit
  758
- Example of an Oscillator Circuit
  758
- System Clock Output Function
  759
- Oscillation Stabilization Time at Power-On
  760
- Clock Generator Circuit
  761
Chapter 19 Jtag

763
- Outline of JTAG
  763
- Configuration of the JTAG Circuit
  763
- JTAG Registers
  763
- Instruction Register (JTAGIR)
  766
- Data Registers
  767
- Basic Operation of JTAG
  768
- Outline of JTAG Operation
  768
- IR Path Sequence
  768
- DR Path Sequence
  768
- Examining and Setting Data Registers
  774
- Boundary Scan Description Language
  776
- Precautions about Board Design When Connecting JTAG
  796
- Configuration of the Power Supply Circuit
  799
- Power-On Sequence
  801
- Power-On Sequence When Not Using RAM Backup
  801
- Power-On Sequence When Using RAM Backup
  802
- Power-Shutdown Sequence
  803
- Power-Shutdown Sequence When Not Using RAM Backup
  803
- Power-Shutdown Sequence When Using RAM Backup
  804
- Absolute Maximum Ratings
  807
- Recommended Operating Conditions
  807
- DC Characteristics
  807
- Electrical Characteristics
  807
- Flash Related Electrical Characteristics
  816
- A-D Conversion Characteristics
  817
- AC Characteristics
  818
- Timing Requirements
  818
- Switching Characteristics
  821
- AC Characteristics
  821
Chapter 22 Typical Characteristics

831
- A-D Conversion Characteristics
  831
Appendix 1 Mechanical Specifications

833
Appendix 1.1 Dimensional Outline Drawing

833

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Mitsubishi Electric M32170F3VFP Manuals

Mitsubishi Electric M32170F3VFP User Manual (850 pages)

Table of Contents

Chapter 1 Overview

Chapter 3 Address Space

Chapter 4 Eit

Chapter 5 Interrupt Controller (Icu)

Chapter 6 Internal Memory

Chapter 9 Dmac

Chapter 10 Multijunction Timers

Chapter 11 A-D Converters

Chapter 12 Serial I/O

Chapter 13 Can Module

Chapter 14 Real-Time Debugger (Rtd)

Chapter 15 External Bus Interface

Chapter 16 Wait Controller

Chapter 17 Ram Backup Mode

Chapter 18 Oscillation Circuit

Chapter 19 Jtag

Chapter 22 Typical Characteristics

Appendix 1 Mechanical Specifications

Appendix 1.1 Dimensional Outline Drawing

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