Hitachi H8S/2645 Manuals

Manuals and User Guides for Hitachi H8S/2645. We have 1 Hitachi H8S/2645 manual available for free PDF download: Hardware Manual

Hitachi H8S/2645 Hardware Manual (1153 pages)

Hitachi 16-Bit Single-Chip Microcomputer H8S/2646 Series

Brand: Hitachi | Category: Desktop | Size: 3.74 MB

Table of Contents
17
Section 1 Overview

33
- Section 1 Overview
  33
  - Overview
    33
- Internal Block Diagram
  38
- Pin Description
  40
  - Pin Arrangement
    40
  - Pin Functions in each Operating Mode
    42
  - Pin Functions
    52
  - Section 2 CPU
    59
Cpu

59
- Overview
  59
  - Features
    59
- Differences between H8S/2600 CPU and H8S/2000 CPU
  60
- Differences from H8/300 CPU
  61
- Differences from H8/300H CPU
  61
- CPU Operating Modes
  62
- Address Space
  67
- Register Configuration
  68
  - Overview
    68
  - General Registers
    69
  - Control Registers
    70
  - Initial Register Values
    72
- Data Formats
  73
  - General Register Data Formats
    73
  - Memory Data Formats
    75
- Instruction Set
  76
- Addressing Modes and Effective Address Calculation
  90
  - Addressing Mode
    90
  - Effective Address Calculation
    93
- Processing States
  97
  - Overview
    97
  - Reset State
    98
  - Exception-Handling State
    99
  - Program Execution State
    102
  - Bus-Released State
    102
  - Power-Down State
    102
- Basic Timing
  103
  - Overview
    103
  - On-Chip Memory (ROM, RAM)
    103
  - On-Chip Supporting Module Access Timing
    105
  - On-Chip HCAN Module Access Timing
    107
  - External Address Space Access Timing
    108
- Usage Note
  108
MCU Operating Modes

111
- Register Configuration
  112
- Overview
  111
  - Operating Mode Selection
    111
- Register Descriptions
  112
- Operating Mode Descriptions
  116
  - Mode 4
    116
  - Mode 5
    116
  - Mode 6
    116
  - Mode 7
    116
- Address Map in each Operating Mode
  117
- Pin Functions in each Operating Mode
  117
Exception Handling

121
- Exception Handling Operation
  122
- Exception Vector Table
  122
- Overview
  121
  - Exception Handling Types and Priority
    121
- Section 4 Exception Handling
  121
- Reset
  124
  - Overview
    124
  - Reset Sequence
    124
  - Interrupts after Reset
    126
  - State of On-Chip Supporting Modules after Reset Release
    127
- Traces
  127
- Interrupts
  128
- Trap Instruction
  129
- Stack Status after Exception Handling
  130
- Notes on Use of the Stack
  131
Interrupt Controller

133
- Block Diagram
  134
- Pin Configuration
  135
- Register Configuration
  135
- Overview
  133
  - Features
    133
- Section 5 Interrupt Controller
  133
- Register Descriptions
  136
- Interrupt Sources
  141
  - External Interrupts
    141
  - Internal Interrupts
    142
  - Interrupt Exception Handling Vector Table
    142
- Interrupt Operation
  146
  - Interrupt Control Modes and Interrupt Operation
    146
  - Interrupt Control Mode 0
    149
  - Interrupt Control Mode 2
    151
  - Interrupt Exception Handling Sequence
    153
  - Interrupt Response Times
    154
- Usage Notes
  155
- DTC Activation by Interrupt
  157
  - Overview
    157
  - Block Diagram
    157
  - Operation
    158
- Overview
  161
  - Features
    161
  - Block Diagram
    162
  - Register Configuration
    163
PC Break Controller (PBC)

161
- Register Descriptions
  163
- Operation
  167
Bus Controller

173
- Block Diagram
  174
- Pin Configuration
  175
- Register Configuration
  175
- Overview
  173
  - Features
    173
- Register Descriptions
  176
- Overview of Bus Control
  186
  - Area Partitioning
    186
  - Bus Specifications
    187
  - Memory Interfaces
    188
  - Interface Specifications for each Area
    189
- Basic Bus Interface
  190
  - Overview
    190
  - Data Size and Data Alignment
    190
  - Valid Strobes
    192
  - Basic Timing
    193
  - Wait Control
    201
- Burst ROM Interface
  203
  - Overview
    203
  - Basic Timing
    203
  - Wait Control
    205
- Idle Cycle
  206
  - Operation
    206
  - Pin States During Idle Cycles
    209
- Write Data Buffer Function
  210
- Bus Arbitration
  211
  - Overview
    211
  - Operation
    211
  - Bus Transfer Timing
    211
- Resets and the Bus Controller
  212
Data Transfer Controller (DTC)

213
- Overview
  213
  - Features
    213
  - Block Diagram
    214
  - Register Configuration
    215
- Register Descriptions
  216
  - DTC Mode Register a (MRA)
    216
  - DTC Mode Register B (MRB)
    218
  - DTC Source Address Register (SAR)
    219
  - DTC Destination Address Register (DAR)
    219
  - DTC Transfer Count Register a (CRA)
    219
  - DTC Transfer Count Register B (CRB)
    220
  - DTC Enable Registers (DTCER)
    220
  - DTC Vector Register (DTVECR)
    221
  - Module Stop Control Register a (MSTPCRA)
    222
- Operation
  224
  - Overview
    224
  - Activation Sources
    226
  - DTC Vector Table
    227
  - Location of Register Information in Address Space
    231
  - Normal Mode
    232
  - Repeat Mode
    233
  - Block Transfer Mode
    234
  - Chain Transfer
    236
  - Operation Timing
    237
  - Number of DTC Execution States
    238
  - Procedures for Using DTC
    240
  - Examples of Use of the DTC
    241
- Interrupts
  244
- Usage Notes
  244
I/O Ports

245
- Overview
  245
- Section 9 I/O Ports
  245
- Port 1
  253
  - Overview
    253
  - Register Configuration
    254
  - Pin Functions
    256
- Port2
  264
  - Overview
    264
  - Register Configuration
    264
  - Pin Functions
    266
- Port3
  274
  - Overview
    274
  - Register Configuration
    274
  - Pin Functions
    277
- Port 4
  279
  - Overview
    279
  - Register Configuration
    280
  - Pin Functions
    280
- Port 5
  281
  - Overview
    281
  - Register Configuration
    282
  - Pin Functions
    283
- Port 9
  285
  - Overview
    285
  - Register Configuration
    286
  - Pin Functions
    286
- Port a
  287
  - Overview
    287
  - Register Configuration
    288
  - Pin Functions
    290
  - MOS Input Pull-Up Function
    292
- Port B
  293
  - Overview
    293
  - Register Configuration
    294
  - Pin Functions
    296
  - MOS Input Pull-Up Function
    297
- Port C
  298
  - Overview
    298
  - Register Configuration
    299
  - Pin Functions
    301
  - MOS Input Pull-Up Function
    302
- Port D
  303
  - Overview
    303
  - Register Configuration
    304
  - Pin Functions
    306
  - MOS Input Pull-Up Function
    307
- Port E
  308
  - Overview
    308
  - Register Configuration
    309
  - Pin Functions
    311
  - MOS Input Pull-Up Function
    311
- Port F
  313
  - Overview
    313
  - Register Configuration
    314
  - Pin Functions
    316
- Port H
  319
  - Overview
    319
  - Register Configuration
    319
  - Pin Functions
    321
- Port J
  321
  - Overview
    321
  - Register Configuration
    322
  - Pin Functions
    323
- Port K
  324
  - Overview
    324
  - Register Configuration
    324
  - Pin Functions
    326
- Overview
  327
  - Features
    327
  - Block Diagram
    331
  - Pin Configuration
    332
  - Register Configuration
    334
Section 10 16-Bit Timer Pulse Unit (TPU)

327
- Register Descriptions
  336
  - Timer Control Register (TCR)
    336
  - Timer Mode Register (TMDR)
    341
  - Timer I/O Control Register (TIOR)
    343
  - Timer Interrupt Enable Register (TIER)
    356
  - Timer Status Register (TSR)
    359
  - Timer Counter (TCNT)
    363
  - Timer General Register (TGR)
    364
  - Timer Start Register (TSTR)
    365
  - Timer Synchro Register (TSYR)
    366
  - Module Stop Control Register a (MSTPCRA)
    367
- Interface to Bus Master
  368
  - 16-Bit Registers
    368
- Operation
  370
  - Overview
    370
  - Basic Functions
    371
  - Synchronous Operation
    377
  - Buffer Operation
    379
  - Cascaded Operation
    383
  - PWM Modes
    385
  - Phase Counting Mode
    390
- Interrupts
  397
  - Interrupt Sources and Priorities
    397
  - DTC Activation
    399
  - A/D Converter Activation
    399
- Operation Timing
  400
  - Input/Output Timing
    400
  - Interrupt Signal Timing
    404
- Usage Notes
  408
- Overview
  419
  - Features
    419
  - Block Diagram
    420
  - Pin Configuration
    421
  - Registers
    422
Section 11 Programmable Pulse Generator (PPG)

419
- Register Descriptions
  423
- Operation
  433
  - Overview
    433
  - Output Timing
    434
  - Normal Pulse Output
    435
  - Non-Overlapping Pulse Output
    437
  - Inverted Pulse Output
    440
  - Pulse Output Triggered by Input Capture
    441
- Usage Notes
  442
- Overview
  445
  - Features
    445
  - Block Diagram
    446
  - Pin Configuration
    448
  - Register Configuration
    448
Section 12 Watchdog Timer

445
- Register Descriptions
  449
  - Timer Counter (TCNT)
    449
  - Timer Control/Status Register (TCSR)
    449
  - Reset Control/Status Register (RSTCSR)
    454
  - Notes on Register Access
    455
- Operation
  457
- Interrupts
  461
- Usage Notes
  461
- Overview
  463
  - Features
    463
  - Block Diagram
    465
  - Pin Configuration
    466
  - Register Configuration
    467
Section 13 Serial Communication Interface (SCI)

463
- Register Descriptions
  468
  - Receive Shift Register (RSR)
    468
  - Receive Data Register (RDR)
    468
  - Transmit Shift Register (TSR)
    469
  - Transmit Data Register (TDR)
    469
  - Serial Mode Register (SMR)
    470
  - Serial Control Register (SCR)
    473
  - Serial Status Register (SSR)
    477
  - Bit Rate Register (BRR)
    481
  - Smart Card Mode Register (SCMR)
    488
  - Module Stop Control Register B (MSTPCRB)
    489
- Operation
  491
  - Overview
    491
  - Operation in Asynchronous Mode
    493
  - Multiprocessor Communication Function
    504
  - Operation in Clocked Synchronous Mode
    512
- SCI Interrupts
  520
- Usage Notes
  521
- Overview
  531
  - Features
    531
  - Block Diagram
    532
  - Pin Configuration
    533
  - Register Configuration
    534
Section 14 Smart Card Interface

531
- Register Descriptions
  535
  - Smart Card Mode Register (SCMR)
    535
  - Serial Status Register (SSR)
    537
  - Serial Mode Register (SMR)
    539
  - Serial Control Register (SCR)
    541
- Operation
  542
  - Overview
    542
  - Pin Connections
    542
  - Data Format
    544
  - Register Settings
    546
  - Clock
    548
  - Data Transfer Operations
    550
  - Operation in GSM Mode
    557
  - Operation in Block Transfer Mode
    558
- Usage Notes
  559
- Overview
  563
  - Features
    563
  - Block Diagram
    564
  - Pin Configuration
    565
  - Register Configuration
    565
Section 15 Hitachi Controller Area Network (HCAN)

563
- Register Descriptions
  567
  - Master Control Register (MCR)
    567
  - General Status Register (GSR)
    568
  - Bit Configuration Register (BCR)
    570
  - Mailbox Configuration Register (MBCR)
    572
  - Transmit Wait Register (TXPR)
    573
  - Transmit Wait Cancel Register (TXCR)
    574
  - Transmit Acknowledge Register (TXACK)
    575
  - Abort Acknowledge Register (ABACK)
    576
  - Receive Complete Register (RXPR)
    577
  - Remote Request Register (RFPR)
    578
  - Interrupt Register (IRR)
    579
  - Mailbox Interrupt Mask Register (MBIMR)
    583
  - Interrupt Mask Register (IMR)
    584
  - Receive Error Counter (REC)
    586
  - Transmit Error Counter (TEC)
    586
  - Unread Message Status Register (UMSR)
    587
  - Local Acceptance Filter Masks (LAFML, LAFMH)
    588
  - Message Control (MC0 to MC15)
    589
  - Message Data (MD0 to MD15)
    593
  - Module Stop Control Register C (MSTPCRC)
    593
- Operation
  594
  - Hardware and Software Resets
    594
  - Initialization after Hardware Reset
    594
  - Transmit Mode
    601
  - Receive Mode
    607
  - HCAN Sleep Mode
    613
  - HCAN Halt Mode
    614
  - Interrupt Interface
    615
  - DTC Interface
    616
- CAN Bus Interface
  617
- Usage Notes
  617
- Overview
  619
  - Features
    619
  - Block Diagram
    620
  - Pin Configuration
    621
  - Register Configuration
    622
Section 16 A/D Converter

619
- Register Descriptions
  623
- Interface to Bus Master
  629
- Operation
  630
  - Single Mode (SCAN = 0)
    630
  - Scan Mode (SCAN = 1)
    632
  - Input Sampling and A/D Conversion Time
    634
  - External Trigger Input Timing
    635
- Interrupts
  636
- Usage Notes
  636
- Overview
  643
  - Features
    643
  - Block Diagram
    644
  - Pin Configuration
    646
  - Register Configuration
    647
Section 17 Motor Control PWM Timer

643
- Register Descriptions
  648
- Bus Master Interface
  658
  - 16-Bit Data Registers
    658
- Operation
  659
  - PWM Channel 1 Operation
    659
  - PWM Channel 2 Operation
    660
- Usage Note
  661
- Overview
  663
  - Features
    663
  - Block Diagram
    664
  - Pin Configuration
    665
  - Register Configuration
    665
Section 18 LCD Controller/Driver

663
- Register Descriptions
  666
- Operation
  673
- Overview
  685
  - Block Diagram
    685
  - Register Configuration
    686
Section 19 RAM

685
- Register Descriptions
  686
  - System Control Register (SYSCR)
    686
- Operation
  687
- Usage Notes
  687
- Features
  689
Section 20 ROM

689
- Overview
  690
  - Block Diagram
    690
  - Mode Transitions
    691
  - On-Board Programming Modes
    692
  - Flash Memory Emulation in RAM
    694
  - Differences between Boot Mode and User Program Mode
    695
  - Block Configuration
    696
- Pin Configuration
  697
- Register Configuration
  698
- Register Descriptions
  698
- On-Board Programming Modes
  705
  - Boot Mode
    705
  - User Program Mode
    710
- Flash Memory Programming/Erasing
  712
  - Program Mode
    714
  - Program-Verify Mode
    715
  - Erase Mode
    719
  - Erase-Verify Mode
    719
- Protection
  721
  - Hardware Protection
    721
  - Software Protection
    722
  - Error Protection
    723
- Flash Memory Emulation in RAM
  725
- Flash Memory Programmer Mode
  727
  - 20.11.1 Socket Adapter Pin Correspondence Diagram
    728
  - 20.11.2 Programmer Mode Operation
    730
  - 20.11.3 Memory Read Mode
    731
  - 20.11.4 Auto-Program Mode
    734
  - 20.11.5 Auto-Erase Mode
    736
  - 20.11.6 Status Read Mode
    738
  - 20.11.7 Status Polling
    739
  - 20.11.8 Programmer Mode Transition Time
    739
  - 20.11.9 Notes on Memory Programming
    740
- Interrupt Handling When Programming/Erasing Flash Memory
  727
- Flash Memory and Power-Down States
  741
  - 20.12.1 Notes on Power-Down States
    741
- Flash Memory Programming and Erasing Precautions
  742
- Overview
  747
  - Block Diagram
    747
  - Register Configuration
    748
Section 21 Clock Pulse Generator

747
- Register Descriptions
  748
  - System Clock Control Register (SCKCR)
    748
  - Low-Power Control Register (LPWRCR)
    749
- Oscillator
  750
  - Connecting a Crystal Resonator
    750
- Bus Master Clock Selection Circuit
  753
- Medium-Speed Clock Divider
  753
- PLL Circuit
  753
- Subclock Oscillator
  754
- Note on Crystal Resonator
  755
- Subclock Waveform Generation Circuit
  755
- Overview
  757
  - Register Configuration
    761
Section 22 Power-Down Modes

757
- Register Descriptions
  762
- Medium-Speed Mode
  770
- Sleep Mode
  771
  - Exiting Sleep Mode
    771
- Module Stop Mode
  772
  - Usage Notes
    773
- Software Standby Mode
  774
- Hardware Standby Mode
  777
  - Hardware Standby Mode Timing
    778
- Watch Mode
  778
  - Exiting Watch Mode
    779
  - Notes
    779
- Sub-Sleep Mode
  780
  - Exiting Sub-Sleep Mode
    780
- Sub-Active Mode
  781
  - 22.10.2 Exiting Sub-Active Mode
    781
- Clock Output Disabling Function
  782
- Direct Transitions
  782
  - 22.11.1 Overview of Direct Transitions
    782
- Usage Notes
  783
- Absolute Maximum Ratings
  785
Section 23 Electrical Characteristics

785
- Power Supply Voltage and Operating Frequency Range
  786
- DC Characteristics
  787
- AC Characteristics
  792
  - Clock Timing
    793
  - Control Signal Timing
    795
  - Bus Timing
    797
  - Timing of On-Chip Supporting Modules
    803
- A/D Conversion Characteristics
  808
- LCD Characteristics
  809
- Flash Memory Characteristics
  810
Appendix A Instruction Set

813
- Instruction List
  813
- A.2 Instruction Codes
  837
- Instruction Codes
  837
- Operation Code Map
  852
- Number of States Required for Instruction Execution
  856
- Bus States During Instruction Execution
  870
- Condition Code Modification
  884
- Address
  890
Appendix B Internal I/O Register

890
- B.2 Functions
  906
- Functions
  906
Appendix C I/O Port Block Diagrams

1107
- C.2 Port 2 Block Diagrams
  1113
- Port 2 Block Diagrams
  1113
- C.3 Port 3 Block Diagrams
  1115
- Port 3 Block Diagrams
  1115
- C.4 Port 4 Block Diagram
  1122
- Port 4 Block Diagram
  1122
- C.5 Port 5 Block Diagrams
  1123
- Port 5 Block Diagrams
  1123
- C.6 Port 9 Block Diagram
  1127
- Port 9 Block Diagram
  1127
- C.7 Port a Block Diagram
  1128
- Port a Block Diagram
  1128
- C.8 Port B Block Diagram
  1129
- Port B Block Diagram
  1129
- C.9 Port C Block Diagram
  1130
- Port C Block Diagram
  1130
- C.10 Port D Block Diagram
  1131
- Port D Block Diagram
  1131
- C.11 Port E Block Diagram
  1132
- Port E Block Diagram
  1132
- C.12 Port F Block Diagrams
  1133
- Port F Block Diagrams
  1133
- C.13 Port G Block Diagram
  1140
- Port G Block Diagram
  1140
- C.14 Port J Block Diagram
  1141
- Port J Block Diagram
  1141
- C.15 Port K Block Diagram
  1142
- Port K Block Diagram
  1142
Appendix D Pin States

1143
Appendix E Timing of Transition to and Recovery

1150
Appendix F Package Dimensions

1150

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Hitachi H8S/2645 Hardware Manual (1153 pages)

Table of Contents

Section 1 Overview

Cpu

MCU Operating Modes

Exception Handling

Interrupt Controller

PC Break Controller (PBC)

Bus Controller

Data Transfer Controller (DTC)

I/O Ports

Section 10 16-Bit Timer Pulse Unit (TPU)

Section 11 Programmable Pulse Generator (PPG)

Section 12 Watchdog Timer

Section 13 Serial Communication Interface (SCI)

Section 14 Smart Card Interface

Section 15 Hitachi Controller Area Network (HCAN)

Section 16 A/D Converter

Section 17 Motor Control PWM Timer

Section 18 LCD Controller/Driver

Section 19 RAM

Section 20 ROM

Section 21 Clock Pulse Generator

Section 22 Power-Down Modes

Section 23 Electrical Characteristics

Appendix A Instruction Set

Appendix B Internal I/O Register

Appendix C I/O Port Block Diagrams

Appendix D Pin States

Appendix E Timing of Transition to and Recovery

Appendix F Package Dimensions

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