Page 1 S3C8275X/F8275X/C8278X /F8278X/C8274X/F8274X 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.4...
Page 2: Important Notice
Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 3: April,
NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea PRODUCT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-bit CMOS Microcontroller DOCUMENT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's Manual, Revision1.4 DOCUMENT NUMBER: 21.4-S3-C8275X/F8275X/C8278X/F8278X/C8274X/F8274X-042007 EFFECTIVE DATE: April, 2007 SUMMARY: As a result of additional product testing and evaluation, some specifications published in the S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's Manual, Revision 1, have been changed.
Page 4: Revision History
REVISION HISTORY Revision Date Remark February, 2005 Preliminary spec for internal release only. April, 2005 First edition. Reviewed by Finechips. July, 2005 Second edition. Reviewed by Finechips. August, 2005 Third edition. Reviewed by Finechips. May, 2006 Fourth edition. Reviewed by Finechips April, 2007 Fifth edition.
Page 5: Electrical Data
REVISION DESCRIPTIONS 1. Electrical Data Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM ° ° = − 25 C to + 85 C, V = 2.0 V to 3.6 V) Parameter Symbol Conditions Unit − − − µs Programming time −...
Page 6 2. CHAPTHER 17. Electrical Data It is changed “V = 2.0 V to 3.6 V” into “V = 2.2 V to 3.6 V” in the Table 17-12. 3. DEVICE NAME The device name is changed S3C8275/F8275/C8278/F8278/C8274/F8274 to S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X. The ‘X’ means ‘Commercial type’.
Page 7 Preface The S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller User's Manual is designed for application designers and programmers who are using the S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure.
Page 8: Table Of Contents
Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series Microcontrollers ........................1-1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller............1-1 Flash................................1-1 Features ................................1-2 Block Diagram ...............................1-3 Pin Assignment .............................1-4 Pin Descriptions ............................1-6 Pin Circuits ..............................1-8 Chapter 2 Address Spaces Overview................................2-1 Program Memory (ROM)..........................2-2 Smart Option............................2-3...
Page 9 Overview ............................... 4-1 Chapter 5 Interrupt Structure Overview ............................... 5-1 Interrupt Types ............................. 5-2 S3C8275X/C8278X/C8274X Interrupt Structure ................. 5-3 Interrupt Vector Addresses ........................5-4 Enable/Disable Interrupt Instructions (EI, DI) ..................5-6 System-Level Interrupt Control Registers.................... 5-6 Interrupt Processing Control Points ..................... 5-7 Peripheral Interrupt Control Registers ....................
Page 10 I/O Ports Overview................................9-1 Port Data Registers ..........................9-2 port 0..............................9-3 port 1..............................9-7 port 2..............................9-11 port 3..............................9-13 Port 4 ..............................9-15 Port 5 ..............................9-17 Port 6 ..............................9-19 Chapter 10 Basic Timer Overview................................10-1 Basic Timer Control Register (BTCON) ....................10-2 Basic Timer Function Description......................10-3 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER...
Page 11 SIO Control Registers (SIOCON) ......................14-2 SIO Pre-Scaler Register (SIOPS) ......................14-3 SIO Block Diagram ............................14-3 Serial I/O Timing Diagram (SIO) ......................14-4 Chapter 15 Battery Level Detector Overview ............................... 15-1 Battery Level Detector Control Register (BLDCON)................15-2 viii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER...
Page 12 Chapter 19 S3F8275X/F8278X/F8274X Flash MCU Overview................................19-1 Operating Mode Characteristics ......................19-5 Chapter 20 Development Tools Overview................................20-1 SHINE ..............................20-1 SAMA Assembler..........................20-1 SASM88..............................20-1 HEX2ROM ............................20-1 Target Boards ............................20-1 TB8275/8/4 Target Board ........................20-3 SMDS2+ Selection (SAM8) ........................20-6 Idle LED ..............................20-6 Stop LED ..............................20-6 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER...
Page 13 1-10 Pin Circuit Type H-10 (P2.0)..................1-11 Program Memory Address Space ................2-2 Smart Option.......................2-3 Internal Register File Organization (S3C8275X)............2-6 Internal Register File Organization (S3C8278X/C8274X)..........2-7 Register Page Pointer (PP) ..................2-8 Set 1, Set 2, Prime Area Register, and LCD Data Register Map.......2-11 8-Byte Working Register Areas (Slices) ..............2-12...
Page 14 Oscillator Control Register (OSCCON) ..............7-6 7-11 STOP Control Register (STPCON)................7-8 S3C8275X/C8278X/C8274X I/O Port Data Register Format ........9-2 Port 0 High-Byte Control Register (P0CONH)............9-4 Port 0 Low-Byte Control Register (P0CONL) ............9-4 Port 0 Pull-up Control Register (P0PUR) ..............9-5 External Interrupt Control Register, Low Byte (EXTICONL)........
Page 15 Flash Memory User-Programming Enable Register (FMUSR) ........16-3 16-3 Flash Memory Sector Address Register, High Byte (FMSECH) ........16-4 16-4 Flash Memory Sector Address Register, Low Byte (FMSECL) .........16-4 16-5 Program Memory Address Space ................16-5 16-6 Sector Configurations in User Program Mode ............16-7 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xiii...
Page 16 S3F8275X/F8278X/F8274X Pin Assignments (64-LQFP-1010) ....... 19-3 19-3 Operating Voltage Range ..................19-7 20-1 SMDS Product Configuration (SMDS2+)..............20-2 20-2 TB8275/8/4 Target Board Configuration..............20-3 20-3 40-Pin Connectors (J101, J102) for TB8275/8/4 ............20-7 20-4 S3E8270 Cables for 64-QFP Package ..............20-7 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER...
Page 17 Instruction Notation Conventions ................6-9 Opcode Quick Reference................... 6-10 Condition Codes......................6-12 S3C8275X/C8278X/C8274X Set 1 Register and Values After RESET ..... 8-2 S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RESET....8-3 S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RESET....8-4 S3C8275X/C8278X/C8274X Port Configuration Overview ........
Page 18 17-12 A.C. Electrical Characteristics for Internal Flash ROM ..........17-13 19-1 Descriptions of Pins Used to Read/Write the Flash ROM..........19-4 19-2 Comparison of S3F8275X/F8278X/F8274X and S3C8275X/C8278X/C8274X Features...............19-4 19-3 Operating Mode Selection Criteria ................19-5 19-4 D.C. Electrical Characteristics ..................19-6 20-1 Power Selection Settings for TB8275/8/4..............20-4 20-2 Main-clock Selection Settings for TB8275/8/4............20-4...
Page 19 How to clear an interrupt pending bit......................5-15 Chapter 7: Clock Circuit Switching the CPU Clock.......................... 7-7 Chapter 16: Embedded Flash Memory Interface Sector Erase ............................. 16-8 Program ..............................16-10 Reading..............................16-11 Hard Lock Protection ..........................16-12 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xvii...
Page 20 Stack Pointer (High Byte) ................... 4-42 Stack Pointer (Low Byte).................... 4-42 STPCON Stop Control Register ....................4-43 System Mode Register ....................4-44 TACON Timer 1/A Control Register..................4-45 TBCON Timer B Control Register.................... 4-46 WTCON Watch Timer Control Register..................4-47 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER...
Page 21 Enable Interrupts ......................6-40 ENTER Enter ........................... 6-41 EXIT Exit..........................6-42 IDLE Idle Operation......................6-43 Increment ........................6-44 INCW Increment Word......................6-45 IRET Interrupt Return ......................6-46 Jump........................... 6-47 Jump Relative......................6-48 Load..........................6-49 Load Bit ........................6-51 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER...
Page 22 Subtract with Carry .....................6-77 Set Carry Flag......................6-78 Shift Right Arithmetic ....................6-79 SRP/SRP0/SRP1 Set Register Pointer....................6-80 STOP Stop Operation......................6-81 Subtract ........................6-82 SWAP Swap Nibbles......................6-83 Test Complement under Mask ...................6-84 Test under Mask ......................6-85 Wait for Interrupt ......................6-86 Logical Exclusive OR....................6-87 xxii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER...
Page 23: Chapter 1 Product Overview
PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: • Efficient register-oriented architecture •...
Page 24: Features
Data Memory (RAM) • - Including LCD display data memory Stop: selected system clock and CPU clock stop - 544 × 8 bits data memory(S3C8275X/F8275X) Oscillation Sources - 288 × 8 bits data memory(S3C8278X/F8278X) • Crystal, ceramic, or RC for main clock - 288 ×...
Page 25: Block Diagram
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW BLOCK DIAGRAM Watchdog Timer TAOUT/P0.4 8-Bit Timer/ nRESET 16-Bit T1CLK/P0.3 Counter A Basic Timer Timer/ 8-Bit Timer/ TBOUT/P0.5 Counter 1 Counter B Low Voltage Reset P0.0/INT0 Clock Out P0.1/INT1 CLKOUT/P0.6 Block P0.2/INT2 Port I/O and Interrupt Control P0.3/T1CLK...
Page 26: Pin Assignment
COM0/P6.0 SEG15/P4.0 COM1/P6.1 SEG16/P3.7 COM2/P6.2 SEG17/P3.6 COM3/P6.3 SEG18/P3.5 VLC0 SEG19/P3.4 S3C8275X/F8275X VLC1 SEG20/P3.3 VLC2 SEG21/P3.2 S3C8278X/F8278X SEG22/P3.1 S3C8274X/F8274X SEG23/P3.0 SEG24/P2.7 SEG25/P2.6 TEST (64-QFP-1420F) SEG26/P2.5 SEG27/P2.4 SEG28/P2.3 nRESET SEG29/P2.2 SEG30/P2.1 P0.0/INT0 SEG31/P2.0/V BLDREF P0.1/INT1 P1.7/INT7 Figure 1-2. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-QFP-1420F)
Page 27 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW SEG0/P5.7 SEG17/P3.6 COM0/P6.0 SEG18/P3.5 COM1/P6.1 SEG19/P3.4 COM2/P6.2 SEG20/P3.3 COM3/P6.3 SEG21/P3.2 S3C8275X/F8275X VLC0 SEG22/P3.1 S3C8278X/F8278X VLC1 SEG23/P3.0 VLC2 SEG24/P2.7 S3C8274X/F8274X SEG25/P2.6 SEG26/P2.5 SEG27/P2.4 (64-LQFP-1010) SEG28/P2.3 TEST SEG29/P2.2 SEG30/P2.1 SEG31/P2.0/V BLDREF nRESET P1.7/INT7 Figure 1-3. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-LQFP-1010)
Page 28: Pin Descriptions
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PIN DESCRIPTIONS Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions Circuit Shared Names Type Description Type Functions I/O port with bit-programmable pins; P0.0−P0.2 18−20 INT0−INT2 P0.3 Schmitt trigger input or push-pull, open-drain T1CLK P0.4 output and software assignable pull-ups; TAOUT P0.5...
Page 29 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions (Continued) Circuit Shared Names Type Description Type Functions − − − LCD power supply pins. VLC0−VLC2 6−8 External interrupts input pins. INT0−INT2 18−20 P0.0−P0.2 INT3−INT7 29−33 P1.3−P1.7 T1CLK Timer 1/A external clock input.
Page 30: Pin Circuits
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PIN CIRCUITS Pull-Up P-Channel Resistor N-Channel Schmitt Trigger Figure 1-5. Pin Circuit Type B (nRESET) Figure 1-4. Pin Circuit Type A Pull-up Resistor Resistor Open Enable Drain P-CH Data N-CH Output Disable Schmitt Trigger Figure 1-6. Pin Circuit Type E-4 (P0, P1)
Page 31: Pin Circuit Type H-4
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW COM/SEG Output Disable Figure 1-7. Pin Circuit Type H-4 Pull-Up Resistor Resistor Enable Open Drain P-CH Data Output N-CH Disable 1 Circuit Type H-4 Output Disable 2 Figure 1-8. Pin Circuit Type H-8 (P2.1 P2.7, P3)
Page 32: Pin Circuit Type H-9 (P4, P5, P6)
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pull-Up Resistor Resistor Enable P-CH Data Output N-CH Disable 1 COM/SEG Circuit Type H-4 Output Disable 2 Figure 1-9. Pin Circuit Type H-9 (P4, P5, P6) 1 - 10...
Page 33: Pin Circuit Type H-10 (P2.0)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW Pull-Up Resistor Resistor Enable Open-Drain P-CH Data Output N-CH Disable 1 Circuit Alternative Type H-4 Function BLDEN BLD Select To BLD Figure 1-10. Pin Circuit Type H-10 (P2.0) 1-11...
Page 34: Chapter 2 Address Spaces
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C8275X has an internal 16-Kbyte mask-programmable ROM. The S3C8278X has an internal 8-Kbyte mask-programmable ROM. The S3C8274X has an internal 4-Kbyte mask-programmable ROM.
Page 35: Program Memory (Rom)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3C8275X has 16K bytes internal mask- programmable program memory, the S3C8278X has 8K bytes, the S3C8274X has 4K bytes. The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory.
Page 36: Smart Option
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES SMART OPTION ROM Address: 003EH Not used (note) ISP reset vector change enable/disable bit: ISP protection size selection: 0 = OBP reset vector address 00 = 256 bytes 1 = Normal vector (address 0100H) 01 = 512 bytes...
Page 37 The ISP of smart option (003EH) is available in the S3F8275X only. The default value of ROM address 003EH is FFH. And ROM address 003EH should be kept FFH when used the S3C8275X/C8278X/F8278X/C8274X/F8274X. The LVR of smart option (003FH) is available in all the device, S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X. The default value of ROM address 003FH is FFH.
Page 38: Register Architecture
(bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3C8275X the total number of addressable 8-bit registers is 605. Of these 605 registers, 13 bytes are for CPU and system control registers, 16 bytes are for LCD data registers, 48 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 512 registers are for general-purpose use, page 0-page 1 (in case of S3C8278X/C8274X, page 0).
Page 39: Internal Register File Organization (S3C8275X)
Mode, and Stack (Register Addressing Mode) Operations) General Purpose Register Bytes (Register Addressing Mode) Page 0 Page 2 Prime Data Registers Bytes Prime Data Registers (All Addressing Modes) Bytes (All addressing modes) LCD Display Reigster Figure 2-3. Internal Register File Organization (S3C8275X)
Page 40: Internal Register File Organization (S3C8278X/C8274X)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES Set1 Bank 1 Bank 0 Page 0 System and Peripheral Control Bytes System and Set 2 Registers Peripheral Control Registers General-Purpose (Register Addressing Mode) Data Registers Bytes (Indirect Register, Indexed System Registers Mode, and Stack (Register Addressing Mode)
Page 41: Register Page Pointer (Pp)
Not used for the S3C8275X/C8278X/C8274X NOTES: In the S3C8275X microcontroller, the internal register file is configured as three pages (Pages 0-2). The pages 0-1 are used for general purpose register file, and page 2 is used for LCD data register or general purpose register.
Page 42: Using The Page Pointer For Ram Clear (Page 0, Page 1)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1) ; Destination ← 0, Source ← 0 PP,#00H #0C0H R0,#0FFH ; Page 0 RAM clear starts RAMCL0 DJNZ R0,RAMCL0 ; R0 = 00H ;...
Page 43: Register Set 1
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For the S3C8275X, the set 2 address range (C0H–FFH) is accessible on pages 0–1.
Page 44: Prime Register Space
ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C8275X/C8278X/C8274X's two or one 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset.
Page 45: Working Registers
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices."...
Page 46: Using The Register Points
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
Page 47: Non-Contiguous 16-Byte Working Register Block
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X F7H (R7) 8-Byte Slice F0H (R0) 16-Byte Register File Contiguous Contains 32 1 1 1 1 0 X X X working 8-Byte Slices Register block 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R0) Figure 2-9.
Page 48: Register Addressing
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2.
Page 49: Register File Addressing
C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). LCD Data NOTE: In the S3C8275X/C8278X/C8274X microcontroller, Registers pages 0-2 are implemented. Pages 0-2 contain all of the addressable registers in the internal register file.
Page 50: Common Working Register Area (C0H-Cfh)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area.
Page 51: 4-Bit Working Register Addressing
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Examples 1. LD 0C2H,40H ; Invalid addressing mode!
Page 52: Bit Working Register Addressing Example
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES Selects RP0 or RP1 Address OPCODE 4-bit address Register pointer provides three provides five low-order bits high-order bits Together they create an 8-bit register address Figure 2-13. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0...
Page 53: 8-Bit Working Register Addressing
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B."...
Page 54: Bit Working Register Addressing Example
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 8-bit address Register form instruction 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1...
Page 55: System And User Stack
SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C8275X/C8278X/C8274X, the SPL must be initialized to an 8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general- purpose register, if necessary.
Page 56: Standard Stack Operations Using Push And Pop
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES Programming TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SPL ← FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...
Page 57: Chapter 3 Addressing Modes
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
Page 58: Register Addressing Mode (R)
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Page 59: Indirect Register Addressing Mode (Ir)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
Page 60: Indirect Register Addressing To Program Memory
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...
Page 61: Indirect Working Register Addressing To Register File
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points Program Memory to start fo working register 4-bit block 3 LSBs Working Register Point to the OPCODE ADDRESS...
Page 62: Indirect Working Register Addressing To Program Or Data Memory
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register 4-bit Working block Register Address Register Next 2-bit Point Pair OPCODE...
Page 63: Indexed Addressing Mode (X)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
Page 64: Indexed Addressing To Program Or Data Memory With Short Offset
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address Point to Working...
Page 65: Indexed Addressing To Program Or Data Memory
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of Program Memory working register OFFSET block OFFSET NEXT 2 Bits 4-bit Working Register dst/src Register Address...
Page 66: Direct Address Mode (Da)
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
Page 67: Direct Addressing For Call And Jump Instructions
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.
Page 68: Indirect Address Mode (Ia)
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Page 69: Relative Address Mode (Ra)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.
Page 70: Immediate Mode (Im)
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
Page 71: Set 1 Registers
CONTROL REGISTERS OVERVIEW In this chapter, detailed descriptions of the S3C8275X/C8278X/C8274X control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.
Page 72: Set 1, Bank 0 Registers
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Address Decimal Oscillator control register OSCCON SIO control register SIOCON SIO data register SIODATA SIO pre-scaler register SIOPS Port 0 control register (high byte) P0CONH Port 0 control register (low byte)
Page 73: Set 1, Bank 1 Registers
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Address Decimal LCD control Register LCON Watch timer control register WTCON Timer A counter TACNT Timer B counter TBCNT Timer A data register TADATA Timer B data register...
Page 74: Register Description Format
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Bit number(s) that is/are appended to Name of individual the register name for bit addressing bit or related bits Register location in the internal Register address register file Register ID Full Register name (hexadecimal) FLAGS - System Flags Register...
Page 75: Bldcon Battery Level Detector Control Register
– – Read/Write – – Addressing Mode Register addressing mode only .7–.6 Not used for the S3C8275X/C8278X/C8274X Source Bit Internal source External source Battery Level Detector Output Bit > V (when BLD is enabled) < V (when BLD is enabled)
Page 76: Btcon Basic Timer Control Register
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTCON — Basic Timer Control Register Set 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) Disable watchdog timer function Other values Enable watchdog timer function .3–.2...
Page 77: Clkcon System Clock Control Register
Oscillator IRQ Wake-up Function Bit Enable IRQ for main wake-up in power down mode Disable IRQ for main wake-up in power down mode .6–.5 Not used for the S3C8275X/C8278X/C8274X (must keep always “0”) (note) .4–.3 CPU Clock (System Clock) Selection Bits...
Page 78: Clocon Clock Output Control Register
– – – Read/Write – – – – – – Addressing Mode Register addressing mode only .7–.2 Not used for the S3C8275X/C8278X/C8274X (must keep always “0”) .1–.0 Clock Output Frequency Selection Bits Select fxx/64 Select fxx/16 Select fxx/8 Select fxx/4...
Page 79 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER EXTICONH — Set 1, Bank 0 External Interrupt Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.7 External Interrupt (INT7) Configuration Bits Disable interrupt Enable interrupt by falling edge...
Page 80 CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X EXTICONL — Set 1, Bank 0 External Interrupt Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.3 External Interrupt (INT3) Configuration Bits Disable interrupt Enable interrupt by falling edge...
Page 81 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER EXTIPND — External Interrupt Pending Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P1.7/INT7 Interrupt Pending Bit Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending (when read) P1.6/INT6 Interrupt Pending Bit...
Page 82: Flags System Flags Register
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X FLAGS — System Flags Register Set 1 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode Carry Flag (C) Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7...
Page 83: Fmcon Flash Memory Control Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER FMCON — Flash Memory Control Register Set 1, Bank 1 Bit Identifier Reset Value – – Read/Write – – Addressing Mode Register addressing mode only .7–.4 Flash Memory Mode Selection Bits Programming mode Sector erase mode Hard lock mode...
Page 84: Fmsech Flash Memory Sector Address Register (High Byte)
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X FMSECH — Set 1, Bank 1 Flash Memory Sector Address Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.0 Flash Memory Sector Address Bits (High Byte) The 15th - 8th bits to select a sector of flash ROM NOTE: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.
Page 85: Fmusr Flash Memory User Programming Enable Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER FMUSR — Set 1, Bank 1 Flash Memory User Programming Enable Register Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.0 Flash Memory User Programming Enable Bits 1 0 1 0 0 1 0 1 Enable user programming mode...
Page 86: Imr Interrupt Mask Register
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Interrupt Mask Register Set 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P1.4–1.7 Disable (mask) Enable (unmask) Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.3...
Page 87: Iph Instruction Pointer (High Byte)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER — Instruction Pointer (High Byte) Set 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
Page 88: Ipr Interrupt Priority Register
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Interrupt Priority Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode (note) .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C Group priority undefined B >...
Page 89: Irq Interrupt Request Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER — Interrupt Request Register Set 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Level 7 (IRQ7) Request Pending Bit; External Interrupt P1.4–1.7 Not pending Pending Level 6 (IRQ6) Request Pending Bit; External Interrupt P1.3...
Page 90: Lcon Lcd Control Register
"x" means don't care. When 1/2 bias is selected, the bias levels are set as V ), and V Not used for the S3C8275X/C8278X/C8274X LCD Display Control Bit Turn display off (Turn off the P-Tr) Turn display on (Turn on the P-Tr)
Page 91: Osccon Oscillator Control Register
The OSCCON.7 must be maintained to “1”, during the sub oscillator operation. A capacitor (0.1uF) should be connected between V and GND. .6–.4 Not used for the S3C8275X/C8278X/C8274X Main Oscillator Control Bit Main oscillator RUN Main oscillator STOP Sub Oscillator Control Bit...
Page 92: P0Conh Port 0 Control Register (High Byte)
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P0CONH — Port 0 Control Register (High Byte) Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.7/BUZ Configuration Bits Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (BUZ) .5–.4...
Page 93: P0Conl Port 0 Control Register (Low Byte)
Register addressing mode only .7–.6 P0.3/T1CLK Configuration Bits Schmitt trigger input mode (T1CLK) N-channel open-drain output mode Push-pull output mode Not used for the S3C8275X/C8278X/C8274X .5–.4 P0.2/INT2 Configuration Bits Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275X/C8278X/C8274X .3–.2...
Page 94: P0Pur Port 0 Pull-Up Control Register
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P0PUR — Port 0 Pull-Up Control Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode P0.7's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P0.6's Pull-up Resistor Enable Bit...
Page 95: P1Conh Port 1 Control Register (High Byte)
Register addressing mode only .7–.6 P1.7/INT7 Configuration Bits Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275X/C8278X/C8274X .5–.4 P1.6/INT6 Configuration Bits Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275X/C8278X/C8274X .3–.2...
Page 96: P1Conl Port 1 Control Register (Low Byte)
Register addressing mode only .7–.6 P1.3/INT3 Configuration Bits Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275X/C8278X/C8274X .5–.4 P1.2/SI Configuration Bits Schmitt trigger input mode (SI) N-channel open-drain output mode Push-pull output mode Not used for the S3C8275X/C8278X/C8274X .3–.2...
Page 97: P1Pur Port 1 Pull-Up Control Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P1PUR — Port 1 Pull-up Control Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode P1.7's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P1.6's Pull-up Resistor Enable Bit...
Page 98: P2Conh Port 2 Control Register (High Byte)
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P2CONH — Port 2 Control Register (High Byte) Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P2.7/SEG24 Configuration Bits Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG24) .5-.4...
Page 99: P2Conl Port 2 Control Register (Low Byte)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P2CONL — Port 2 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P2.3/SEG28 Configuration Bits Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG28) .5–.4...
Page 100: P2Pur Port 2 Pull-Up Control Register
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P2PUR — Port 2 Pull-up Control Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode P2.7's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P2.6's Pull-up Resistor Enable Bit...
Page 101: P3Conh Port 3 Control Register (High Byte)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P3CONH — Port 3 Control Register (High Byte) Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P3.7/SEG16 Configuration Bits Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG16) .5–.4...
Page 102: P3Conl Port 3 Control Register (Low Byte)
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P3CONL — Port 3 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P3.3/SEG20 Configuration Bits Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG20) .5–.4...
Page 103: P3Pur Port 3 Pull-Up Control Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P3PUR — Port 3 Pull-up Control Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode P3.7's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P3.6's Pull-up Resistor Enable Bit...
Page 104: P4Conh Port 4 Control Register (High Byte)
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P4CONH — Port 4 Control Register (High Byte) Set 1, Bank 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P4.7/SEG8 Configuration Bits Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG8) .5–.4...
Page 105: P4Conl Port 4 Control Register (Low Byte)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P4CONL — Port 4 Control Register (Low Byte) Set 1, Bank 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P4.3/SEG12 Configuration Bits Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG12) .5–.4...
Page 106: P5Conh Port 5 Control Register (High Byte)
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P5CONH — Port 5 Control Register (High Byte) Set 1, Bank 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P5.7/SEG0 Configuration Bits Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG0) .5–.4...
Page 107: P5Conl Port 5 Control Register (Low Byte)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P5CONL — Port 5 Control Register (Low Byte) Set 1, Bank 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P5.3/SEG4 Configuration Bits Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG4) .5–.4...
Page 108: P6Con Port 6 Control Register
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P6CON — Port 6 Control Register Set 1, Bank 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.6 P6.3/COM3 Configuration Bits Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (COM3) .5–.4...
Page 109: Pp Register Page Pointer
Not used for the S3C8275X/C8278X/C8274X NOTES: In the S3C8275X microcontroller, the internal register file is configured as three pages (Pages 0-2). The pages 0-1 are used for general purpose register file, and page 2 is used for LCD data register or general purpose registers.
Page 110: Rp0 Register Pointer 0
8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H–C7H. .2–.0 Not used for the S3C8275X/C8278X/C8274X — Register Pointer 1 Set 1 Bit Identifier Reset Value –...
Page 111: Siocon Sio Control Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER SIOCON — SIO Control Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only SIO Shift Clock Selection Bit Internal clock (P.S clock) External clock (SCK) Data Direction Control Bit MSB-first mode...
Page 112: Sph Stack Pointer (High Byte)
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Stack Pointer (High Byte) Set 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8).
Page 113: Stpcon Stop Control Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER STPCON — Stop Control Register Set 1, Bank 0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7–.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE: Before execute the STOP instruction, set this STPCON register as “10100101b”.
Page 114: Sym System Mode Register
Bit Identifier Reset Value – – Read/Write – – Addressing Mode Register addressing mode only This bit must remain logic "0" .6–.5 Not used for the S3C8275X/C8278X/C8274X .4–.2 Fast Interrupt Level Selection Bits IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7...
Page 115: Tacon Timer 1/A Control Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER TACON — Timer 1/A Control Register Set 1, Bank 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Timer 1 Operating Mode Selection Bit Two 8-bit timers mode (timer A/B) One 16-bit timer mode (timer 1) .6–.4...
Page 116: Tbcon Timer B Control Register
— Timer B Control Register Set 1, Bank 1 Bit Identifier Reset Value – Read/Write – Addressing Mode Register addressing mode only Not used for the S3C8275X/C8278X/C8274X .6–.4 Timer B Clock Selection Bits fxx/512 fxx/256 fxx/64 fxx/8 fxt (sub clock) Others...
Page 117: Wtcon Watch Timer Control Register
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER WTCON — Watch Timer Control Register Set 1, Bank 1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Watch Timer Clock Selection Bit Main system clock divided by 2 (fx/128) Sub system clock (fxt)
Page 118: Overview
Sources A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each vector can have several interrupt sources. In the S3C8275X/C8278X/C8274X interrupt structure, there are twelve possible interrupt sources. When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually"...
Page 119: Interrupt Types
) + multiple sources (S − V − S − S Type 3: One level (IRQn) + multiple vectors (V ) + multiple sources (S In the S3C8275X/C8278X/C8274X microcontroller, two interrupt types are implemented. Levels Vectors Sources Type 1: IRQn Type 2:...
Page 120: S3C8275X/C8278X/C8274X Interrupt Structure
INTERRUPT STRUCTURE S3C8275X/C8278X/C8274X INTERRUPT STRUCTURE The S3C8275X/C8278X/C8274X microcontroller supports twelve interrupt sources. All twelve of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.
Page 121: Interrupt Vector Addresses
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8275X/C8278X/C8274X interrupt structure are stored in the vector address area of the internal 16-Kbyte ROM, 0H−3FFFH, or 8, 4-Kbyte (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
Page 122: Interrupt Vectors
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE Table 5-1. Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Interrupt Priority in Value Value Level Level − √ 100H Basic timer overflow Reset √ Timer B match IRQ0 √ Timer 1/A match − √ SIO interrupt IRQ1 −...
Page 123: Enable/Disable Interrupt Instructions (Ei, Di)
Interrupt priority register Controls the relative processing priorities of the interrupt levels. The seven levels of S3C8275X/C8278X/C8274X are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
Page 124: Interrupt Processing Control Points
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) —...
Page 125: Peripheral Interrupt Control Registers
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers...
Page 126: System Mode Register (Sym)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4−SYM.2, is undetermined.
Page 127: Interrupt Mask Register (Imr)
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
Page 128: Interrupt Priority Register (Ipr)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
Page 129: Interrupt Priority Register (Ipr)
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W Group priority: Group A: 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ1 > IRQ0 Group B: = Undefined 0 = IRQ2 > (IRQ3, IRQ4) = B >...
Page 130: Interrupt Request Register (Irq)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.
Page 131: Interrupt Pending Function Types
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.
Page 132: Interrupt Source Polling Sequence
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.
Page 133: Generating Interrupt Vector Addresses
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H−FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack.
Page 134 When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”). NOTE For the S3C8275X/C8278X/C8274X microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7, can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1.
Page 135: Data Types
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM88RC instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: •...
Page 136: Instruction Group Summary
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load bit dst,src Load external data memory dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrement...
Page 137 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions dst,src Add with carry dst,src dst,src Compare Decimal adjust Decrement DECW Decrement word dst,src Divide Increment INCW Increment word MULT dst,src Multiply dst,src Subtract with carry...
Page 138 INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal...
Page 139 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic SWAP Swap nibbles CPU Control Instructions Complement carry flag...
Page 140: Flags Register (Flags)
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7−FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic.
Page 141: Flag Descriptions
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Page 142: Instruction Set Notation
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation −...
Page 143: Instruction Notation Conventions
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0−15) Bit (b) of working register Rn.b (n = 0−15, b = 0−7) Bit 0 (LSB) of working register Rn (n = 0−15)
Page 144: Opcode Quick Reference
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) − r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1...
Page 145 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) − DJNZ NEXT r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER EXIT IDLE ↓ ↓ ↓ ↓ ↓ ↓ ↓...
Page 146: Condition Codes
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"...
Page 147: Instruction Descriptions
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: •...
Page 148: Adc Add With Carry
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Add with carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed.
Page 149: Add Add
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Page 150: And Logical And
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
Page 151: Band Bit And
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source).
Page 152: Bcp Bit Compare
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Bit Compare dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.
Page 153: Bitc Bit Complement
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 154: Bitr Bit Reset
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BITR — Bit Reset BITR dst.b dst(b) ← 0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 155: Bits Bit Set
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 156: Bor Bit Or
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Bit OR dst,src.b dst.b,src dst(0) ← dst(0) OR src(b) Operation: dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.
Page 157: Btjrf Bit Test, Jump Relative On False
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 158: Btjrt Bit Test, Jump Relative On True
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b If src(b) is a "1", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 159: Bxor Bit Xor
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.
Page 160: Call Call Procedure
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
Page 161: Ccf Complement Carry Flag
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
Page 162: Clr Clear
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
Page 163: Com Complement
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 164: Cp Compare
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Page 165: Cpije Compare, Increment, And Jump On Equal
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.
Page 166: Cpijne Compare, Increment, And Jump On Non-Equal
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA "0", PC ← PC + RA Operation: If dst – src Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement...
Page 167: Da Decimal Adjust
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not...
Page 168 INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Decimal Adjust (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1,R0 R1 ←...
Page 169: Dec Decrement
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
Page 170: Decw Decrement Word
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DECW — Decrement Word DECW dst ← dst – 1 Operation: The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.
Page 171: Di Disable Interrupts
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
Page 172: Div Divide (Unsigned)
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Divide (Unsigned) dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.
Page 173: Djnz Decrement And Jump If Non-Zero
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
Page 174: Ei Enable Interrupts
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Enable Interrupts SYM (0) ← 1 Operation: An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
Page 175: Enter Enter
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET ENTER — Enter ENTER ← Operation: SP – 2 ← ← ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.
Page 176: Exit Exit
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X EXIT — Exit EXIT ← Operation: ← SP + 2 ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.
Page 177: Idle Idle Operation
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. In application programs, a IDLE instruction must be immediately followed by at least three NOP instructions.
Page 178: Inc Increment
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
Page 179: Incw Increment Word
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.
Page 180: Iret Interrupt Return
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) FLAGS ← @SP PC ↔ IP Operation: SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.
Page 181: Jp Jump
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
Page 182: Jr Jump Relative
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
Page 183: Ld Load
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
Page 184 INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...
Page 185: Ldb Load Bit
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.
Page 186: Ldc/Lde Load Memory
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.
Page 187 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: ;...
Page 188: Ldcd/Lded Load Memory And Decrement
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 189: Ldci/Ldei Load Memory And Increment
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 190 INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src rr ← rr – 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented.
Page 191: Ldcpi/Ldepi Load Memory With Pre-Increment
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented.
Page 192: Ldw Load Word
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Load Word dst,src dst ← src Operation: The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode...
Page 193: Mult Multiply (Unsigned)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
Page 194: Next Next
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X NEXT — Next NEXT PC ← @ IP Operation: IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.
Page 195: Nop No Operation
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.
Page 196: Or Logical Or
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
Page 197: Pop Pop From Stack
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
Page 198: Popud Pop User Stack (Decrementing)
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X POPUD — Pop User Stack (Decrementing) POPUD dst,src dst ← src Operation: IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.
Page 199: Popui Pop User Stack (Incrementing)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.
Page 200: Push Push To Stack
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
Page 201: Pushud Push User Stack (Decrementing)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.
Page 202: Pushui Push User Stack (Incrementing)
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src IR ← IR + 1 Operation: dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.
Page 203: Rcf Reset Carry Flag
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
Page 204: Ret Return
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
Page 205: Rl Rotate Left
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Page 206: Rlc Rotate Left Through Carry
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
Page 207: Rr Rotate Right
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Page 208: Rrc Rotate Right Through Carry
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
Page 209: Sb0 Select Bank 0
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Select Bank 0 BANK ← 0 Operation: The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.
Page 210: Sb1 Select Bank 1
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Select Bank 1 BANK ← 1 Operation: The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.)
Page 211: Sbc Subtract With Carry
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Subtract with Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
Page 212: Scf Set Carry Flag
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex)
Page 213: Sra Shift Right Arithmetic
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
Page 214: Srp/Srp0/Srp1
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SRP/SRP0/SRP1 — Set Register Pointer SRP0 SRP1 ← Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) src (3–7) ← If src (1) = 0 and src (0) = 1 then: RP1 (3–7) src (3–7)
Page 215: Stop Stop Operation
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
Page 216: Sub Subtract
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Page 217: Swap Swap Nibbles
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET SWAP — Swap Nibbles SWAP dst (0 – 3) ↔ dst (4 – 7) Operation: The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise.
Page 218: Tcm Test Complement Under Mask
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
Page 219: Tm Test Under Mask
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
Page 220: Wfi Wait For Interrupt
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Wait for Interrupt Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt.
Page 221: Xor Logical Exclusive Or
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
Page 222: System Clock Circuit
CLOCK CIRCUIT OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency of S3C8275X/C8278X/C8274X is determined by CLKCON register settings.
Page 223: Main Oscillator Circuits
CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MAIN OSCILLATOR CIRCUITS SUB OSCILLATOR CIRCUITS 32.768 kHz Figure 7-1. Crystal/Ceramic Oscillator (fx) Figure 7-4. Crystal Oscillator (fxt) Figure 7-5. External Oscillator (fxt) Figure 7-2. External Oscillator (fx) Figure 7-3. RC Oscillator (fx)
Page 224: Clock Status During Power-Down Modes
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: • In stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with RC delay noise filter).
Page 225: System Clock Control Register (Clkcon)
/2, or f System Clock Control Register (CLKCON) D4H, Set 1, R/W Oscillator IRQ wake-up function bit: Not used for S3C8275X/C8278X/C8274X 0 = Enable IRQ for main wake up in (must keep always 0) power down mode 1 = Disable IRQ for main wake up in...
Page 226: Clock Output Control Register (Clocon)
After a reset, fxx/64 is select for clock output frequency because the reset value of CLOCON.1−.0 is "00b". Clock Output Control Register (CLOCON) E8H, Set 1, Bank 1, R/W Not used for S3C8275X/C8278X/C8274X (must keep always "0") Clock output frequency selection bits:...
Page 227: Oscillator Control Register (Osccon)
The sub oscillator can be stopped or run by setting OSCCON.2. Oscillator Control Register (OSCCON) E0H, Set 1, Bank 0, R/W System clock selection bit: Not used for S3C8275X/ 0 = Main oscillator select C8278X/C8274X 1 = Sub oscillator select...
Page 228: Switching The Cpu Clock
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT SWITCHING THE CPU CLOCK Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies.
Page 229: Stop Control Register (Stpcon)
CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X STOP Control Register (STPCON) FBH, Set 1, Bank 0, R/W STOP control bits: Other values = Disable STOP instruction 10100101 = Enable STOP instruction NOTE: Before execute the STOP instruction, set this STPCON register as "10100101B". Otherwise the STOP instuction will not execute as well as reset will be generated.
Page 230: System Reset
CPU clock. This procedure brings the S3C8275X/C8278X/C8274X into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance.
Page 231: Hardware Reset Values
An "x" means that the bit value is undefined after a reset. • A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value. Table 8-1. S3C8275X/C8278X/C8274X Set 1 Register and Values After RESET Register Name Mnemonic...
Page 232: S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After Reset
RESET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X and POWER-DOWN Table 8-2. S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET − − − − Oscillator control register OSCCON SIO control register SIOCON SIO data register SIODATA SIO pre-scaler register...
Page 233: S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After Reset
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 8-3. S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET − LCD control register LCON Watch timer control register WTCON Timer A counter TACNT Timer B counter...
Page 234: Power-Down Modes
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode. The external interrupts in the S3C8275X/C8278X/C8274X interrupt structure that can be used to release Stop mode are: •...
Page 235: Idle Mode
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals remain active.
Page 236: S3C8275X/C8278X/C8274X Port Configuration Overview
The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3C8275X/C8278X/C8274X can be configured to input or output mode. P2−P6 are shared with LCD signals. Table 9-1 gives you a general overview of S3C8275X/C8278X/C8274X I/O port functions.
Page 237: Port Data Registers
PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C8275X/C8278X/C8274X I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1.
Page 238: Port
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 0 Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location F0H in set 1, bank 0. P0.0-P0.7 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 239: Port 0 High-Byte Control Register (P0Conh)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 0 Control Register, High Byte (P0CONH) E4H, Set 1, Bank 0, R/W P0.7/BUZ P0.5/TBOUT P0.6/CLKOUT P0.4/TAOUT P0CONH bit-pair pin configuration settings: Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (BUZ, CLKOUT, TBOUT, TAOUT) Figure 9-2.
Page 240: Port 0 Pull-Up Control Register (P0Pur)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS Port 0 Pull-up Control Register (P0PUR) E6H, Set 1, Bank 0, R/W P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P0PUR bit configuration settings: Disable pull-up resistor Enable pull-up resistor NOTE: A pull-up resistor of port 0 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function.
Page 241: External Interrupt Pending Register (Extipnd)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X External Interrupt Pending Register (EXTIPND) F7H, Set 1, Bank 0, R/W P1.7 P1.6 P1.5 P1.4 P1.3 P0.2 P0.1 P0.0 (INT7) (INT6) (INT5) (INT4) (INT3) (INT2) (INT1) (INT0) EXTIPND bit configuration settings: No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-6.
Page 242: Port
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location F1H in set 1, bank 0. P1.0−P1.7 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 243: Port 1 High-Byte Control Register (P1Conh)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 1 Control Register, High Byte (P1CONH) E7H, Set 1, Bank 0, R/W P1.7/INT7 P1.6/INT6 P1.5/INT5 P1.4/INT4 P1CONH bit-pair pin configuration settings: Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not available Figure 9-7. Port 1 High-Byte Control Register (P1CONH)
Page 244: Port 1 Pull-Up Control Register (P1Pur)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS Port 1 Pull-up Control Register (P1PUR) E9H, Set 1, Bank 0, R/W P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P1PUR bit configuration settings: Disable pull-up resistor Enable pull-up resistor NOTE: A pull-up resistor of port 1 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function.
Page 245: External Interrupt Control Register, Low Byte (Exticonl)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X External Interrupt Control Register, Low Byte (EXTICONL) F9H, Set 1, Bank 0, R/W P1.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 EXTICONL bit configuration settings: Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9-11.
Page 246: Port 2 High-Byte Control Register (P2Conh)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location F2H in set 1, Bank 0. P2.0-P2.7 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 247: Port 2 Low-Byte Control Register (P2Conl)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 2 Control Register, Low Byte (P2CONL) EBH, Set 1, Bank 0, R/W P2.3/SEG28 P2.2/SEG29 P2.1/SEG30 P2.0/SEG31/V BLDREF P2CONL bit-pair pin configuration settings: Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG28-SEG31/V BLDREF Figure 9-14. Port 2 Low-byte Control Register (P2CONL)
Page 248: Port 3 High Byte Control Register (P3Conh)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 3 Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F3H in set 1, bank 0. P3.0-P3.7 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 249: Port 3 Low Byte Control Register (P3Conl)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 3 Control Register, Low Byte (P3CONL) EEH, Set 1, Bank 0, R/W P3.3/SEG20 P3.2/SEG21 P3.1/SEG22 P3.0/SEG23 P3CONL bit-pair pin configuration settings: Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG20-SEG23) Figure 9-17. Port 3 Low Byte Control Register (P3CONL)
Page 250: Port 4 High-Byte Control Register (P4Conh)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location F4H in set 1, bank 0. P4.0-P4.7 can serve as inputs (with or without pull- up), as push-pull output or you can be configured the following functions.
Page 251: Port 4 Low-Byte Control Register (P4Conl)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 4 Control Register, Low Byte (P4CONL) EAH, Set 1, Bank 1, R/W P4.3/SEG12 P4.2/SEG13 P4.1/SEG14 P4.0/SEG15 P4CONH bit-pair pin configuration settings: Input mode Input with pull-up resistor Push-pull output mode Alternative function (SEG12-SEG15) Figure 9-20. Port 4 Low-Byte Control Register (P4CONL)
Page 252: Port 5 High-Byte Control Register (P5Conh)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location F5H in set 1, bank 0. P5.0-P5.7 can serve as inputs (with or without pull- up), as push-pull output or you can be configured the following functions.
Page 253: Port 5 Low-Byte Control Register (P5Conl)
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 5 Control Register, Low Byte (P5CONL) ECH, Set 1, Bank 1, R/W P5.3/SEG4 P5.2/SEG5 P5.1/SEG6 P5.0/SEG7 P5CONL bit-pair pin configuration settings: Input mode Input with pull-up resistor Push-pull output mode Alternative function (SEG4-SEG7) Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)
Page 254: Port 6 Control Register (P6Con)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 6 Port 6 is a 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location F6H in set 1, bank 0. P6.0-P6.3 can serve as inputs (with or without pull- up), as push-pull output or you can be configured the following functions.
Page 255: Overview
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: • As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. • To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
Page 256: Basic Timer Control Register (Btcon)
BASIC TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using Register addressing mode.
Page 257: Basic Timer Function Description
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7−BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function.
Page 258: Basic Timer Block Diagram
BASIC TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus /4096 Clear /1024 8-Bit Up Counter /128 (BTCNT, Read-Only) RESET (note) Start the CPU Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
Page 259: One 16-Bit Timer Mode (Timer 1)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.
Page 260: Timer 1/A Control Register (Tacon)
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to • Enable the timer 1 operating (interval timer) • Select the timer 1 input clock frequency • Clear the timer 1 counter, TACNT and TBCNT •...
Page 261: Timer 1 Block Diagram (One 16-Bit Mode)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 BTCON.0 TACON.6-.4 1/512 TACON.3 Data Bus 1/256 TACON.2 or XT 1/64 Clear TBCNT TACNT TACON.1 Match 16-Bit Comparator TACON.0 T1INT T1CLK TAOUT TBDATA TADATA Buffer Buffer Match Signal T1CLR TBDATA TADATA Data Bus NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) Figure 11-2.
Page 262: Two 8-Bit Timers Mode (Timer A And B)
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
Page 263: Timer 1/A Control Register (Tacon)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 TACON and TBCON are located in set 1, bank 1, at address E6H and E7H, and is read/write addressable using Register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt.
Page 264: Timer B Control Register (Tbcon)
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Timer B Control Register (TBCON) E7H, Set 1, Bank 1, R/W Timer B interrupt pending bit: Not used for 0 = No interrupt pending (when read) S3C8275X/C8278X/C8274X Clear pending bit (when write) 1 = Interrupt is pending (when read)
Page 265: Timer A Block Diagram(Two 8-Bit Timers Mode)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 BTCON.0 TACON.6-.4 1/512 1/256 Data Bus TACON.3 TACON.2 or XT 1/64 Clear TACNT (8-Bit Up-Counter) TACON.1 Match 8-Bit Comparator TACON.0 TAINT T1CLK TAOUT TADATA Buffer Match Signal TACLR TADATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) Figure 11-5.
Page 266: Timer B Block Diagram (Two 8-Bit Timers Mode)
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTCON.0 TBCON.6-.4 1/512 TBCON.3 Data Bus 1/256 TBCON.2 or XT Clear 1/64 TBCNT (8-Bit Up-Counter) TBCON.1 Match 8-Bit Comparator TBCON.0 TBINT TBOUT TBDATA Buffer Match Signal TBCLR TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) Figure 11-6.
Page 267: Overview
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt (IRQ 2, vector F6H), then set the WTCON.6 to "1".
Page 268: Watch Timer Control Register (Wtcon)
WATCH TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in set 1, bank 1 at address E1H, and is read/write addressable using Register addressing mode.
Page 269: Watch Timer Circuit Diagram
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER WATCH TIMER CIRCUIT DIASGRAM WTCON.7 WTCON.6 WT INT Enable BUZ (P0.7) WTCON.6 WTCON.5 WTCON.4 WTINT /64 (0.5 kHz) WTCON.3 /32 (1 kHz) /16 (2 kHz) /8 (4 kHz) WTCON.2 Enable/Disable Selector WTCON.1 WTCON.0 Circuit WTCON.0 (Pending Bit)
Page 270: Lcd Function Diagram
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER LCD CONTROLLER/DRIVER OVERVIEW The S3C8275X/C8278X/C8274X microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel. Its LCD block has the following components: • LCD controller/driver • Display RAM (00H−0FH of page 2) for storing display data •...
Page 271: Lcd Circuit Diagram
LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CIRCUIT DIAGRAM SEG31/P2.0 Port Latch SEG/Port SEG16/P3.7 Driver SEG15/P4.0 SEG0/P5.7 Display COM3/P6.3 COM2/P6.2 (200H-20FH) COM/Port Driver COM0/P6.0 Timing Controller LCON Voltage Controller Figure 13-2. LCD Circuit Diagram 13-2...
Page 272: Lcd Ram Address Area
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER LCD RAM ADDRESS AREA RAM addresses of page 2 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
Page 273: Lcd Control Register (Lcon)
(Turn off the P-Tr) 1 = Turn display on (Turn on the P-Tr) LCD clock selection bits: 00 = fw/2 (64 Hz) Not used for S3C8275X/C8278X/C8274X 01 = fw/2 (128 Hz) LCD duty and bias selection bits: 10 = fw/2 (256 Hz)
Page 274: Lcd Voltage Dividing Resistor
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER LCD VOLTAGE DIVIDING RESISTOR Static and 1/3 Bias 1/2 Bias S3C8275X/C8278X/C8274X S3C8275X/C8278X/C8274X LCON.0 LCON.0 LCON.7 = 0: Enable internal resistors LCON.7 = 0: Enable internal resistors Voltage Dividing Resistor Adjustment S3C8275X/C8278X/C8274X LCON.0 LCON.7 = 1: Disable internal resistors NOTES: R = Internal LCD dividing resistors.
Page 275: Segment (Seg) Signals
LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. • In 1/4 duty mode, COM0-COM3 pins are selected • In 1/3 duty mode, COM0-COM2 pins are selected •...
Page 276: Select/No-Select Signal In 1/2 Duty, 1/2 Bias Display Mode
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER Select Non-Select 1 Frame LC 0 LC1, 2 LC 0 LC1, 2 LC 0 LC1, 2 COM-SEG LC1, 2 LC 0 Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode Select Non-Select 1 Frame COM-SEG Figure 13-8.
Page 277: Lcd Signals And Wave Forms Example In 1/4 Duty, 1/3 Bias Display Mode
LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SEG1.4 x C0 1 Frame COM0 COM1 SEG0.1 x C1 COM2 COM3 SEG2.1 x C1 SEG0.3 x C3 SEG1.7 x C3 SEG0 SEG1 COM0 -SEG0 COM0 -SEG1 COM1 -SEG0 COM1 -SEG1 Figure 13-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode...
Page 278: Programming Procedure
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: • 8-bit control register (SIOCON) • Clock selector logic •...
Page 279: Sio Control Registers (Siocon)
SERIAL I/O INTERFACE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in set 1, bank 0. It has the control setting for SIO module. • Clock source selection (internal or external) for shift clock •...
Page 280: Sio Block Diagram
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, is located at E3H in set 1, bank 0. The value stored in the SIO pre-scaler register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.
Page 281: Serial I/O Timing Diagram (Sio)
SERIAL I/O INTERFACE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIAL I/O TIMING DIAGRAM (SIO) Transmit SIO INT Complete Set SIOCON.3 Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) Transmit SIO INT Complete Set SIOCON.3 Figure 14-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
Page 282: Block Diagram For Voltage Level Detect
BATTERY LEVEL DETECTOR OVERVIEW The S3C8275X/C8278X/C8274X micro-controller has a built-in BLD (Battery Level Detector) circuit which allows detection of power voltage drop or external input level through software. Turning the BLD operation on and off can be controlled by software. Because the IC consumes a large amount of current during BLD operation. It is recommended that the BLD operation should be kept OFF unless it is necessary.
Page 283: Battery Level Detector Control Register (Bldcon)
BATTERY LEVEL DETECTOR S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON) The bit 3 of BLDCON controls to run or disable the operation of Battery Level Detector. Basically this V is set as 2.2V by system reset and it can be changed in 3 kinds voltages by selecting Battery Level Detector Control Register (BLDCON).
Page 284: Overview
S3F8275X EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW This chapter is only for the S3F8275X. The S3F8275X has an on-chip full-flash memory internally instead of masked ROM. The flash memory is accessed by "LDC" instruction and the type of sector erase and a byte programmable flash, a user can program the data in the flash memory area any time you want.
Page 285: User Program Mode
EMBEDDED FLASH MEMORY INTERFACE S3F8275X USER PROGRAM MODE This mode supports sector erase, byte programming, byte read and one protection mode (Hard lock protection). The read protection mode is available only in Tool Program mode. So in order to make a chip into read protection, you need to select a read protection option when you program an initial your code to a chip by using Tool Program mode by using a programming tool.
Page 286: Flash Memory User-Programming Enable Register (Fmusr)
S3F8275X EMBEDDED FLASH MEMORY INTERFACE Flash Memory User Programming Enable Register The FMUSR register is used for a safety operation of the flash memory. This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming mode is disabled, because the value of FMUSR is "00000000B"...
Page 287: Flash Memory Sector Address Register, High Byte (Fmsech)
EMBEDDED FLASH MEMORY INTERFACE S3F8275X Flash Memory Sector Address Registers There are two sector address registers for addressing a sector to be erased. The FMSECL (Flash Memory Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Sector Address Register High Byte) indicates the high byte of sector address.
Page 288: Isp Tm (On-Board Programming) Sector
S3F8275X EMBEDDED FLASH MEMORY INTERFACE (ON-BOARD PROGRAMMING) SECTOR sectors located in program memory area can store on board program software (boot program code for upgrading application code by interfacing with I/O pin). The ISP sectors can not be erased or programmed by LDC instruction for the safety of On Board Program software.
Page 289: Isp Sector Size
EMBEDDED FLASH MEMORY INTERFACE S3F8275X Table 16-1. ISP Sector Size Smart Option(003EH) ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bit 2 Bit 1 Bit 0 − 100H – 1FFH (256 byte) 256 Bytes 100H – 2FFH (512 byte) 512 Bytes 100H –...
Page 290: Sector Erase
S3F8275X EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit of flash memory to be erased and programmed in User Program Mode is called sector. The program memory of S3F8275X is divided into 128 sectors for unit of erase and programming.
Page 291: Sector Erase
EMBEDDED FLASH MEMORY INTERFACE S3F8275X The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B". 2. Set Flash Memory Sector Address Register (FMSECH/FMSECL). 3. Check user’s ID code (written by user). 4.
Page 292: Programming
S3F8275X EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one byte unit after sector erase. And for programming safety's sake, must set FMSECH and FMSECL to flash memory sector value. The write operation of programming starts by 'LDC' instruction. You can write until 128byte, because this flash sector's limits is 128byte.
Page 293: Program
EMBEDDED FLASH MEMORY INTERFACE S3F8275X PROGRAMMING TIP ⎯ Program • • FMUSR,#0A5H ; User Program mode enable FMSECH,#17H FMSECL,#80H ; Set sector address (1780H−17FFH) R2,#17H ; Set a ROM address in the same sector 1780H−17FFH R3,#84H R4,#78H ; Temporary data UserID_Code,#User_value ;...
Page 294: Reading
S3F8275X EMBEDDED FLASH MEMORY INTERFACE READING The read operation of programming starts by 'LDC' instruction. The Reading Procedure in User Program Mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register. 3.
Page 295: Hard Lock Protection
EMBEDDED FLASH MEMORY INTERFACE S3F8275X HARD LOCK PROTECTION User can set Hard Lock Protection by write ‘0110’ in FMCON.7−4. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution (in the tool program mode).
Page 296: Overview
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C8275X/C8278X/C8274X electrical characteristics are presented in tables and graphs. The information is arranged in the following order: • Absolute maximum ratings • D.C. electrical characteristics • Data retention supply voltage in Stop mode •...
Page 297: Absolute Maximum Ratings
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit − − 0.3 to + 4.6 Supply voltage − 0.3 to V Input voltage Ports 0–6 + 0.3 − − 0.3 to V Output voltage + 0.3...
Page 298 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (Continued) ° ° = − 25 C to + 85 C, V = 2.0 V to 3.6 V) Parameter Symbol Conditions Unit − − µA Input low = 0 V; –3 LIL1...
Page 299 ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-2. D.C. Electrical Characteristics (Concluded) ° ° = − 25 C to + 85 C, V = 2.0 V to 3.6 V) Unit Parameter Symbol Conditions − Run mode: 8.0 MHz Supply current = 3.3 V ± 0.3 V Crystal oscillator 4.0 MHz...
Page 300: Stop Mode Release Timing When Initiated By An External Interrupt
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-3. Data Retention Supply Voltage in Stop Mode ° ° = − 25 C to + 85 Parameter Symbol Conditions Unit − − Data retention supply DDDR voltage ° − − µA Data retention supply Stop mode, T...
Page 301: Stop Mode Release Timing When Initiated By A Reset
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Oscillation RESET Stabilization Occurs TIme Stop Mode Normal Data Retention Mode Operating Mode DDDR Execution of STOP Instrction nRESET 0.8 V 0.2 V WAIT is the same as 16 × 1/BT clock. NOTE: WAIT Figure 17-2. Stop Mode Release Timing When Initiated by a RESET Table 17-4.
Page 302: Input Timing For External Interrupts
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-5. A.C. Electrical Characteristics ° ° = − 25 C to + 85 C, V = 2.0 V to 3.6 V) Parameter Symbol Conditions Unit − − SCK cycle time External SCK source 1,000 Internal SCK source...
Page 303: Input Timing For Reset
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X nRESET 0.2 V Figure 17-4. Input Timing for RESET 0.8V 0.2V 0.8V 0.2V Output Data Figure 17-5. Serial Data Transfer Timing 17-8...
Page 304: Lvr (Low Voltage Reset) Timing
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-6. Battery Level Detector Electrical Characteristics ° = 25 C, V = 2.0 V to 3.6 V) Parameter Symbol Conditions Unit − − Operating voltage of BLD DDBLD Voltage of BLD BLDCON.2-.0 = 000b BLDCON.2-.0 = 101b 2.15...
Page 305: Main Oscillation Characteristics
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-8. Main Oscillation Characteristics ° ° = − 25 C to + 85 Oscillator Clock Configuration Parameter Test Condition Units 2.5 V − 3.6 V − Crystal Main oscillation frequency 2.0 V − 3.6 V −...
Page 306: Main Oscillation Stabilization Time
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-10. Main Oscillation Stabilization Time ° ° = − 25 C to + 85 C, V = 2.0 V to 3.6 V) Oscillator Test Condition Unit − − Crystal fx > 1 MHz − − Ceramic...
Page 307: Sub Oscillation Stabilization Time
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-11. Sub Oscillation Stabilization Time ° ° = − 25 C to + 85 C, V = 2.0 V to 3.6 V) Oscillator Test Condition Unit − − Crystal – − µs input high and low width (t...
Page 308: Operating Voltage Range
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.05 MHz 4.2 MHz 6.25 kHz(main)/8.2 kHz(sub) 400 kHz (main)/32.8 kHz(sub) Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 17-9.
Page 309: Pin Qfp Package Dimensions (64-Qfp-1420F)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C8275X/C8278X/C8274X microcontroller is currently available in a 64-pin QFP and LQFP package. ± 0.30 23.90 ± 0.20 20.00 + 0.10 0.15 - 0.05 64-QFP-1420F 0.10 MAX + 0.10 0.40 - 0.05 0.05 MIN 1.00...
Page 310: Pin Lqfp Package Dimensions (64-Lqfp-1010)
MECHANICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 12.00 BSC 10.00 BSC 0.09~0.20 64-LQFP-1010 0.08 MAX + 0.07 0.20 - 0.03 ± 0.05 0.10 0.50 BSC ± 0.05 1.40 1.60 MAX NOTE: Dimensions are in millimeters. Figure 18-2. 64-Pin LQFP Package Dimensions (64-LQFP-1010) 18-2...
Page 311: Overview
OVERVIEW The S3F8275X/F8278X/F8274X single-chip CMOS microcontroller is the Flash MCU version of the S3C8275X/C8278X/C8274X microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F8275X/F8278X/F8274X is fully compatible with the S3C8275X/C8278X/C8274X, both in function and in pin configuration.
Page 312: S3F8275X/F8278X/F8274X Pin Assignments (64-Qfp-1420F)
S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SEG14/P4.1 SEG0/P5.7 COM0/P6.0 SEG15/P4.0 COM1/P6.1 SEG16/P3.7 COM2/P6.2 SEG17/P3.6 COM3/P6.3 SEG18/P3.5 VLC0 SEG19/P3.4 S3F8275X SDAT/VLC1 SEG20/P3.3 SCLK/VLC2 SEG21/P3.2 S3F8278X SEG22/P3.1 S3F8274X SEG23/P3.0 SEG24/P2.7 SEG25/P2.6 (64-QFP-1420F) /TEST SEG26/P2.5 SEG27/P2.4 SEG28/P2.3 nRESET/nRESET SEG29/P2.2 SEG30/P2.1 P0.0/INT0 SEG31/P2.0/V BLDREF P0.1/INT1 P1.7/INT7 Figure 19-1.
Page 313: S3F8275X/F8278X/F8274X Pin Assignments (64-Lqfp-1010)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU SEG0/P5.7 SEG17/P3.6 COM0/P6.0 SEG18/P3.5 COM1/P6.1 SEG19/P3.4 COM2/P6.2 SEG20/P3.3 COM3/P6.3 SEG21/P3.2 S3F8275X VLC0 SEG22/P3.1 S3F8278X SDAT/VLC1 SEG23/P3.0 SCLK/VLC2 SEG24/P2.7 S3F8274X SEG25/P2.6 SEG26/P2.5 SEG27/P2.4 (64-LQFP-1010) SEG28/P2.3 /TEST SEG29/P2.2 SEG30/P2.1 SEG31/P2.0/V BLDREF nRESET/nRESET P1.7/INT7 Figure 19-2. S3F8275X/F8278X/F8274X Pin Assignments (64-LQFP-1010)
Page 314: Descriptions Of Pins Used To Read/Write The Flash Rom
Chip initialization 9 / 10 Power supply pin for logic circuit. should be tied to +3.3 V during programming. Table 19-2. Comparison of S3F8275X/F8278X/F8274X and S3C8275X/C8278X/C8274X Features Characteristic S3F8275X/F8278X/F8274X S3C8275X/C8278X/C8274X Program memory 16/8/4-Kbyte Flash ROM 16/8/4-Kbyte mask ROM Operating voltage (V 2.0 V to 3.6 V...
Page 315: Operating Mode Characteristics
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V (TEST) pin of the S3F8275X/F8278X/F8274X, the Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 19-3 below.
Page 316: D.c. Electrical Characteristics
S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 19-4. D.C. Electrical Characteristics ° ° = − 25 C to + 85 C, V = 2.0 V to 3.6 V) Unit Parameter Symbol Conditions − Run mode: 8.0 MHz Supply current = 3.3 V ± 0.3 V Crystal oscillator 4.0 MHz...
Page 317: Operating Voltage Range
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.05 MHz 4.2 MHz 6.25 kHz (main)/8.2 kHz(sub) 400 kHz(main)/32.8 kHz(sub) Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 19-3.
Page 318: Shine
SMDS2+, and OPENice for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
Page 319: Smds Product Configuration (Smds2+)
DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IBM-PC AT or Compatible RS-232C SMDS2+ Target PROM/OTP Writer Unit Application System RAM Break/Display Unit Probe Adapter Trace/Timer Unit TB8275/8/4 Target SAM8 Base Unit Board Power Supply Unit Chip Figure 20-1. SMDS Product Configuration (SMDS2+) 20-2...
Page 320: Tb8275/8/4 Target Board
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS TB8275/8/4 TARGET BOARD The TB8275/8/4 target board is used for the S3C8275X/C8278X/C8274X microcontroller. It is supported with the SMDS2+. TB8275/8/4 IDLE STOP To User_VCC RESET 7411 Y1(sub-clock) J101 J102 160 QFP S3E8270 EVA Chip Device Selection Select Smart Option Source...
Page 321: Power Selection Settings For Tb8275/8/4
DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 20-1. Power Selection Settings for TB8275/8/4 "To User_Vcc" Operating Mode Comments Settings The SMDS2/SMDS2+ TB8275 To User_V supplies V to the target TB8278 Target board (evaluation chip) and TB8274 System the target system. SMDS2/SMDS2+ The SMDS2/SMDS2+...
Page 322: Select Smart Option Source Setting For Tb8275/8/4
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS Table 20-3. Select Smart Option Source Setting for TB8275/8/4 "Smart Option Source" Operating Mode Comments Settings The Smart Option is selected Select Smart by external smart option Option Source Target switch (SW1) TB8275/8/4 Internal External System The Smart Option is selected...
Page 323: Smds2+ Selection (Sam8)
DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 20-5. Device Selection Settings for TB8275/8/4 "Device Selection" Operating Mode Comments Settings Operate with TB8275 Device Selection S3F8278/4 S3F8275 Target TB8275 System Operate with TB8278/4 Device Selection Target S3F8278/4 S3F8275 TB8278/4 System SMDS2+ SELECTION (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows.
Page 324: Pin Connectors (J101, J102) For Tb8275/8/4
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS J101 J102 SEG0/P5.7 P6.0/COM0 INT7/P1.7 SEG31/P2.0/V BLDREF COM1/P6.1 P6.2/COM2 SEG30/P2.1 SEG29/P2.2 COM3/P6.3 VLC0 SEG28/P2.3 SEG27/P2.4 VLC1 VLC2 SEG26/P2.5 SEG25/P2.6 SEG24/P2.7 SEG23/P3.0 SEG22/P3.1 SEG21/P3.2 TEST SEG20/P3.3 SEG19/P3.4 nRESET SEG18/P3.5 SEG17/P3.6 P0.0/INT0 SEG16/P3.7 SEG15/P4.0 INT1/P0.1 P0.2/INT2 SEG14/P4.1 SEG13/P4.2 T1CLK/P0.3 P0.4/TAOUT...

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F8275x F8274x C8278x C8274x F8278x

Samsung S3C8275X User Manual

Chapter 1 Product Overview

Chapter 2 Address Spaces

Chapter 3 Addressing Modes

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