Sony TRINITRON BVM-A14F5M Service Manual page 136
Color video monitor
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Also See for TRINITRON BVM-A14F5M:
- Pocket manual (20 pages) ,
- Product manual (18 pages) ,
- Operation manual (130 pages)
Table of Contents
BC (2/3)
F352
L352
+5V
Q358,364-366
DC/DC CONVERTER
OVER CURRENT
24
DETECT
VCC
9
STBY1
Q363
10
IC404
STBY2
Q360
4.0V
RESET
5
1
Q362
D361
Q367
LED
DRIVE
TP354
IC352
12V
+15V
+12V
REG
TP302
IC351
1.5V
+3.3V
+1.5V
REG
IC167,166
RECEIVE BUFFER
REM [0]-[7]
REM [0]
1
REM [5]
6
1,3,5,9,11,13
2,4,6,8,10,12
REM [1]
2
CN153
REM [6]
7
REM [2]
REMOTE2
3
REM [7]
8
REM [3]
4
9
REM [4]
5
IC310
+3.3V
RESET
D0-D31
1/3,3/3
IC350
A0-A25
1/3,3/3
Q351
29
DD-CONV
1/3
OUT1-U
TP351
WAIT
SW
L350
F351
L353
1/3
RD/WR
28
LL1
+3.3V
1/3
WE0-WE3
Q353
1/3
RD
27
OUT1-D
DD-CONV
SW
1/3
BS
1/3
IRQ4 X
1
INV1
1/3
BREQ
1/3
BACK
1/3
CS2
1/3
Q356
CS5
1/3
17
LED. DIGIT[0]
DD-CONV
TP350
OUT2-U
SW
1/3
LED. DIGIT[1]
L351
L354
F350
18
1/3
LED. WE X
LL2
+1.8V
Q354
1/3
LED. SEG[0]-[7]
19
DD-CONV
OUT2-D
1/3
FLASH1. RY/BY
SW
1/3
FLASH1. WP/ACC
15
INV2
1/3
FLASH2. RY/BY
1/3
FLASH2. WP/ACC
1/3
CS0
1/3
CS2 FRAM X
LAN. A0-A3
1/3
1/3
LAN. AEN
1/3
LAN. RD
1/3
LAN. WR
1/3
LAN. ARDY
1/3
LAN. BE0
1/3
LAN. BE1
1/3
CS2 UART X
1/3
FPGA. CKIO
3/3
JATG. TMS
3/3
JATG. TCK
3/3
FPGA ROM. TDI
IC312
IC311
OPEN
SCHMITT
3/3
JATG. TDO
DRAIN
INVERTER
INVERTER
2
4
2
4
7-14
BC (2/3)
BC (2/3)
IC300
FPGA
BUS INTERFACE
N2,P3,N1,N4,M2,N3,M1,M4,L2,L4
L1,L3,K2,K3,K1,G3,J1,G4,G2,F3,F1
F4,F2,E3,E1,E4,D1,D3,D2,C3,C2,C4
D0
ADIN X[0]
|
D0-D31
D31
ADIN X[7]
B2,D5,A2,C5,B3,C6
B4,C7,A4,C8,B5,D8,B6,D9,A6,C9,B7
ADOUT0
C10,B8,D10,A8,C11,A9,C12,B9,D12
A0
ADOUT7
A0-A25
|
A25
TA A X/D
B15
WAIT
TA R/W X
A15
RD/WR
TA CLK RW
4
B12,A13,B13,B14
WE0-WE3
A11
RD
B10
IRQ[1]-[7]
BS
B1
IRQ4 X
E13
BREQ
XILINX. DOE X[0]
D14
BACK
XILINX. DOE X[1]
C14
CS2
FREE[0]
D13
CS5
FREE[1]
H5
LED. DIGIT[0]
FREE[2]
G5
LED. DIGIT[1]
VMS. ADOE X
G1
LED. WE X
FPGA. RESET
8
E10,E9,E8,E7,D6,E6,E5,F5
LED. SEG[0]-[7]
CS2 VMBUS X
T2
FLASH1. RY/BY
SLOT X[2]
R3
FLASH1. WP/ACC
P4
FLASH2. RY/BY
INIT DONE X
N5
FLASH2. WP/ACC
C13
CS0
P2
CS2 FRAM X
T8,R8,R7,T6
LAN. A0
HS X[0]
LAN. A0 - LAN. A3
|
VS X[0]
LAN. A3
HS X[1]
VS X[1]
T4
LAN. AEN
R5
LAN. RD
R6
POWER
LAN. WR
STAND BY
R10
OVERLOAD
LAN. ARDY
T13
LAN. BE0
R12
LAN. BE1
R1
CS2 UART X
H/W. RST
H/W. RST EN
H16
CLK3
R11,P10,N10,P11
P12,N12,P13,P14
REM X[0]-X[7]
IC301
FPGA ROM
2
H2
DIG[0]-[2]
DATA
DATA
19
3
K4
TMS
DCLK
DCLK
3
13
H3
TCK
nINIT CONF
NCONFIG
11
8
J13
TDI
OE
NSTATUS
1
9
K13
TDO
CONF DONE
nCS
SEG[0]-[7]
J15
TMS
J14
TCK
H14
TDI
H15
TDO
7-14
LG13,G14,H13,K14
L14,L13,M14,M13
|
ADIN X[0]-X[7]
3/3
E15,E16,F15,F16
G15,J16,K16,K15
|
ADOUT0-7
3/3
TA A X/D
N14,N13,G16
3
3/3
TA R/W X
TA CLK RW
L15,M16,M15
N16,N15,R16,P15
7
IRQ[1]-[7]
3/3
F14
3/3
SUB
SUB
R14
3/3
XILINX. DOE X[0]
R13
3/3
XILINX. DOE X[1]
M12
FREE[0]
3/3
M11
3/3
FREE[1]
N11
+5V
3/3
FREE[2]
T15
VMS. ADOE X
3/3
Q382,383
F13
3/3
FPGA. RESET
B16
3/3
CS2 VMBUS X
R15
SLOT X[2]
3/3
IC303
D4
3/3
INIT DONE X
2
4
D7,B11
2
HS X[0]
3/3
VS X[0]
M3,E2
2
HS X[1]
3/3
VS X[1]
POWER
F12,E12,E11,D11
4
STAND BY
3/3
OVERLOAD
TALLY
TALLY
IC313
MULTIVIBRATOR
HARDWARE RESET
R2
4
6
A1
H/W. RESET
Q1
1/3
P5
3
RESET1
CONF DONE X
1/3
IC013
LED DRIVE
+3.3V-3
4
1/3
STATUS1
5
1/3
STATUS0
T9
6
1/3
LED. LAN CNTRL
7
CONF DONE X
IC013
LED DRIVE
H12,K12,L12
3
1-3
IC1011
LED DRIVE
K5,L5,M5,M6
8
1-8
N6,M7,M8,M9
IC302
SCHMITT
INVERTER
2
4
TP352
CN350
1
5V
DC OUT
RY301
CN351
+5V
DELAY
1
5V
15
D011 STATUS1
14
D012 STATUS2
13
D013 LAN CNTRL
12
D014 FPGA CONFIG
D014
7 SEG LED
2,4,5
18-16
3
DIG1-3
1,3,6-11
D.P
18-11
8
a-g
BVM-A14
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