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Emerson Motorola MVME197LE User Manual

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  • Page 1 (217) 352-9330 | Click HERE Find the Emerson / Motorola MVME197LE at our website:...
  • Page 2 MVME197LE Single Board Computer User’s Manual (MVME197LE/D2)
  • Page 3 Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 4 Preface This document provides general information, hardware preparation and installation instructions, operating instructions, and a functional description for the MVME197LE Single Board Computer. This document is intended for anyone who wants to design OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes.
  • Page 5 Data and address sizes are defined as follows: A byte is eight bits, numbered 0 through 7, with bit 0 being the least significant. A two-byte is 16 bits, numbered 0 through 15, with bit 0 being the least significant. For the MVME197series and other RISC modules, this is called a half-word.
  • Page 6 Related Documentation The following publications are applicable to the MVME197LE module and may provide additional helpful information. If not shipped with this product, they may be purchased by contacting your Motorola sales office. Motorola Document Title Publication Number MVME197LE, MVME197DP, and MVME197SP Single MVME197PG Board Computers Programmer’s Reference Guide MVME197BUG 197Bug Debugging Package User’s Manual...
  • Page 7 To further assist your development effort, Motorola has collected user’s manuals for each of the peripheral controllers used on the MVME197 module series and other boards from the suppliers. This bundle includes manuals for the following: 68-1X7DS for use with the MVME197 series of Single Board Computers. NCR 53C710 SCSI Controller Data Manual and Programmer’s Guide Intel i82596 Ethernet Controller User’s Manual Cirrus Logic CD2401 Serial Controller User’s Manual...
  • Page 8 The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1991, and may be used only under license such as the License for Computer Programs (Article 14) contained in Motorola’s Terms and Conditions of Sale, Rev. 1/79. ®...
  • Page 9 SAFETY SUMMARY SAFETY DEPENDS ON YOU The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola Inc. assumes no liability for the customer’s failure to comply with these requirements.

  • Page 10: Table Of Contents

    Contents CHAPTER 1 GENERAL INFORMATION Introduction ......................1-1 General Description ....................1-1 Features........................1-2 Specifications ......................1-3 Cooling Requirements..................1-4 FCC Compliance ....................1-5 Equipment Required....................1-5 Support Information ....................1-6 CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION Introduction ......................2-1 Unpacking Instructions ..................2-1 Hardware Preparation....................2-1 Configuration Switches...................2-3 Configuration Switch S1: General Information........2-3 Configuration Switch S1: General Purpose Functions (S1-1 to S1-8)...................2-4 Configuration Switch S1: System Controller Enable...
  • Page 11 Processor Bus Memory Map ................3-2 Detailed I/O Memory Maps...............3-5 BBRAM, TOD Clock Memory Map ............3-19 VMEbus Memory Map ..................3-20 VMEbus Accesses to the Local Peripheral Bus ........3-20 VMEbus Short I/O Memory Map............3-20 Software Initialization ....................3-21 Multi-MPU Programming Considerations ............3-21 Local Reset Operation ..................3-21 CHAPTER 4 FUNCTIONAL DESCRIPTION...
  • Page 12 List of Figures Figure 2-1. MVME197LE Switches, Connectors, and LED Indicators Location Diagram..............2-2 Figure 4-1. MVME197LE Block Diagram.............4-2 Figure A-1. Middle-of-the-Road EIA-232-D Configuration......A-5 Figure A-2. Minimum EIA-232-D Connection...........A-6...
  • Page 14 List of Tables Table 1-1. MVME197LE Specifications..............1-3 Table 3-1. Processor Bus Memory Map ..............3-3 Table 3-2. Local Devices Memory Map ...............3-4 Table 3-3. BusSwitch Register Memory Map .............3-6 Table 3-4. ECDM CSR Register Memory Map ............3-7 Table 3-5. DCAM (I C) Register Memory Map...........3-8 Table 3-6.

  • Page 16: General Information

    GENERAL INFORMATION Introduction This user’s manual provides general information, preparation for use and installation instructions, operating instructions, and a functional description for the MVME197LE version of the MVME197 series of single board computers. General Description The MVME197LE module is a double-high VMEmodule based on the MC88110 RISC microprocessor.

  • Page 17: Features

    General Information For the MVME197 series, the term Local Bus, as used in other MVME1xx Single Board Computer series, is referred to as the Local Peripheral Bus. The DCAM (DRAM Controller and Address Multiplexer) ASIC provides the address multiplexers and RAS/CAS/WRITE control for the DRAM as well as data control for the ECDM.

  • Page 18: Specifications

    Specifications 128 or 256 kilobytes of BOOT ROM Six 32-bit tick timers for periodic interrupts Watchdog timer Eight software interrupts – SCSI Bus interface with Direct Memory Access (DMA) – Four serial ports with EIA-232-D buffers – Centronics printer port –...

  • Page 19: Cooling Requirements

    Cooling Requirements The Motorola MVME197LE VMEmodule is specified, designed, and tested to operate reliably with an incoming air temperature range from 0° to 55° C (32° to 131° F) with forced air cooling at a velocity typically achievable by using a 100 CFM axial fan.

  • Page 20: Fcc Compliance

    Equipment Required While the exact amount of airflow required for cooling depends on the ambient air temperature and the type, number, and location of boards and other heat sources, adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module. Less airflow is required to cool the module in environments having lower maximum ambients.

  • Page 21: Support Information

    General Information a user interface which accepts commands from the system console terminal. 197Bug can also operate in a System Mode, which includes choices from a service menu. Refer to the MVME197BUG 197Bug Debugging Package User’s Manual for more details. The MVME712 series transition modules provide an interface between the MVME197LE module and peripheral devices.

  • Page 22: Hardware Preparation And Installation

    HARDWARE PREPARATION AND INSTALLATION Introduction This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MVME197LE VMEmodule. The MVME712X transition module hardware preparation is provided in separate manuals, refer to the Related Documentation section found in the preface part of this User’s Manual.
  • Page 23 Hardware Preparation and Installation User’s Manual...
  • Page 24 VMEbus CONNECTOR P1 VMEbus CONNECTOR P2 1A17 2A17 3A17 1E17 2E17 3E17 MEZZANINE CONNECTOR J2 CONFIGURATION SWITCH S6 SERIAL PORT 4 CLOCK SELECT CONFIGURATION SWITCH S1 GENERAL PURPOSE/SCON MODULE CONNECTOR J1 REMOTE RESET/ABORT/LEDS ABORT RESET SWITCH SWITCH MVME197LE Figure 2-1. MVME197LE Switches, Connectors, and LED Indicators Location Diagram...

  • Page 25: Configuration Switches

    Hardware Preparation and Installation Configuration Switches The location of the switches, connectors, and LED indicators on the MVME197LE is illustrated in Figure 2-1. The MVME197LE has been factory tested and is shipped with factory switch settings that are described in the following sections.

  • Page 26: Configuration Switch S1: General Purpose Functions

    Hardware Preparation Configuration Switch S1: General Purpose Functions (S1-1 to S1-8) The eight General Purpose Input lines (GPI0-GPI7) on the MVME197LE may be configured with selectable switch segments S1-1 through S1-8. These switches can be read as a register (at $FFF40088) in the VMEchip2 LCSR. Refer to the VMEchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for the status of lines GPI0 through GPI7.

  • Page 27: Configuration Switch S6: Serial Port 4 Clock Select

    Hardware Preparation and Installation Configuration Switch S6: Serial Port 4 Clock Select (S6-1, S6-2) Serial port 4 can be configured to use clock signals provided by the RTXC4 and TRXC4 signal lines. Switch segments S6-1 and S6-2 on the MVME197LE configures serial port 4 to drive or receive TRXC4 and RTXC4, respectively.

  • Page 28: Mvme197Le Module Installation

    Installation Instructions MVME197LE Module Installation Now that the MVME197LE module is ready for installation, proceed as follows: a. Turn all equipment power OFF and disconnect the power cable from the power source. Inserting or removing modules while power is applied aution could result in damage to module components.

  • Page 29: System Considerations

    Hardware Preparation and Installation are provided in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide). Some cable(s) are not provided with the MVME712X module and therefore, are made or provided by the user. (Motorola recommends using shielded cables for all connections to peripherals to minimize radiation).
  • Page 30 Installation Instructions Multiple MVME197LE modules may be configured into a single VME card cage. In general, hardware multiprocessor features are supported. Other MPUs on the VMEbus can interrupt, disable, communicate with and determine the operational status of the RISC processor(s). One register of the GCSR set includes four bits which function as location monitors to allow one MVME197LE processor to broadcast a signal to other MVME197LE processors, if any.
  • Page 31 Hardware Preparation and Installation 2-10 User’s Manual...

  • Page 32: Operating Instructions

    OPERATING INSTRUCTIONS Introduction This chapter provides the necessary information to use the MVME197LE VMEmodule in a system configuration. This includes controls and indicators, memory maps, and software initialization of the module. Controls and Indicators The MVME197LE Single Board Computer has two push-botton switches (ABORT and RESET) and six LED indicators (FAIL, SCON, RUN, LAN, VME, and SCSI), all located on the front panel of the module.

  • Page 33: Front Panel Indicators (Ds1-Ds6)

    Operating Instructions by a control bit in the LCSR. SYSRESET* remains asserted for at least 200 msec, as required by the VMEbus specification. Similarly, the VMEchip2 provides an input signal and a control bit to initiate a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation.

  • Page 34: Table 3-1. Processor Bus Memory Map

    Memory Maps The memory maps of MVME197LE devices are provided in the following tables. Table 3-1 is the entire map from $00000000 to $FFFFFFFF. Many areas of the map are user-programmable, and suggested uses are shown in the table. This is assuming no address translation is used between the processor and local peripheral bus and between the local peripheral bus and VMEbus.

  • Page 35: Table 3-2. Local Devices Memory Map

    Operating Instructions The following table focuses on the Local Devices portion of the Memory Map. Table 3-2. Local Devices Memory Map Address Range Devices Accessed Port Size Size Notes $FFF00000 - $FFF00FFF BusSwitch D64-D8 $FFF01000 - $FFF01FFF ECDM (DCAM access) $FFF02000 - $FFF02FFF reserved $FFF03000 - $FFF03FFF...

  • Page 36: Detailed I/O Memory Maps

    Memory Maps 3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16, or 32 bits. Reads to the LCSR and GCSR may be 8, 16, or 32 bits.

  • Page 37: Table 3-3. Busswitch Register Memory Map

    Operating Instructions Table 3-3. BusSwitch Register Memory Map BusSwitch Base Address = $FFF00000 Offset CHIPID CHIPREV GCSR IODATA IODIR PSAR1 PEAR1 PSAR2 PEAR2 PSAR3 PEAR3 PSAR4 PEAR4 PTR1 PTSR1 PTR2 PTSR2 PTR3 PTSR3 PTR4 PTSR4 SSAR1 SEAR1 SSAR2 SEAR2 SSAR3 SEAR3 SSAR4 SEAR4...
  • Page 38 Memory Maps MVME197LE/D2...

  • Page 39: Table 3-4. Ecdm Csr Register Memory Map

    Table 3-4. ECDM CSR Register Memory Map Sub-System Memory CSR Base Address = $FFF01000 Offset/Register: ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER 00 / MEMCON0 01 / ECDMID0 02 / MEMCON1 03 / ECDMID1 04 / MEMCON2 05 / ECDMID2 06 / MEMCON3 07 / ECDMID3...

  • Page 40: Table 3-5. Dcam (I 2 C) Register Memory Map

    Memory Maps Table 3-5. DCAM (I C) Register Memory Map DCAM (I C) Base Address = $C0 (default) Offset BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00 00 ID Register 01 01 Version Register 02 02 SL31...
  • Page 41 Operating Instructions 3-10 User’s Manual...

  • Page 42: Table 3-6. Vmechip2 Memory Map

    Table 3-6. VMEchip2 Memory Map (Sheet 1 of 4) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: VMEbus SLAVE ENDING ADDRESS 1 VMEbus SLAVE STARTING ADDRESS 1 VMEbus SLAVE ENDING ADDRESS 2 VMEbus SLAVE STARTING ADDRESS 2 VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 1 VMEbus SLAVE ADDRESS TRANSLATION SELECT 1 VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 2 VMEbus SLAVE ADDRESS TRANSLATION SELECT 2...
  • Page 43 Operating Instructions 3-12 User’s Manual...
  • Page 44 Table 3-6. VMEchip2 Memory Map (Continued) (Sheet 2 of 4) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: ROM0 DMAC TB SPRAM DMAC DMAC DMAC DMAC DMAC DMAC (XX) SNP MODE SPEED ROBN FAIR REQUEST HALT FAIR RELM REQUEST (XX) (XX) MODE LEVEL LEVEL...
  • Page 45 Operating Instructions 3-14 User’s Manual...
  • Page 46 Table 3-6. VMEchip2 Memory Map (Continued) (Sheet 3 of 4) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: IRQ1 DMAC GCSR GCSR GCSR GCSR GCSR GCSR SPARE VME FAIL FAIL EDGE TIM2 TIM1 IACK SIG3 SIG2 SIG1 SIG0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2...
  • Page 47 Operating Instructions 3-16 User’s Manual...
  • Page 48 Table 3-6. VMEchip2 Memory Map (Continued) (Sheet 4 of 4) VMEchip2 GCSR Base Address = $FFF40100 CHIP REVISION CHIP ID SIG3 SIG2 SIG1 SIG0 SCON GENERAL PURPOSE CONTROL AND STATUS REGISTER 0 GENERAL PURPOSE CONTROL AND STATUS REGISTER 1 GENERAL PURPOSE CONTROL AND STATUS REGISTER 2 GENERAL PURPOSE CONTROL AND STATUS REGISTER 3 GENERAL PURPOSE CONTROL AND STATUS REGISTER 4 GENERAL PURPOSE CONTROL AND STATUS REGISTER 5...
  • Page 49 Operating Instructions 3-18 User’s Manual...

  • Page 50: Table 3-7. Pccchip2 Memory Map

    Table 3-7. PCCchip2 Memory Map PCCchip2 LCSR Base Address = $FFF42000 OFFSET: MSTR FAST CHIP ID CHIP REVISION BRAM VECTOR BASE TIC TIMER 1 COMPARE TIC TIMER 1 COUNTER TIC TIMER 2 COMPARE TIC TIMER 2 COUNTER OVERFLOW COUN COUN OVERFLOW COUN COUN...

  • Page 51: Table 3-8. Printer Memory Map

    Operating Instructions Table 3-8. Printer Memory Map Printer ACK Interrupt Control Register $FFF42030 NAME PLTY E/L* ICLR Printer FAULT Interrupt Control Register $FFF42031 NAME PLTY E/L* ICLR Printer SEL Interrupt Control Register $FFF42032 PLTY E/L* ICLR NAME Printer PE Interrupt Control Register $FFF42033 NAME PLTY...

  • Page 52: Table 3-9. Cirrus Logic Cd2401 Serial Port Memory Map

    Memory Maps Table 3-9. Cirrus Logic CD2401 Serial Port Memory Map Base Address Is $FFF45000 Cirrus Logic CD2400 Memory Map Offsets Size Access Global Firmware Revision Code Register (GFRCR) Transmit FIFO Transfer Count (TFTC) Modem End Of Interrupt Register (MEOIR) Transmit End Of Interrupt Register (TEOIR) Receive End Of Interrupt Register...

  • Page 53: Table 3-10. 82596Ca Ethernet Lan Memory Map

    Operating Instructions Table 3-10. 82596CA Ethernet LAN Memory Map 82596CA Ethernet LAN Directly Accessible Registers Data Bits Address $FFF46000 Upper Command Word Lower Command Word $FFF46004 MPU Channel Attention (CA) 1. Refer to the MPU Port and MPU Channel Attention otes registers in the PCCchip2 chapter of the MVME197LE, MVME197DP,...

  • Page 54: Table 3-11. 53C710 Scsi Memory Map

    Memory Maps Table 3-11. 53C710 SCSI Memory Map 53C710 Register Address Map Base Address is $FFF47000 SCRIPTs Mode Endian and Little Mode Endian Mode SIEN SDID SCNTL1 SCNTL0 SOCL SODL SXFER SCID SBCL SBDL SIDL SFBR SSTAT2 SSTAT1 SSTAT0 DSTAT CTEST3 CTEST2 CTEST1...

  • Page 55: Table 3-13. Bbram Configuration Area Memory Map

    Operating Instructions Table 3-13. BBRAM Configuration Area Memory Map Address Range Description Size (Bytes) $FFFC1EF8 - $FFFC1EFB Version $FFFC1EFC - $FFFC1F07 Serial Number $FFFC1F08 $FFFC1F17 Board ID $FFFC1F18 $FFFC1F27 $FFFC1F28 $FFFC1F2B Speed $FFFC1F2C - $FFFC1F33 Ethernet Address $FFFC1F34 $FFFC1FF6 Reserved $FFFC1FF7 Checksum Table 3-14.

  • Page 56: Bbram, Tod Clock Memory Map

    Memory Maps BBRAM, TOD Clock Memory Map The MK48T08 BBRAM (also called Non-Volatile RAM or NVRAM) is divided into six areas as shown in Table 3-12. The first five areas are defined by software, while the sixth area, the time-of-day (TOD) clock, is defined by the chip hardware.

  • Page 57: Vmebus Memory Map

    Operating Instructions Sixteen bytes are reserved for the printed wiring assembly (PWA) number assigned to this board in ASCII format. This includes the 01-W prefix. This is for the main logic board if more than one board is required for a set. Additional boards in a set are defined by a structure for that set.

  • Page 58: Software Initialization

    Software Initialization Software Initialization Most functions that have been done with switches or jumpers on other modules are done by setting control registers on the MVME197LE. At power- up or reset, the FLASH memory that contains the 197Bug debugging package sets up the default values of many of these registers.
  • Page 59 Operating Instructions Any VMEbus access to the MVME197LE while it is in the reset state is ignored. If a global bus timer is enabled, a bus error is generated. 3-28 User’s Manual...

  • Page 60: Functional Description

    FUNCTIONAL DESCRIPTION Introduction This chapter provides a block diagram level description of the MVME197LE Single Board Computer. The functional description provides an overview of the module, followed by a detailed description of several blocks of the module. The block diagram for the MVME197LE is illustrated in Figure 4-1. Descriptions of the other blocks of the MVME197LE module, including programmable registers in the ASICs and peripheral chips, are given in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers...
  • Page 61 Functional Description User’s Manual...
  • Page 62 MC88110 MUX Address Address Data RAS, CAS DCAM Address Bus Mezzanine Memory Array PROCESSOR Port 32/64 MB Data ECDM (X4) Data Bus BusSwitch C EEPROM CBus Address Data LOCAL PERIPHERAL Address Bus Data Bus NVRAM/RTC BOOT Flash PCCchip2 82596CA Memory VMEbus SCSI -II 4 Serial Ports...

  • Page 63: Boot Rom

    Functional Description BOOT ROM Currently a socket (socket will be removed from module in later board revisions) for a 32-pin PLCC/CLCC ROM/EPROM referred to as BOOT ROM or DROM (Download ROM) is provided. It is organized as a 128K x 8 device, but as viewed from the processor it looks like a 16K x 64 memory.

  • Page 64: Vmebus Interface

    MVME197LE Functional Description format. Corrections for 28-, 29-, (leap year) and 30-day months are automatically made. No interrupts are generated by the clock. The MK48T08 is an 8-bit device; however the interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the MK48T08. Refer to the PCCchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide and to the MK48T08 data sheet for detailed programming information.

  • Page 65: Printer Interface

    Functional Description All four serial ports use EIA-232-D drivers and receivers located on the main board, and all the signal lines are routed to the I/O connector. The configuration headers are located on the MVME712X transition board. An external I/O transition board such as the MVME712X should be used to convert the I/O connector pinout to industry-standard connectors.

  • Page 66: Scsi Interface

    MVME197LE Functional Description the BBRAM, TOD Clock memory map description in the Operating Instructions chapter of this manual. The MVME197LE debugger has the capability to retrieve or set the Ethernet address. If the data in the BBRAM is lost, the user should use the number on the VMEbus P2 connector label to restore it.

  • Page 67: Watchdog Timer

    Functional Description Refer to the VMEchip2, PCCchip2, and BusSwitch chapters in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information. Watchdog Timer A watchdog timer function is provided in the VMEchip2. When the watchdog timer is enabled, it must be reset by software within the programmed time or it times out.
  • Page 68 MVME197LE Functional Description other external sources (PALINT and IRQ). The BusSwitch may also generate the non-maskable interrupt (NMI) signal to the MPU from the ABORT push- button switch. Refer to the BusSwitch, PCCchip2, and VMEchip2 chapters in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for more detailed information.
  • Page 69 Functional Description 4-10 User’s Manual...
  • Page 70 EIA-232-D INTERCONNECTIONS The EIA-232-D Standard is the most widely used interface between terminals and computers or modems, and yet it is not fully understood. This is because all the lines are not clearly defined, and many users do not see the need to conform for their applications.
  • Page 71 EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Signal Signal Name and Description Number Mnemonic Not used. TRANSMIT DATA - data to be transmitted is furnished on this line to the modem from the terminal. RECEIVE DATA - data which is demodulated from the receive line is presented to the terminal by the modem.
  • Page 72 EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections (Continued) Signal Signal Name and Description Number Mnemonic RING INDICATOR - RI is sent by the modem to the terminal. This line indicates to the terminal that an incoming call is present. The terminal causes the modem to answer the phone by carrying DTR true while RI is active.
  • Page 73 EIA-232-D Interconnections be provided by a pull-up resistor or gate as described before (see Figure A-1). Many modems expect a DTR high signal and issue a DSR. These signals are used by software to help prompt the operator about possible causes of trouble. The DTR signal is used sometimes to disconnect the phone circuit in preparation for another automatic call.

  • Page 74: Table A-1. Eia-232-D Interconnections

    EIA-232-D Interconnections 6850 39kΩ -12V CONNECTOR 470Ω LS08 +12V TERMINAL 470Ω OPTIONAL HARDWARE 470Ω TRANSPARENT SIG GND MODE CHASSIS GND LS08 LOGIC SIG GND 470Ω +12V 6850 CONNECTOR 39kΩ -12V MODEM 470Ω HOST +12V SYSTEM 39kΩ -12V 470Ω +12V 39kΩ -12V MODULE Figure A-1.
  • Page 75 EIA-232-D Interconnections Another subject that needs to be considered is the use of ground pins. There are two pins labeled GND. Pin 7 is the SIGNAL GROUND and must be connected to the distant device to complete the circuit. Pin 1 is the CHASSIS GROUND, but it must be used with care.
  • Page 76 Index When using this index, keep in mind that a page number indicates only where referenced material begins. It may extend to the page or pages following the page referenced. Numerics DCAM (I2C) Register Memory Map 3-8 DCAM ASIC 1-2 197Bug 2-3 Detailed I/O Memory Maps 3-5 53C710 SCSI Memory Map 3-17...
  • Page 77 Index PCCchip2 3-13 printer 3-14 I/O Interfaces 4-4 Processor Bus 3-3 Installation Instructions 2-5 SCSI 3-17 installation, MVME197LE 2-6 VMEchip2 3-9 interfaces mezzanine connector 2-5 ethernet 4-5 MK48T08 BBRAM Memory 3-19 I/O 4-4 MK48T08 BBRAM, TOD Clock Memory printer 4-5 Map 3-17 SCSI 4-6 module expansion 2-5...
  • Page 78 processor bus (MC88110 bus) 1-1 Processor Bus Memory Map 3-2, 3-3 Unpacking Instructions 2-1 Processor Bus Timeout 4-7 Programmable Tick Timers 4-6 VMEbus Interface 4-4 VMEchip2 ASIC 1-2 Relative humidity 1-3 VMEchip2 Memory Map 3-9 RESET switch (S3) 3-1 VMEsystem 3000 chassis 1-4 SCSI Interface 4-6 Watchdog Timer 4-7 SCSI Termination 4-6...
  • Page 79 Index IN-4 User’s Manual...

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