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Epson S1C17624 Technical Manual

Cmos 16-bit single chip microcontroller
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CMOS 16-BiT SinGle ChiP MiCROCOnTROlleR
S1C17624/604/622/602/621
Technical Manual
Rev. 1.3
Table of Contents
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Summary of Contents for Epson S1C17624

  • Page 1 CMOS 16-BiT SinGle ChiP MiCROCOnTROlleR S1C17624/604/622/602/621 Technical Manual Rev. 1.3...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability...
  • Page 3 Configuration of product number Configuration of product number Devices 17xxx 00E1 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions...
  • Page 4 1 Overview ........................1-1 1.1 Features ...........................1-1 1.2 Block Diagram ........................1-3 1.3 Pins/Pads .........................1-4 1.3.1 S1C17624 Pin Configuration Diagram ...............1-4 1.3.2 S1C17604 Pin Configuration Diagram ...............1-7 1.3.3 S1C17622 Pin Configuration Diagram ..............1-10 1.3.4 S1C17602/621 Pin Configuration Diagram ............1-13 1.3.5 Pin Descriptions ....................1-17 2 CPu ..........................2-1...
  • Page 5 8.5 Details of Control Registers .....................8-9 RTC Clock Control Register (RTC_CC) ..................8-9 RTC Interrupt Status Register (RTC_INTSTAT) ............... 8-10 RTC Interrupt Mode Register (RTC_INTMODE) ..............8-10 RTC Control 0 Register (RTC_CNTL0) ..................8-11 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 6 10.5 Timer Reset ........................10-3 10.6 Timer RUN/STOP Control .....................10-3 10.7 T8F Output Signals .......................10-4 10.8 Fine Mode ........................10-4 10.9 T8F Interrupts ........................10-5 10.10 Control Register Details ....................10-6 T8F Ch.x Count Clock Select Registers (T8F_CLKx) .............. 10-6 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 7 13.4 T16A2 Operating Modes ....................13-4 13.4.1 Comparator Mode and Capture Mode ............13-4 13.4.2 Repeat Mode and One-Shot Mode ..............13-5 13.4.3 Normal Channel Mode and Multi-Comparator/Capture Mode ......13-6 13.4.4 Normal Clock Mode and Half Clock Mode ............13-7 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 8 Clock Timer Interrupt Flag Register (CT_IFLG) ................ 15-4 16 Stopwatch Timer (SWT) .....................16-1 16.1 SWT Module Overview ....................16-1 16.2 Operation Clock......................16-1 16.3 BCD Counters .......................16-1 16.4 Timer Reset ........................16-2 16.5 Timer RUN/STOP Control .....................16-2 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 9 SPI Ch.x Receive Data Register (SPI_RXDx) ................19-7 SPI Ch.x Control Register (SPI_CTLx)..................19-7 20 i C Master (i2CM) .......................20-1 20.1 I2CM Module Overview ....................20-1 20.2 I2CM Input/Output Pins ....................20-1 20.3 Synchronization Clock ....................20-2 20.4 Settings Before Data Transfer ..................20-2 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 10 23.4 Drive Duty Control ......................23-3 23.4.1 Drive Duty Switching ..................23-3 23.4.2 Drive Waveform ....................23-4 23.5 Display Memory ......................23-9 23.6 Display Control ......................23-13 23.6.1 Display On/Off ....................23-13 23.6.2 LCD Contrast Adjustment ................23-13 23.6.3 Inverted Display .....................23-13 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 11 25.8 Control Register Details ....................25-8 RFC Clock Control Registers (OSC_RFC) ................25-9 RFC Control Register (RFC_CTL).................... 25-9 RFC Oscillation Trigger Register (RFC_TRG) ................. 25-10 RFC Measurement Counter Low and High Registers (RFC_MCL, RFC_MCH) ......25-11 Seiko epson Corporation viii S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 12 29.6 Input/Output Pin Characteristics ...................29-6 29.7 SPI Characteristics ......................29-8 29.8 I C Characteristics ......................29-8 29.9 LCD Driver Characteristics ....................29-9 29.10 A/D Converter Characteristics ..................29-11 29.11 R/F Converter Characteristics ..................29-12 29.12 SVD Circuit Characteristics ..................29-14 29.13 Flash Memory Characteristics..................29-15 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 13: Revision History

    0x5380–0x5386 A/D Converter ............AP-A-24 0x5067, 0x53a0–0x53ae R/F Converter ............AP-A-25 0x5068, 0x5400–0x540c 16-bit PWM Timer (T16A2) Ch.0 (S1C17624/604) ..AP-A-26 0x5069, 0x5420–0x542c 16-bit PWM Timer (T16A2) Ch.1 (S1C17624/604) ..AP-A-28 0xffff84–0xffffd0 S1C17 Core I/O ............AP-A-29 appendix B Power Saving ..................aP-B-1 B.1 Clock Control Power Saving..................
  • Page 14 It allows 8.2 MHz high-speed operation at a minimum of 1.8 V operating voltage, and executes a basic instruction in one clock cycle with 16-bit RISC processing. The S1C17624/604/622/602/621 also includes a coprocessor sup- porting multiplication, division, and MAC (multiply and accumulation) operations.
  • Page 15 TQFP15-128pin (body size: 14 mm × 14 mm, lead pitch: 0.4 mm) Size/pitch TQFP14-100pin (body size: 12 mm × 12 mm, lead pitch: 0.4 mm) (body size: 7 mm × 7 mm, ball pitch: 0.5 mm) VFBGA7H-144 Die form (pad pitch: 100 µm) Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 16 Figure 1. 2.1 Block Diagram *1: The models have a different memory size, LCD outputs and I/O port configurations. *2: The real-time clock (RTC) and 16-bit PWM timer (T16A2) are available only in the S1C17624 and S1C17604. Memory/function S1C17624 S1C17604...
  • Page 17 SCL1/SCL0/TOUTA6/CAPA6/P33 SeG48 SDA1/SDA0/TOUTB6/CAPB6/P34 SeG47 FOUT1/#BFR/P35 SeG46 SeG45 TOUT3/RFCLKO/(eXCl5)P36 TOUTN3/LFRO/TOUT4/(eXCl6)P37 SeG44 FOUTH/P40 SeG43 P41/DSiO SeG42 SeG41 P42/DST2 P43/DClK SeG40 SeG0 SeG39 SeG1 SeG38 SeG2 SeG37 SeG3 SeG36 Figure 1. 3.1.1 S1C17624 Pin Configuration Diagram (TQFP15-128pin) Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 18 CJ624D*** SeG2 SeG36 SeG3 4.200 mm Figure 1. 3.1.2 S1C17624 Pad Configuration Diagram Chip size X = 4.200 mm, Y = 4.256 mm Pad opening No. 1 to 32, 66 to 97: X = 87 µm, Y = 85 µm No.
  • Page 19 1 OVeRVieW Table 1. 3.1.1 S1C17624 Pad Coordinates name X (mm) Y (mm) name X (mm) Y (mm) SeG4 -1.550 -2.027 66 V 1.650 2.027 SeG5 -1.450 -2.027 67 OSC4 1.550 2.027 SeG6 68 OSC3 -1.350 -2.027 1.450 2.027 SeG7 69 V -1.250...
  • Page 20 SIN1/REF1/P30 SeG38/COM5 SeG37/COM6 SCL0/SENA1/TOUTA5/CAPA5/P31 SDA0/SENB1/TOUTB5/CAPB5/P32 SeG36/COM7 SeG35 SCL1/SCL0/TOUTA6/CAPA6/P33 SDA1/SDA0/TOUTB6/CAPB6/P34 SeG34 FOUT1/#BFR/P35 SeG33 SeG32 TOUT3/RFCLKO/(eXCl5)P36 TOUTN3/LFRO/TOUT4/(eXCl6)P37 SeG31 SeG30 FOUTH/P40 P41/DSiO SeG29 P42/DST2 SeG28 SeG27 P43/DClK SeG0 SeG26 Figure 1. 3.2.1 S1C17604 Pin Configuration Diagram (TQFP14-100pin) Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 21 No. 33 to 65, 98 to 130: X = 85 µm, Y = 87 µm Chip thickness 400 µm * The S1C17604 chip has the same pad configuration and coordinates as those of the S1C17624. However, the P44–P47, P50–P56, and SEG40–SEG55 pads do not exist in the S1C17604 chip.
  • Page 22 -1.999 -1.230 62 V 1.999 1.370 127 N.C. -1.999 -1.330 63 V 1.999 1.470 128 N.C. -1.999 -1.430 64 V 1.999 1.570 129 N.C. -1.999 -1.530 65 V 1.999 1.680 130 SeG0 -1.999 -1.630 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 23 Figure 1. 3.3.1 S1C17622 Pin Configuration Diagram (TQFP15-128pin) * The S1C17622 (TQFP15-128pin) has the same pin configuration as that of the S1C17624 (TQFP15-128pin). However, 16-bit PWM timer (T16A2) input/output signals (EXCL5, TOUTA5/CAPA5, TOUTB5/CAPB5, EXCL6, TOUTA6/CAPA6, and TOUTB6/CAPB6) are not assigned to the S1C17622 pins.
  • Page 24 No. 33 to 65, 98 to 130: X = 85 µm, Y = 87 µm Chip thickness 400 µm * The S1C17622 chip has the same pad configuration and coordinates as those of the S1C17624. However, 16-bit PWM timer (T16A2) input/output signals (EXCL5, TOUTA5/CAPA5, TOUTB5/CAPB5, EXCL6, TOUTA6/CAPA6, and TOUTB6/CAPB6) are not assigned to the S1C17622 pads.
  • Page 25 -1.230 62 V 127 SeG0 1.999 1.370 -1.999 -1.330 63 V 128 SeG1 1.999 1.470 -1.999 -1.430 64 V 129 SeG2 1.999 1.570 -1.999 -1.530 65 V 1.999 1.680 130 SeG3 -1.999 -1.630 Seiko epson Corporation 1-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 26 * The S1C17602/621 (TQFP14-100pin) has the same pin configuration as that of the S1C17604 (TQFP14-100pin). However, 16-bit PWM timer (T16A2) input/output signals (EXCL5, TOUTA5/CAPA5, TOUTB5/CAPB5, EXCL6, TOUTA6/CAPA6, and TOUTB6/CAPB6) are not assigned to the S1C17602/621 pins. Seiko epson Corporation 1-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 27 SeG24 SeG27 SeG30 SeG34 COM7 COM4 COM1 OSC3 OSC4 SEG36 SEG39 N.C. SeG26 SeG28 SeG31 SeG33 SeG35 COM5 COM2 SEG38 N.C. N.C. N.C. Figure 1. 3.4.2 S1C17602/621 Pin Configuration Diagram (VFBGA7H-144, Top View) Seiko epson Corporation 1-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 28 No. 1 to 29, 60 to 88: X = 87 µm, Y = 85 µm No. 30 to 59, 89 to 118: X = 85 µm, Y = 87 µm Chip thickness 400 µm Seiko epson Corporation 1-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 29 -1.030 56 V 115 DClK/P43 1.849 1.170 -1.849 -1.130 57 V 1.849 1.270 116 N.C. -1.849 -1.230 58 V 1.849 1.370 117 SeG0 -1.849 -1.330 59 V 1.849 1.480 118 N.C. -1.849 -1.430 Seiko epson Corporation 1-16 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 30 R/F converter Ch.0 sensor B oscillation control pin I/O I (Pull-up) I/O port pin SENA0 I/O R/F converter Ch.0 sensor A oscillation control pin I/O I (Pull-up) I/O port pin REF0 I/O R/F converter Ch.0 reference oscillation control pin Seiko epson Corporation 1-17 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 31 – TOUT4 O T8OSC1 PWM signal non-inverted output pin I/O I (Pull-up) I/O port pin – – – (eXCl6) T16A2 Ch.1 external clock input pin – SCLK1 UART Ch.1 external clock input pin Seiko epson Corporation 1-18 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 32 DCLK pin initial status The DCLK pin of the S1C17624/604/622 goes high after the #RESET pin is set to 1 (after reset status is canceled). The DCLK pin must be set to low with the pull-down resistor in the IC while the #RESET pin is set to 0 (reset status), therefore do not connect any circuit such as a pull-up resistor that may set the pin to high.
  • Page 33 2 CPu The S1C17624/604/622/602/621 contains the S1C17 Core as its core processor. The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor. It features low power consumption, high-speed operation, large address space, main instructions executable in one clock cycle, and a small sized design. The S1C17 Core is suitable for embedded applications such as controllers and sequencers for which an eight-bit CPU is commonly used.
  • Page 34 -[%rb],%rs [%sp+imm7],%rs General-purpose register (16 bits) → stack General-purpose register (16 bits) → memory [imm7],%rs General-purpose register (24 bits) → general-purpose register ld.a %rd,%rs Immediate → general-purpose register (zero-extended) %rd,imm7 Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 35 16-bit comparison with carry between general-purpose registers cmc/c Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). cmc/nc %rd,sign7 16-bit comparison of general-purpose register and immediate with carry Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 36 Absolute subroutine call Delayed call possible calla.d Return from subroutine ret.d Delayed return possible Software interrupt imm5 intl imm5,imm3 Software interrupt with interrupt level setting reti Return from interrupt handling Delayed call possible reti.d Debug interrupt Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 37 Signed immediate (numerals indicating bit length) Reading PSR The S1C17624/604/622/602/621 includes the MISC_PSR register for reading the contents of the PSR (Processor Status Register) in the S1C17 Core. Reading the contents of this register makes it possible to check the contents of the PSR using the application software.
  • Page 38 The value of the PSR N (negative) flag can be read out. 1 (R): 0 (R): 0 (default) Processor information The S1C17624/604/622/602/621 has the IDIR register shown below that allows the application software to identify CPU core type. Processor iD Register (iDiR) Register name address name...
  • Page 39 3 MeMORY MaP Memory Map Figures 3.1, 3.2, and 3.3 show the S1C17624/604, S1C17622/602, and S1C17621 memory maps, respectively. Peripheral function (Device size) reserved – 0xff ffff 0x5440–0x5fff Reserved for core I/O area 16-bit PWM timer (T16A2) Ch.0–1 (16 bits) 0x5400–0x543f...
  • Page 40 (8 bits) Internal RAM area 0x4100–0x413f reserved – (2K bytes, 1 cycle) 0x4040–0x40ff MISC registers (MISC) (8 bits) (Device size: 32 bits) 0x4020–0x403f reserved – 0x4000–0x401f 0x00 0000 Figure 3. 3 S1C17621 Memory Map Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 41 • When the CPU executes the instruction stored in the Flash area and accesses data in the Flash area or display RAM area • When the CPU executes the instruction stored in the internal RAM area and accesses data in the internal RAM area Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 42 3.2.1 embedded Flash Memory The S1C17624/604 contains a 128K-byte Flash memory (4K bytes × 32 sectors), the S1C17622/602 contains a 64K-byte Flash memory (4K bytes × 16 sectors), and the S1C17621 contains a 32K-byte Flash memory (4K bytes × 8 sectors) for storing application programs and data.
  • Page 43 • Be sure not to locate the area with data-read protection into the .data and .rodata sections. • Be sure to set D0 of address 0x27ffe (S1C17624/604/622) or 0x17ffe (S1C17602/621) to 1. If it is set to 0, the program cannot be booted.
  • Page 44 The S1C17624/604 enables the RAM size used to apply restrictions to 8KB, 4KB, or 2KB. The S1C17622 enables the RAM size used to apply restrictions to 4KB or 2KB. For example, when using the S1C17624/604/622 to devel- op an application for a built-in ROM model, you can set the RAM size to match that of the target model, preventing creating programs that seek to access areas outside the RAM areas of the target product.
  • Page 45 Display RaM area The display RAM for the on-chip LCD driver is located in the 56-byte area (S1C17624/622) or 40-byte area (S1C17604/602/621) beginning with address 0x53c0 in the internal peripheral area. The display RAM is accessed in one cycle as a 16-bit device. It can be used as a general-purpose RAM when it is not used for display. See the “Display Memory”...
  • Page 46 • R/F converter (RFC, 16-bit device) • Display RAM (SEGRAM, 16-bit device) • 16-bit PWM timers (T16A2, 16-bit device) Available only in the S1C17624/604 S1C17 Core i/O area The 1K-byte area from address 0xfffc00 to address 0xffffff is the I/O area for the CPU core in which the I/O regis- ters listed in the table below are located.
  • Page 47 Power Supply Circuit The S1C17624/604/622/602/621 has a built-in power supply circuit shown in Figure 4.3.1 to generate all the power voltages required for the internal circuits. The power supply module consists of two circuits.
  • Page 48 The LCD system voltage regulator generates the 1/3-bias LCD drive voltages V , and V . In the S1C17624/604/622/602/621, the LCD drive voltage is supplied to the built-in LCD driver that drives the LCD panel connected to the SEG and COM pins. The reference voltage (V or V...
  • Page 49 (8 bits) hVlD heavy load protection mode 1 On 0 Off (VD1_CTl) D4–1 – reserved – – – 0 when being read. VD1MD Flash erase/programming mode 1 Flash (2.5 V) 0 Norm.(1.8 V) D[7:6] Reserved Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 50 Set VCSEL to 0 when V is less than 2.5 V. note: The V to V voltages cannot be obtained correctly if VCSEL is set to 1 when V is less than 2.5 V. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 51 By setting the #RESET pin to low level, the S1C17624/604/622/602/621 enters initial reset state. In order to initial- ize the S1C17624/604/622/602/621 for sure, the #RESET pin must be held at low for more than the prescribed time (see “Input/Output Pin Characteristics” in the “Electrical Characteristics” chapter) after the power supply voltage is supplied.
  • Page 52 Resetting by the Watchdog Timer The S1C17624/604/622/602/621 has a built-in watchdog timer to detect runaway of the CPU. The watchdog timer overflows if it is not reset with software (due to CPU runaway) in four-second cycles. The overflow signal can gen- erate either NMI or reset.
  • Page 53 1. Address 0x5140 = 0x01 (in 8-bit access) 2. Address 0x5141 = 0x06 (in 8-bit access) • After the S1C17624/604 power is turned on, clear the RTC interrupt flag and then disable RTC interrupts as shown below before executing the interrupt enable (ei) instruction.
  • Page 54 The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be read by the S1C17 Core to execute the handler when an interrupt occurs. Table 6.2.1 shows the vector table of the S1C17624/604/622/602/621. Table 6.
  • Page 55 The two modules cannot be set to different interrupt level, as they use the same interrupt vector. Vector table base address The S1C17624/604/622/602/621 allows the base (starting) address of the vector table to be set using the MISC_ TTBRL and MISC_TTBRH registers. “TTBR” described in Table 6.2.1 means the value set to these registers.
  • Page 56 The previously occurring interrupt is held. The held interrupt is canceled and no interrupt is generated if the interrupt flag in the peripheral module is reset with software. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 57 C master (I2CM) interrupt ILV15[2:0] (D[10:8]/ITC_LV7 register) 0x4314 IR remote controller (REMC) interrupt ILV16[2:0] (D[2:0]/ITC_LV8 register) 0x4316 16-bit PWM timer (T16A2) Ch.1 interrupt (S1C17624/604) ILV17[2:0] (D[10:8]/ITC_LV8 register) 0x4316 A/D converter (ADC10) interrupt ILV18[2:0] (D[2:0]/ITC_LV9 register) 0x4318 R/F converter (RFC) interrupt...
  • Page 58 1. Address 0x5140 = 0x01 (in 8-bit access) 2. Address 0x5141 = 0x06 (in 8-bit access) • After the S1C17624/604 power is turned on, clear the RTC interrupt flag and then disable RTC interrupts as shown below before executing the interrupt enable (ei) instruction.
  • Page 59 SPI Ch.0 interrupt ILV15[2:0] (D[10:8]) C master (I2CM) interrupt ITC_LV8(0x4316) ILV16[2:0] (D[2:0]) IR remote controller (REMC) interrupt ILV17[2:0] (D[10:8]) 16-bit PWM timer (T16A2) Ch.1 interrupt (S1C17624/604) ITC_LV9(0x4318) ILV18[2:0] (D[2:0]) A/D converter (ADC10) interrupt ILV19[2:0] (D[10:8]) R/F converter (RFC) interrupt Seiko epson Corporation...
  • Page 60 Divider CT, SWT, WDT 256 Hz HSCLK FOUTH output circuit LCD, SVD, RFC, T8OSC1, T16A2* * S1C17624/604 only Noise filter To internal circuits RESET Noise filter To S1C17 Core Figure 7. 1.1 CLG Module Configuration To reduce current consumption, control the clock in conjunction with processing and use HALT and SLEEP modes.
  • Page 61 IOSC oscillation—e.g., when the IOSC oscillator is turned on with soft- ware. Figure 7.3.1.2 shows the relationship between the oscillation start time and the oscillation stabilization wait time. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 62 A crystal resonator (X’tal3) or a ceramic resonator (Ceramic) and a feedback resistor (R ) should be connected between the OSC3 and OSC4 pins. Additionally, two capacitors (C and C ) should be connected between the OSC3/OSC4 pins and V Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 63 It can be used as the system clock instead of the IOSC or OSC3 clock to reduce power consumption when no high- speed processing is required. The S1C17624/604 also uses OSC1 as the clock source for the RTC. Figures 7.3.3.1 and 7.3.3.2 show the OSC1 oscillator configurations.
  • Page 64 When RTCCE = 0, the OSC1 stops in SLEEP mode regardless of how OSC1EN is set. After an initial reset, OSC1EN and RTCCE are both set to 0, and the OSC1 oscillator circuit is halted. Table 7. 3.3.1 OSC1 Oscillator Operating Status (S1C17624/604, in normal operation) Clock supply to OSC1en...
  • Page 65 4.1 System Clock Selector The S1C17624/604/622/602/621 has three system clock sources (IOSC, OSC3, and OSC1) and it start operating with the IOSC clock after an initial reset. The system clock can be switched to the OSC3 clock when a high-speed clock is required for the processing, or to the OSC1 clock for power saving.
  • Page 66 Clearing SLEEP mode with an external interrupt restarts the system clock supply and the CCLK supply. Peripheral Module Clock (PClK) Control The CLG module also controls the clock supply to peripheral modules. The system clock is used unmodified for the peripheral module clock (PCLK). Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 67 The oscillator circuit used as the clock source cannot (S1C17624/604) (divided IOSC/OSC3/OSC1 be disabled (see the “16-bit PWM Timers (T16A2)” clock) chapter). The PCLK supply can be disabled. * The interrupt controller (ITC) needs PCLK only when the register is set. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 68 FOUT1 clock from the FOUT1 pin. Setting it to 0 disables output. FOUT1E FOUT1 output Figure 7. 7.3 FOUT1 Output note: Since the FOUTH/FOUT1 signal is not synchronized with FOUTHE/FOUT1E writing, switching output on or off will generate certain hazards. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 69 Filters noise when NMIFE/OSC_NFEN register = 1; bypassed when NMIFE = 0 notes: • The RESET input noise filter should normally be enabled. • The S1C17624/604/622/602/621 has no external NMI input pin, but the watchdog timer NMI request signal passes through the filter.
  • Page 70 OSC3 enable 1 Enable 0 Disable D[7:6] iOSCWT[1:0]: iOSC Wait Cycle Select Bits An oscillation stabilization wait time is set to prevent malfunctions due to unstable clock operations at the start of IOSC oscillation. Seiko epson Corporation 7-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 71 Enables or disables IOSC oscillator operations. 1 (R/W): Enabled (on) (default) 0 (R/W): Disabled (off) note: The IOSC oscillator cannot be stopped if the IOSC clock is being used as the system clock. Seiko epson Corporation 7-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 72 Enables or disables the NMI input noise filter. 1 (R/W): Enabled (noise filtering) 0 (R/W): Disabled (bypass) (default) note: The S1C17624/604/622/602/621 has no external NMI input pin, but the watchdog timer NMI request signal passes through the filter. FOuT Control Register (OSC_FOuT)
  • Page 73 • 16-bit PWM timer (T16E) • I/O port (P) • MISC register (MISC) • Power generator (VD1) • Supply voltage detector (SVD) • IR remote controller (REMC) • A/D converter (ADC10) • Interrupt controller (ITC) Seiko epson Corporation 7-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 74 Selects the gear ratio for reducing system clock speed and sets the CCLK clock speed for operating the S1C17 Core. To reduce current consumption, operate the S1C17 Core using the slowest possible clock speed. Table 7. 9.7 CCLK Gear Ratio Selection CClKGR[1:0] Gear ratio (Default: 0x0) Seiko epson Corporation 7-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 75 The RTC is available only in the S1C17624/604. RTC Module Overview The S1C17624/604 incorporates a real-time clock (RTC) with a perpetual calendar, and an OSC1 oscillator circuit to generate the operating clock for the RTC. The RTC and OSC1 oscillator circuit (CLG) operate in SLEEP mode. Moreover, the RTC can periodically generate interrupt requests to the CPU.
  • Page 76 The number of days in each month and leap years are taken into account, so that when months change the counter is reset to 0 along with the 1-day counter, and outputs a carry over of 1 to the 1-month counter. The count data is read out and written using RTCDH[1:0]/RTC_DAY register. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 77 2399. Years (0 to 99) without a remainder when divided by 4 are considered leap years. When the 1-year and 10-year counters both are 0, a common year is assumed. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 78 Write 1 to RTCCE/RTC_CC register to start supplying the OSC1 clock from the CLG to the RTC. 9. Starting the divider Write 0 to RTCSTP/RTC_CNTL0 register to run the divider in the RTC module. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 79 The divider bits above are all cleared 0. The interrupt request signal becomes inactive while RTCRST is set to 1 and is enabled to be output again after RTCRST is set to 0 (except when RTCCE = 0). Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 80 0 but it does not change the minutes. This function may be used to round up seconds to minutes when reset- ting seconds in an application. This function can be executed by writing 1 to RTCADJ/RTC_CNTL0 register. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 81 Register read RTCRDHLD ← 0 Figure 8. 3.7.1 Procedure for Reading Counters note: At least three system clock cycles are required before the counter data can be read after data is written to the counter. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 82 After power-on, an RTC interrupt request is masked (not output) regardless of the RTCIEN and RTCIRQ settings until the clock supply to the RTC is enabled using RTCCE/RTC_CC register. However, be sure to set RTCIEN to 0 (interrupt disabled) to prevent the occurrence of unwanted RTC interrupts. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 83 1, the OSC1 oscillator circuit does not stop even if the IC enters SLEEP mode (the OSC1 clock will be supplied to the RTC only). When RTCCE is set to 0, RTC interrupt requests generated by RTCIEN/RTC_INTMODE register and RTCIRQ/RTC_INTSTAT register are masked to prevent occurrence of undesired interrupts. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 84 When RTC interrupts are enabled by RTCIEN, an interrupt request is sent to the ITC. RTCT[2:0] should be set while RTC interrupts are disabled. (These bits may also be set simultaneously when RTC interrupts are enabled.) Seiko epson Corporation 8-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 85 The description “30-second correction” means adding 1 to the minutes when seconds of the time clock are in the 30-to-59 second range, and doing nothing in the 0-to-29 second range. This function may be used to round up seconds to minutes when resetting seconds in an application. Seiko epson Corporation 8-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 86 RTCBSY: Counter Busy Flag Bit This flag indicates whether 1 is being carried over to the next-digit counter. 1 (R): Busy (while carry is taking place) 0 (R): Accessible for read/write (software reset value) Seiko epson Corporation 8-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 87 * Software reset (RTCRST → 1 → 0) does not affect the counter values. This register retains the value set before a software reset is performed. note: Data should not be read from or written to the counters while 1 is being carried over. (See Section 8.3.5, “Counter Hold and Busy Flag,” and Section 8.3.7, “Counter Read.”) Seiko epson Corporation 8-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 88 D3–0 RTCDl[3:0] RTC 1-day counter 0 to 9 X (*) R/W * Software reset (RTCRST → 1 → 0) does not affect the counter values. This register retains the value set before a software reset is performed. Seiko epson Corporation 8-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 89 Section 8.3.5, “Counter Hold and Busy Flag,” and Section 8.3.7, “Counter Read.”) • Rewriting RTC24H/RTC_CNTL0 register may corrupt the count data in this register. Therefore, after changing the RTC24H setting, be sure to set up this register again. Seiko epson Corporation 8-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 90 Table 8.5.3 lists the basic correspondence. Table 8. 5.3 Correspondence between Counter Values and Days of the Week RTCWK[2:0] Days of the week Saturday Friday Thursday Wednesday Tuesday Monday Sunday (Default: indeterminate, software reset: previous value retained) Seiko epson Corporation 8-16 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 91 The following shows the features of the P module: • S1C17624/622: Maximum 47 I/O ports (P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[6:0]) are available. S1C17604/602/621: Maximum 36 I/O ports (P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[3:0]) are available.
  • Page 92 *1: The P02, P13–P15, P36, P37, P47, and P50 pins can also be used as an external clock input pin for the timer module by setting them to input mode. However, general-purpose input port function is also effective in this case. In the S1C17624, either P36 or P47 can be selected as the EXCL5 input port and either P37 or P50 can be selected as the EXCL6 input port using EXCL5S/ P54_56PMUX register and EXCL6S/P54_56PMUX register.
  • Page 93 9 i/O PORTS (P) *2: Available only for S1C17624, *3: Available only for S1C17624/604, *4: Available only for S1C17624/622 *5: P43 can only be used as an output port. For how to configure P43, see the P43MUX/P40_43PMUX register description. At initial reset, each I/O port pin (Pxy) is initialized for the default function (“Pin function 1” in Table 9.2.1).
  • Page 94 (Fixed)” is fixed at CMOS Schmitt level and cannot be switched to CMOS level. In the S1C17624/622/604, the PxSMy bits for these ports are read-only bits (always read as 1) and cannot be altered. In the S1C17602/621, both 1 and 0 can be written to and read from these bits. However, the input interface level cannot be switched.
  • Page 95 Port input interrupts can be generated at either the rising edge or falling edge of the input signal. Select the edge used to generate interrupts using PxEDGEy/Px_EDGE register. Setting PxEDGEy to 1 generates port input interrupts at the input signal falling edge. Setting it to 0 (default) generates interrupts at the rising edge. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 96 Controls the P1 port chattering filter. 0x521a P1_IEN P1 Port Input Enable Register Enables P1 port inputs. 0x5220 P2_IN P2 Port Input Data Register P2 port input data 0x5221 P2_OUT P2 Port Output Data Register P2 port output data Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 97 P5[6:4] Port Function Select Register Selects the P5[6:4] port functions. * * Available only for S1C17624/622 The I/O port registers are described in detail below. These are 8-bit registers. note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
  • Page 98 D7–0 PxPu[7:0] Px[7:0] port pull-up enable 1 Enable 0 Disable Control Register 0x5213 (0xff) (Px_Pu) 0x5223 0x5233 0x5243 0x5253 (8 bits) note: The PxPUy bits for unavailable ports are reserved and always read as 0. Seiko epson Corporation S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 99 (* P43 is an output-only port.) In the S1C17624/622/604, the PxSMy bits for these ports are read-only bits that are always read as 1. In the S1C17602/621, both 1 and 0 can be written to and read from these bits. However, the input interface level cannot be switched.
  • Page 100 • The P port module interrupt flag PxIFy must be reset in the interrupt handler routine after a port interrupt has occurred to prevent recurring interrupts. • To prevent generating unnecessary interrupts, reset the relevant PxIFy before enabling in- terrupts for the required port using PxIEy/Px_IMSK register. Seiko epson Corporation 9-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 101 Px interrupt. Also the chattering filter circuit requires a maximum of twice the check time for stabilizing the operation status. Before enabling the interrupt, make sure that the stabilization time has elapsed. Seiko epson Corporation 9-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 102 Px_IN register. Setting to 0 disables input. Refer to Table 9.3.1 for more information on port input/output status, including settings other than for the Px_IEN register. Seiko epson Corporation 9-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 103 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): REMI (REMC) 0x0 (R/W): P01 (default) D[1:0] P00MuX[1:0]: P00 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): REMO (REMC) 0x0 (R/W): P00 (default) Seiko epson Corporation 9-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 104 0x2 (R/W): Reserved 0x1 (R/W): SDO0 (SPI Ch.0) 0x0 (R/W): P05 (default) D[1:0] P04MuX[1:0]: P04 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SPICLK0 (SPI Ch.0) 0x0 (R/W): P04 (default) Seiko epson Corporation 9-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 105 0x2 (R/W): Reserved 0x1 (R/W): SOUT0 (UART Ch.0) 0x0 (R/W): P11 (default) D[1:0] P10MuX[1:0]: P10 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SCLK0 (UART Ch.0) 0x0 (R/W): P10 (default) Seiko epson Corporation 9-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 106 0x2 (R/W): AIN6 (ADC10) 0x1 (R/W): Reserved 0x0 (R/W): P14/EXCL2 (T16 Ch.2) (default) To use the P14 pin for EXCL2 input, P1OEN4/P1_OEN register must be set to 0 and P1IEN4/P1_IEN register must be set to 1. Seiko epson Corporation 9-16 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 107 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): AIN1 (ADC10) 0x0 (R/W): P21 (default) D[1:0] P20MuX[1:0]: P20 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): AIN2 (ADC10) 0x0 (R/W): P20 (default) Seiko epson Corporation 9-17 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 108 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): REF0 (RFC) 0x0 (R/W): P25 (default) D[1:0] P24MuX[1:0]: P24 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SENA0 (RFC) 0x0 (R/W): P24 (default) Seiko epson Corporation 9-18 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 109 D[7:6] P33MuX[1:0]: P33 Port Function Select Bits 0x3 (R/W): TOUTA6 (T16A2 Ch.1 comparator mode) or CAPA6 (T16A2 Ch.1 capture mode) (Selectable only in the S1C17624/604) 0x2 (R/W): SCL0 (I2CM) 0x1 (R/W): SCL1 (I2CS) 0x0 (R/W): P33 (default) D[5:4] P32MuX[1:0]: P32 Port Function Select Bits 0x3 (R/W): TOUTB5 (T16A2 Ch.0 comparator mode)
  • Page 110 0x1 (R/W): TOUTN3 (T16E Ch.0) 0x0 (R/W): P37/EXCL6 (T16A2 Ch.1) (default) (EXCL6 is available only in the S1C17624/604.) To use the P37 pin for EXCL6 input, P3OEN7/P3_OEN register must be set to 0 and P3IEN7/P3_IEN register must be set to 1. In addition to these settings, EXCL6S/P54_56PMUX register must be set to 0 in the S1C17624.
  • Page 111 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): P41 0x0 (R/W): DSIO (DBG) (default) D[1:0] P40MuX[1:0]: P40 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): FOUTH (CLG) 0x0 (R/W): P40 (default) Seiko epson Corporation 9-21 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 112 0x0 R/W reserved reserved SCL1 note: This register is effective only in the S1C17624/622. The P44 to P47 port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:6] P47MuX[1:0]: P47 Port Function Select Bits...
  • Page 113 (Set EXCL6S to 1.) SCLK1 P50/EXCL6 note: This register is effective only in the S1C17624/622. The P50 to P53 port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:6]...
  • Page 114 LFRO note: This register is effective only in the S1C17624/622. The P54 to P56 port pins are shared with the peripheral module pins. This register is used to select how the pins are used. eXCl6S: eXCl6 input Select Bit Selects a port to be used as the EXCL6 input.
  • Page 115 Fine Mode 8-bit Timers (T8F) 10.1 T8F Module Overview The S1C17624/604/622/602/621 includes two-channel fine mode 8-bit timer module (T8F). The features of the T8F module are listed below. • 8-bit presettable down counter with an 8-bit reload data register for setting the preset value •...
  • Page 116 (or between underflows). The time determined is used to obtain the specified wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. Seiko epson Corporation 10-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 117 Write 0 to PRUN to stop the timer via the application program. The counter stops counting and retains the current counter value until either the timer is reset or restarted. To restart the count from the initial value, the timer should be reset before writing 1 to PRUN. Seiko epson Corporation 10-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 118 TFMD[3:0] specifies the delay pattern to be inserted into a 16 underflow period. Inserting one delay extends the output clock cycle by one count clock cycle. This setting delays the interrupt timing in the same way. Seiko epson Corporation 10-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 119 • The T8F module interrupt flag T8FIF must be reset in the interrupt handler routine after a T8F interrupt has occurred to prevent recurring interrupts. • Reset T8FIF before enabling T8F interrupts with T8FIE to prevent occurrence of unwanted in- terrupt. T8FIF is reset by writing 1. Seiko epson Corporation 10-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 120 D15–8 – reserved – – – 0 when being read. Reload Data 0x4282 D7–0 TR[7:0] Reload data 0x0 to 0xff 0x0 R/W Register (16 bits) TR7 = MSB (T8F_TRx) TR0 = LSB D[15:8] Reserved Seiko epson Corporation 10-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 121 – – – – – – – – – – – – – – – – – – – – – – – – – D: Indicates the insertion of a delay cycle. Seiko epson Corporation 10-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 122 Enables or disables interrupts caused by counter underflows for each channel. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Setting T8FIE to 1 enables T8F interrupt requests to the ITC; setting to 0 disables interrupts. Seiko epson Corporation 10-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 123 No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored T8FIF is the T8F module interrupt flag that is set to 1 when the counter underflows. T8FIF is reset by writing 1. Seiko epson Corporation 10-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 124 16-bit Timers (T16) 11.1 T16 Module Overview The S1C17624/604/622/602/621 includes three-channel 16-bit timer module (T16). The features of the T16 module are listed below. • 16-bit presettable down counter with a 16-bit reload data register for setting the preset value •...
  • Page 125 15 types shown below using DF[3:0]/T16_CLKx register. Table 11. 3.1.1 PCLK Division Ratio Selection DF[3:0] Division ratio DF[3:0] Division ratio Reserved 1/128 1/16384 1/64 1/8192 1/32 1/4096 1/16 1/2048 1/1024 1/512 1/256 (Default: 0x0) Seiko epson Corporation 11-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 126 CKACTV/T16_CTLx register is used to select the active level for the pulses counted. Setting CKACTV to 1 (default) will measure the high period and setting it to 0 will measure the low period. Seiko epson Corporation 11-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 127 (or between underflows). The time determined is used to obtain the specified wait time, the intervals between periodic interrupts or A/D conversion triggers, and the programmable serial interface transfer clock. Seiko epson Corporation 11-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 128 In pulse width measurement mode, the timer counts only while PRUN is set to 1 and the external input signal is at the specified active level. When the external input signal becomes inactive, the timer stops counting and retains the counter value until the next active level input. (See Figure 11.3.3.1.) Seiko epson Corporation 11-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 129 T16 module, is set to 1. At the same time, an interrupt request is sent to the ITC if T16IE/T16_INTx reg- ister has been set to 1 (interrupt enabled). An interrupt is generated if the ITC and S1C17 Core interrupt condi- tions are satisfied. Seiko epson Corporation 11-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 130 Count clock division ratio select DF[3:0] Division ratio 0x0 R/W Source clock = PCLK Register 0x4260 reserved (T16_ClKx) (16 bits) 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 D[15:4] Reserved Seiko epson Corporation 11-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 131 Count mode select 1 One shot 0 Repeat D3–2 – reserved – – – 0 when being read. PReSeR Timer reset 1 Reset 0 Ignored PRun Timer run/stop control 1 Run 0 Stop D[15:11] Reserved Seiko epson Corporation 11-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 132 PReSeR: Timer Reset Bit Resets the timer. 1 (W): Reset 0 (W): Ignored 0 (R): Always 0 when read (default) Writing 1 to this bit presets the counter to the reload data value. Seiko epson Corporation 11-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 133 No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored T16IF is the T16 module interrupt flag that is set to 1 when the counter underflows. T16IF is reset by writing 1. Seiko epson Corporation 11-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 134 16-bit PWM Timer (T16E) 12.1 T16e Module Overview The S1C17624/604/622/602/621 includes a 16-bit PWM timer module (T16E) with one timer channel (Ch.0). The features of T16E are listed below. • 16-bit up counter with a comparator • The counter value can be compared with two specified comparison values by the comparator.
  • Page 135 To input an external clock to T16E, the I/O port shared with an EXCLx input must be set to input mode in advance. For detailed information on the port control, see the “I/O Ports (P)” chapter. The T16E counter counts up at the rising edge of the input signal. Seiko epson Corporation 12-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 136 The T16E module includes T16ERUN/T16E_CTLx register to control run/stop of the timer. The timer starts counting when 1 is written to T16ERUN. Writing 0 to T16ERUN disables clock input and stops the count. Seiko epson Corporation 12-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 137 Switching the pin function to TOUTx/TOUTNx output causes the pin to output the level set by INITOL and IN- VOUT. After the timer output starts, the output is maintained at this level until changed by the counter value. Seiko epson Corporation 12-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 138 TC[14:0] matches the compare data A register CA[15:1]. When CA0 is 0: Changes at the rising edge of the count clock. When CA0 is 1: Changes at the half-cycle delayed falling edge of the count clock. Seiko epson Corporation 12-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 139 • Reset the interrupt flag before enabling interrupts with the interrupt enable bit to prevent oc- currence of unwanted interrupt. The interrupt flag is reset by writing 1. • After an interrupt occurs, the interrupt flag in the T16E module must be reset in the interrupt handler routine. Seiko epson Corporation 12-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 140 TC15 = MSB Register TC0 = LSB (T16e_TCx) D[15:0] TC[15:0]: Counter Data Counter data can be read out. (Default: 0x0) The counter value can also be set by writing data to this register. Seiko epson Corporation 12-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 141 (a clock input via the EXCLx pin) and it functions as an event counter. To input an external clock/pulse to T16E, the I/O port shared with an EXCLx input must be set to input mode. Seiko epson Corporation 12-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 142 Selects a PCLK division ratio to generate the count clock. Table 12. 9.2 PCLK Division Ratio Selection T16eDF[3:0] Division ratio T16eDF[3:0] Division ratio Reserved 1/128 1/16384 1/64 1/8192 1/32 1/4096 1/16 1/2048 1/1024 1/512 1/256 (Default: 0x0) Seiko epson Corporation 12-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 143 Flag is reset 0 (W): Ignored CAIF is a T16E interrupt flag that is set to 1 when the counter reaches the value set in the compare A register. CAIF is reset by writing 1. Seiko epson Corporation 12-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 144 13.1 T16a2 Module Overview The S1C17624/604 includes a 16-bit PWM timer (T16A2) module that consists of counter blocks and comparator/ capture blocks. This timer can be used as an interval timer, PWM waveform generator, external event counter and a count capture unit to measure external event periods.
  • Page 145 For detailed information on pin function switching and port control, see the “I/O Ports (P)” chapter. 13.3 Count Clock The clock controller includes a clock source selector, dividers, and a gate circuit for controlling the count clock. The count clock can be controlled in each channel individually. Seiko epson Corporation 13-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 146 Division ratio ClKDiV[3:0] Clock source = iOSC or OSC3 Clock source = OSC1 Reserved 1/16384 Reserved 1/8192 Reserved 1/4096 Reserved 1/2048 Reserved 1/1024 Reserved 1/512 Reserved 1/256 1/128 1/64 1/32 1/16 (Default: 0x0) Seiko epson Corporation 13-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 147 A and B buffer values instead of the com- pare A and B register values. The compare A and B register values written via software are loaded to the compare A and B buffers when the compare B signal is generated. Seiko epson Corporation 13-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 148 0 or returns to 0 due to a counter overflow. The coun- ter should be set to this mode to generate periodic interrupts at desired intervals or to generate a timer output waveform. Seiko epson Corporation 13-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 149 Comparator/capture block Ch.0 CAPA5/CAPB5 OSC3 OSC1 Interrupt request EXCL5 TOUTA6/TOUTB6 IOSC Clock controller Ch.1 Counter block Ch.1 Comparator/capture block Ch.1 OSC3 CAPA6/CAPB6 OSC1 Interrupt request EXCL6 Figure 13. 4.3.2 Timer Configuration in Multi-Comparator/Capture Mode Seiko epson Corporation 13-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 150 This control does not affect the counter data. The counter data is retained even when the count is halted, allowing resumption of the count from that data. note: After the T16A_CCAx and T16A_CCBx registers have been set, wait for one or more T16A2 count clock cycles and then run the counter. Seiko epson Corporation 13-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 151 Comparator/capture block Ch.x TOUT A Compare A signal Compare B signal output TOUTAx TOUTAMD[1:0] control TOUTAINV Compare A signal TOUT B Compare B signal output TOUTBx control TOUTBMD[1:0] TOUTBINV Figure 13. 6.1 TOUT Output Circuit Seiko epson Corporation 13-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 152 (TOUTAMD[1:0] = 0x2, TOUTAINV = 0) (TOUTAMD[1:0] = 0x2, TOUTAINV = 1) (TOUTAMD[1:0] = 0x3, TOUTAINV = 0) (TOUTAMD[1:0] = 0x3, TOUTAINV = 1) (When T16A_CCAx = 3, T16A_CCBx = 5) Figure 13. 6.2 TOUT Output Waveform Seiko epson Corporation 13-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 153 Each timer channel outputs a single interrupt signal shared by the above interrupt causes to the interrupt controller (ITC). Read the interrupt flags in the T16A2 module to identify the interrupt cause that has been occurred. Seiko epson Corporation 13-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 154 ITC. An interrupt is generated if the ITC and S1C17 core interrupt conditions are satisfied. For more information on interrupt control registers and the operation when an interrupt occurs, see the “Interrupt Controller (ITC)” chapter. Seiko epson Corporation 13-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 155 Count clock enable 1 Enable 0 Disable D[7:4] ClKDiV[3:0]: Clock Division Ratio Select Bits Selects the division ratio for generating the count clock when an internal clock (IOSC, OSC3, or OSC1) is used. Seiko epson Corporation 13-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 156 The CLKEN default setting is 0, which disables the clock supply. Setting CLKEN to 1 sends the clock selected as above to the counter. If timer operation is not required, disable the clock supply to reduce current consumption. Seiko epson Corporation 13-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 157 A and B buffer values instead of the compare A and B register values. The compare A and B register values written via software are loaded to the compare A and B buffers when the compare B signal is generated. Seiko epson Corporation 13-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 158 16-bit transfer instruction. If data is read twice using an 8-bit transfer instruction, the correct value may not be obtained due to occurrence of count up between readings. Seiko epson Corporation 13-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 159 Writing 1 to TOUTBINV generates an active Low signal (Off level = High) for the TOUT B output. When TOUTBINV is 0, an active High signal (Off level = Low) is generated. TOUTBINV is a control bit for comparator mode and is ineffective in capture mode. Seiko epson Corporation 13-16 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 160 When CCAMD is 0, the T16A_ CCAx register functions as the compare A register (comparator mode) for writing a comparison value to generate the compare A signal. Seiko epson Corporation 13-17 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 161 0 Disable Register CaPaie Capture A interrupt enable 1 Enable 0 Disable (T16a_ienx) CBie Compare B interrupt enable 1 Enable 0 Disable Caie Compare A interrupt enable 1 Enable 0 Disable D[15:6] Reserved Seiko epson Corporation 13-18 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 162 Indicates whether the cause of capture B overwrite interrupt has occurred or not. 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored Seiko epson Corporation 13-19 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 163 Flag is reset 0 (W): Ignored CAIF is a T16A2 interrupt flag that is set to 1 when the counter reaches the value set in the compare A register. CAIF is reset by writing 1. Seiko epson Corporation 13-20 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 164 8-bit OSC1 Timer (T8OSC1) 14.1 T8OSC1 Module Overview The S1C17624/604/622/602/621 includes a single-channel 8-bit OSC1 timer that uses OSC1 as its clock source. The features of the T8OSC1 module are listed below. • 8-bit up counter with a comparator • The counter value can be compared with two specified comparison values (compare data and PWM duty data) by the comparator.
  • Page 165 • If count operation is activated while the count mode is set to one-shot mode, and the CPU en- ters halt state, the counter does not stop even when a compare match occurs, disabling one- shot operation. Seiko epson Corporation 14-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 166 The counter is reset to 0 at the same time. If interrupts are enabled, an in- terrupt request is sent to the interrupt controller (ITC). If one-shot mode is set, the timer stops the count. If repeat mode is set, the timer continues to count from 0. Seiko epson Corporation 14-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 167 (2) When the PWM duty data is set greater than the compare data, only the compare match signal will be gen- erated. No duty match signal will be generated. In that case, the TOUT4 output is fixed at low. Seiko epson Corporation 14-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 168 0x0 R/W Clock source: OSC1 (OSC_T8OSC1) [2:0] 0x7–0x6 reserved 1/32 1/16 T8O1Ce Clock enable 1 Enable 0 Disable D[7:4] Reserved D[3:1] T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits Selects the division ratio for generating the count clock. Seiko epson Corporation 14-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 169 Note that the timer resets the counter and then stops after a compare match has occurred. Set T8OSC1 to this mode to create a specific wait time. note: Set the count mode only while T8OSC1 count is stopped. Seiko epson Corporation 14-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 170 – 0 when being read. interrupt Flag (8 bits) T8OiF T8OSC1 interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Register interrupt interrupt not (T8OSC1_iFlG) occurred occurred D[7:1] Reserved Seiko epson Corporation 14-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 171 The set data is compared against the counter data. If the contents match, the timer output waveform rises. If the counter data matches the compare data, the timer output waveform falls. These processes do not affect the counter data or count process. Seiko epson Corporation 14-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 172 15.1 CT Module Overview The S1C17624/604/622/602/621 includes a clock timer module (CT) that uses the OSC1 oscillator as its clock source. This timer can be used for generating cyclic interrupts to implement a software clock function. The features of the CT module are listed below.
  • Page 173 1 (interrupt enabled). An interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied. If the interrupt enable bit is set to 0 (interrupt disabled, default), no interrupt request will be sent to the ITC. Seiko epson Corporation 15-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 174 Stop state until a reset or the next Run state. Clock Timer Counter Register (CT_CnT) Register name address name Function Setting init. R/W Remarks Clock Timer 0x5001 D7–0 CTCnT[7:0] Clock timer counter value 0x0 to 0xff Counter Register (8 bits) (CT_CnT) Seiko epson Corporation 15-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 175 1 at the falling edge of the corresponding 32 Hz, 8 Hz, 2 Hz, or 1 Hz interrupt. CTIF* is reset by writing 1. D[7:4] Reserved Seiko epson Corporation 15-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 176 Indicates whether the cause of 1 Hz interrupt has occurred or not. 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored Seiko epson Corporation 15-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 177 16.1 SWT Module Overview The S1C17624/604/622/602/621 includes a 1/100-second stopwatch timer module (SWT) that uses the OSC1 oscil- lator as its clock source. This timer can be used to implement a software stopwatch function. The features of the SWT module are listed below.
  • Page 178 A cause of interrupt occurs during counting at the 100 Hz (approximate 100 Hz), 10 Hz (approximate 10 Hz), and 1 Hz signal falling edges. If interrupts are enabled, an interrupt request is sent to the interrupt controller (ITC). Seiko epson Corporation 16-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 179 100 Hz Interrupt SIF100/SWT_IFLG register SIE100/SWT_IMSK register 10 Hz Interrupt SIF10/SWT_IFLG register SIE10/SWT_IMSK register 1 Hz Interrupt SIF1/SWT_IFLG register SIE1/SWT_IMSK register For specific information on interrupt processing, see the “Interrupt Controller (ITC)” chapter. Seiko epson Corporation 16-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 180 This register is read-only and cannot be written to. D[3:0] BCD100[3:0]: 1/100 Sec. BCD Counter Value Bits The 1/100-second counter BCD data can be read out. (Default: 0) This register is read-only and cannot be written to. Seiko epson Corporation 16-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 181 Indicates whether the cause of 10 Hz interrupt has occurred or not. 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored Seiko epson Corporation 16-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 182 Indicates whether the cause of 100 Hz interrupt has occurred or not. 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored Seiko epson Corporation 16-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 183 Watchdog Timer (WDT) 17.1 WDT Module Overview The S1C17624/604/622/602/621 includes a watchdog timer module (WDT) that uses the OSC1 oscillator as its clock source. This timer is used to detect CPU runaway. The features of WDT are listed below. • 10-bit up counter •...
  • Page 184 To use WDT, it must be reset by writing 1 to this bit within the NMI/reset generation cycle (4 seconds when f = 32.768 kHz). This resets the up-counter to 0 and starts counting with a OSC1 new NMI/reset generation cycle. Seiko epson Corporation 17-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 185 This bit confirms that WDT was the source of the NMI. The WDTST set to 1 is cleared to 0 by resetting WDT. This is also set by a counter overflow if reset output is selected, but is cleared by initial reset and cannot be confirmed. Seiko epson Corporation 17-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 186 18.1 uaRT Module Overview The S1C17624/604/622/602/621 includes a UART module with two asynchronous communication channels. It includes a 2-byte receive data buffer and 1-byte transmit data buffer allowing successive data transfer. The UART module also includes an RZI modulator/demodulator circuit that enables IrDA 1.0-compatible infrared communica- tions simply by adding basic external circuits.
  • Page 187 Data length The data length is selected by CHLN/UART_MODx register. Setting CHLN to 0 (default) configures the data length to 7 bits. Setting CHLN to 1 configures it to 8 bits. Seiko epson Corporation 18-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 188 LSB. The transfer data bit is shifted in sync with the sampling clock rising edge and output in sequence via the SOUTx pin. Following output of MSB, the parity bit (if parity is en- abled) and the stop bit are output. Seiko epson Corporation 18-3 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 189: Uart: Data Reception Control

    This resets the RD2B flag. The buffer then reverts to the state in (2) above. The second read outputs the most recent received data, after which the buffer reverts to the state in (1) above. Seiko epson Corporation 18-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 190 However, the received data cannot be guaranteed if a parity error occurs. The PER flag is reset to 0 by writing 1. Seiko epson Corporation 18-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 191 The UART sets an error flag, PER, FER, or OER/UART_STx register to 1 if a parity error, framing error, or overrun error is detected when receiving data. If receive error interrupts are enabled (REIEN = 1), an interrupt request is sent simultaneously to the ITC. Seiko epson Corporation 18-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 192 This setting must be performed before setting other UART conditions. irDa receive detection clock selection The input pulse detection clock is generated by dividing PCLK. The division ratio can be selected using IR- CLK[2:0]/UART_EXPx register. Seiko epson Corporation 18-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 193 0 Empty TRBS Transmit busy flag 1 Busy 0 Idle Shift register status RDRY Receive data ready flag 1 Ready 0 Empty TDBe Transmit data buffer empty flag 1 Empty 0 Not empty Reserved Seiko epson Corporation 18-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 194 Buffer empty (default) RDRY is set to 1 when received data is loaded into the receive data buffer and is reset to 0 when all data has been read from the receive data buffer. Seiko epson Corporation 18-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 195 1 With parity 0 No parity Parity mode select 1 Odd 0 Even STPB Stop bit select 1 2 bits 0 1 bit SSCK Input clock select 1 External 0 Internal D[7:5] Reserved Seiko epson Corporation 18-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 196 Enables interrupt requests to the ITC caused when the received data quantity in the receive data buffer reaches the quantity specified in RBFI. 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to read received data using interrupts. Seiko epson Corporation 18-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 197 Selects a PCLK division ratio to generate the IrDA input pulse detection clock. Table 18. 9.2 IrDA Receive Detection Clock (PCLK Division Ratio) Selection iRClK[2:0] Division ratio 1/128 1/64 1/32 1/16 (Default: 0x0) Seiko epson Corporation 18-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 198 1 (R/W): On 0 (R/W): Off (default) Set IRMD to 1 to use the IrDA interface. When IRMD is set to 0, this module functions as a normal UART, with no IrDA functions. Seiko epson Corporation 18-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 199 1.1 SPI Module Configuration notes: • In the S1C17602/621, the transmit buffer empty interrupt can only be used in master mode. In the S1C17624/604/622, the transmit buffer empty interrupt can be used in both master and slave modes. • The letter ‘x’ in register and pin names refers to a channel number (0).
  • Page 200 The SPI clock polarity is selected by CPOL/SPI_CTLx register. Setting CPOL to 1 treats the SPI clock as ac- tive Low; setting it to 0 (default) treats it as active High. The SPI clock phase is selected by CPHA/SPI_CTLx register. As shown below, these control bits set transfer timing. Seiko epson Corporation 19-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 201 In slave mode, SPBSY flag indicates the SPI slave selection signal (#SPISSx pin) status. The flag is set to 1 when the SPI module is selected as a slave module and is set to 0 when the module is not selected. Seiko epson Corporation 19-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 202 In master mode, the SPBSY flag indicating the shift register status can be used in the same way while transfer- ring data. Seiko epson Corporation 19-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 203 In the S1C17602/621, the transmit buffer empty interrupt can only be used in master mode. In the S1C17624/604/622, the transmit buffer empty interrupt can be used in both master and slave modes.
  • Page 204 It reverts to 0 once the buffer data is read from the SPI_RXDx register. SPTBe: Transmit Data Buffer empty Flag Bit Indicates the transmit data buffer status. 1 (R): Empty (default) 0 (R): Data exists Seiko epson Corporation 19-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 205 1 Enable 0 Disable note: In the S1C17602/621, do not access to the SPI_CTLx register while SPBSY/SPI_STx register is set to 1 or SPRBF/SPI_STx register is set to 1 (while data is being transmitted/received). Seiko epson Corporation 19-7 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 206: The Receive Data Buffer

    SPI interrupts are not generated by transmit data buffer empty if SPTIE is set to 0. note: In the S1C17602/621, the transmit buffer empty interrupt can only be used in master mode. In the S1C17624/604/622, the transmit buffer empty interrupt can be used in both master and slave modes.
  • Page 207 Setting SPEN to 1 starts the SPI module operation, enabling data transfer. Setting SPEN to 0 stops the SPI module operation. note: The SPEN bit should be set to 0 before setting the CPHA, CPOL, and MSSL bits. Seiko epson Corporation 19-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 208 C MaSTeR (i2CM) C Master (I2CM) 20.1 i2CM Module Overview The S1C17624/604/622/602/621 includes an I C master (I2CM) module that supports two-wire communications. The I2CM module operates as an I C bus master device and can communicate with I C-compliant slave devices.
  • Page 209 C master (this module) must generate a start condition. The slave address is then sent to establish communications. (1) Generating start condition The start condition applies when the SCL line is maintained at High and the SDA line is pulled down to Low. Seiko epson Corporation 20-2 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 210: I2Cm: Transmit Data Specifying Slave Address And Transfer Direction

    MSB leading. The I2CM module outputs 9 clocks with each data transmission. In the 9th clock cycle, the I2CM module sets the SDA line into high impedance to receive an ACK or NAK sent from the slave device. Seiko epson Corporation 20-3 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 211: I2Cm: Data Reception Control

    3. Wait for RBUSY to become 1 (reception start). 4. Wait for RBUSY to become 0 (reception end). 5. Read out RTDT (received data). 6. Enables interrupts to the CPU using the ei instruction. Seiko epson Corporation 20-4 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 212: I2Cm: End Of Data Transfers (Generating Stop Condition)

    C bus is in busy status, the SCL0 and SDA0 output levels and transfer data at that point cannot be guaranteed. Timing chart STRT setting Start condition C bus busy PCLK T16 Ch.2 output SCL0 SDA0 STRT Figure 20. 5.6 Start Condition Generation Seiko epson Corporation 20-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 213 The I2CM module includes a function for generating the following two different types of interrupts. • Transmit buffer empty interrupt • Receive buffer full interrupt The I2CM module outputs one interrupt signal shared by the two above interrupt causes to the interrupt controller (ITC). Seiko epson Corporation 20-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 214 Enables or disables I2CM module operation. 1 (R/W): Enabled 0 (R/W): Disabled (default) Setting I2CMEN to 1 starts the I2CM module operation, enabling data transfer. Setting I2CMEN to 0 stops the I2CM module operation. Seiko epson Corporation 20-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 215 The repeated start condition can be generated by setting STRT to 1 when the I C bus is busy. STRT is automatically reset to 0 once the start condition or repeated start condition is generated. The C bus subsequently becomes busy. Seiko epson Corporation 20-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 216 “Data reception control” in Section 20.5. In the S1C17624/604/622, the RBRDY flag can be used to await reception with polling. Ac- cess the I2CM_DAT register in 16-bit size to read both RBRDY and RTDT[7:0] at a time and use the RTDT[7:0] value as valid receive data when RBRDY = 1.
  • Page 217 These interrupt requests are generated when the data written to RTDT[7:0] is transferred to the shift register. I2CM interrupts are not generated by transmit buffer empty if TINTE is set to 0. Seiko epson Corporation 20-10 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 218: I2Cs: I2Cs Module Overview

    C SlaVe (i2CS) C Slave (I2CS) 21.1 i2CS Module Overview The S1C17624/604/622/602/621 includes an I C slave (I2CS) module that supports two-wire communications. The I2CS module operates as an I C bus slave device and can communicate with an I C-compliant master device.

  • Page 219: I2Cs: Bus Free Request With An Input From The #Bfr Pin

    The control registers will not be initialized as distinct from the software reset described above. note: When BFREQ is set to 1 (an interrupt can be used for checking this status), perform a software reset and set the registers again. Seiko epson Corporation 21-2 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 220: I2Cs: Clock Stretch Function

    (1) Initialize the I2CS module. See Section 21.4. (2) Set the interrupt conditions to use I2CS interrupt. See Section 21.6. note: Make sure that the I2CS module is disabled (I2CSEN/I2CS_CTL register = 0) before setting the conditions above. Seiko epson Corporation 21-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 221 1. If the previous transmit data is still stored in SDATA[7:0], it is overwritten with the new data to be transferred. Therefore, the clear operation (see below) using TBUF_CLR is unnecessary. Seiko epson Corporation 21-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 222 SDA line. An interrupt can be generated when DMS is set to 1, so an error handling can be performed in the interrupt handler routine. DMS is cleared by writing 1. Seiko epson Corporation 21-5 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 223: The I2Cs Module Is Placed Into Transfer Standby State

    Data transfers will be terminated when the master generates a stop condition. The stop condition is a state in which the SDA line is pulled up from Low to High with the SCL line maintained at High. Seiko epson Corporation 21-6 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 224: I2Cs: Timing Charts

    SDATA[7:0] D[7:0] Interrupt Transmit interrupt Transmit data is set. Bus status interrupt 5.6 I2CS Timing Chart 2 (data transmission → stop condition) Figure 21. Seiko epson Corporation 21-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 225 RDATA[7:0]. Set RXRDY_IEN/I2CS_ICTL register to 1 when using this interrupt. If RXRDY_IEN is set to 0 (default), in- terrupt requests by this cause will not be sent to the ITC. Seiko epson Corporation 21-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 226 The I2CS module registers are described in detail below. These are 16-bit registers. note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. Seiko epson Corporation 21-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 227 C clock (SCL1 input clock) after RXRDY is set to 1. If the next data has been received without reading the received data, this register will be overwritten with the newly received data. Seiko epson Corporation 21-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 228 SCL1 pins into high-impedance to be ready to detect a start condition. Furthermore, the I2CS con- trol bits except for SOFTRESET are initialized. Perform the software reset in the initial setting process before staring communication. Seiko epson Corporation 21-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 229 • When the asynchronous address detection function is enabled, the I C bus signals are input without passing through the noise filter. Therefore, the slave address may not be detected in a high-noise environment. Seiko epson Corporation 21-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 230 After TXUDF/RXOVF is set to 1, it is reset to 0 by writing 1. BFReQ: Bus Free Request Bit Indicates the I C bus free request input status. 1 (R/W): Request has been issued 0 (R/W): Request has not been issued (default) Seiko epson Corporation 21-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 231 ITC if the interrupt is enabled with BSTAT_IEN/I2CS_ICTL register. This inter- rupt can be used to perform an error handling. After DA_NAK is set to 1, it is reset to 0 by writing 1. Seiko epson Corporation 21-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 232 When the slave address that is set in this module is received, SELECTED is set to 1 to indicate that this module is selected as the I C slave device. After SELECTED is set to 1, it is reset to 0 when a stop con- dition or a repeated start condition is detected. Seiko epson Corporation 21-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 233 When TXEMP_IEN is set to 1, I2CS transmit interrupt requests to the ITC are enabled. A transmit in- terrupt request occurs when the data written to the I2CS_TRNS register is transferred to the shift regis- ter. When TXEMP_IEN is set to 0, a transmit interrupt will not be generated. Seiko epson Corporation 21-16 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 234 IR Remote Controller (REMC) 22.1 ReMC Module Overview The S1C17624/604/622/602/621 includes an IR remote controller (REMC) module for transmitting/receiving infra- red remote control communication signals. The following shows the features of the REMC module: • Supports input and output infrared remote control communication signals.
  • Page 235 0xff using the interrupt when the input changes and by reading out the count value when a subsequent interrupt occurs due to input changes. Seiko epson Corporation 22-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 236 Enable REMC operation by setting REMEN/REMC_CFG register to 1. This initiates REMC transmission. Set REMDT/REMC_LCNT register to 0 and REMLEN[7:0]/REMC_LCNT register to 0x0 before setting REMEN to 1 to prevent unnecessary data transmission. Seiko epson Corporation 22-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 237 Note that if the signal level after the input has changed is not detected for at least two continuous sampling clock cycles, the input signal transition is interpreted as noise, and no rising or falling edge interrupt is gener- ated. Seiko epson Corporation 22-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 238 REMRIF should be inspected in the REMC interrupt handler routine to determine whether the REMC interrupt is attributable to input signal rising edge. The interrupt cause should be cleared in the interrupt handler routine by resetting (writing 1 to) REMRIF. Seiko epson Corporation 22-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 239 Selects a carrier generation clock (PCLK division ratio). Table 22. 7.2 Carrier Generation Clock (PCLK Division Ratio) Selection CGClK[3:0] Division ratio CGClK[3:0] Division ratio Reserved 1/128 1/16384 1/64 1/8192 1/32 1/4096 1/16 1/2048 1/1024 1/512 1/256 (Default: 0x0) Seiko epson Corporation 22-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 240 Sets the carrier signal H section length. (Default: 0x0) Specify a value corresponding to the number of carrier generation clock cycles selected by CGCLK[3:0]/ REMC_CFG register + 1. Calculate carrier H section length as follows: Seiko epson Corporation 22-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 241 If REMEN/REMC_CFG register is set to 1, the REMDT setting is modulated by the carrier signal for data transmission and output from the REMO pin. For data receiving, this bit is set to the value corre- sponding to the signal level of the data pulse input. Seiko epson Corporation 22-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 242 REMUIF is set to 1 when a data length counter underflow occurs. REMUIF is reset to 0 by writing 1. D[7:3] Reserved ReMFie: Falling edge interrupt enable Bit Enables or disables input signal falling edge interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Seiko epson Corporation 22-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 243 Enables or disables input signal rising edge interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) ReMuie: underflow interrupt enable Bit Enables or disables data length counter underflow interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Seiko epson Corporation 22-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 244 23.1 lCD Module Overview The S1C17624/622 and S1C17604/602/621 include a dot-matrix LCD driver capable of driving an LCD panel with up to 416 segments (52 segments × 8 commons) and 288 segments (36 segments × 8 commons), respectively. The main features of the LCD driver are listed below.
  • Page 245 The LCD driver generates the frame signal by dividing LCLK. The clock division ratio can be set using FRM- CNT[1:0]/LCD_CCTL register. Figures 23.4.2.1 to 23.4.2.5 show one cycle of the frame frequency as “1 frame.” Tables 23.3.2.1 and 23.3.2.2 list the frame frequencies that can be programmed. Seiko epson Corporation 23-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 246 Drive duty can be set to 1/8, 1/4, 1/3, 1/2 or static drive using LDUTY[2:0]/LCD_CCTL register. Tables 23.4.1.1 and 23.4.1.2 show the correspondence between LDUTY[2:0] settings, drive duty, and maximum number of display segments. S1C17624/622 Table 23. 4.1.1 Drive Duty Settings (S1C17624/622) Max. number of lDuTY[2:0] Duty Valid COM pins...
  • Page 247 The drive bias is fixed at 1/3 (three potentials V ) for all duty settings. 23.4.2 Drive Waveform Figures 23.4.2.1 to 23.4.2.5 shows the drive waveforms according to the duty selections. Seiko epson Corporation 23-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 248 23 lCD DRiVeR (lCD) Frame interrupt Frame interrupt 1 frame LFRO COM0 COM1 COM2 COM3 COM4 display status COM0 COM5 COM6 SEGx COM7 SEGx Figure 23. 4.2.1 1/8 Duty Drive Waveform Seiko epson Corporation 23-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 249 23 lCD DRiVeR (lCD) Frame interrupt Frame interrupt 1 frame LFRO COM0 display status COM1 COM0 COM2 SEGx COM3 SEGx Figure 23. 4.2.2 1/4 Duty Drive Waveform Seiko epson Corporation 23-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 250 23 lCD DRiVeR (lCD) Frame interrupt Frame interrupt 1 frame LFRO COM0 display status COM0 COM1 SEGx COM2 SEGx Figure 23. 4.2.3 1/3 Duty Drive Waveform Seiko epson Corporation 23-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 251 COM0 COM0 SEGx COM1 SEGx Figure 23. 4.2.4 1/2 Duty Drive Waveform Frame interrupt Frame interrupt 1 frame display status LFRO COM0 SEGx COM0 SEGx Figure 23. 4.2.5 Static Drive Waveform Seiko epson Corporation 23-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 252 23.5 Display Memory The S1C17624/622 includes a 56-byte display memory (address 0x53c0 to address 0x53f7). The S1C17604/602/621 includes a 40-byte display memory (address 0x53c0 to address 0x53e7). The correspondence between memory bits and COM/SEG pins varies depending on the conditions selected, as follows.
  • Page 253 Display area 1 (DSPAR = 1) COM2 COM1 COM3 COM0 SEGREV = 1 SEGREV = 0 Figure 23. 5.2 S1C17624/622 Display Memory Map (1/4 duty) Address COMREV = 1 COMREV = 0 COM0 COM2 Display area 0 (DSPAR = 0) COM1 COM1...
  • Page 254 – – Unused area (general-purpose memory) – – – – SEGREV = 1 SEGREV = 0 Figure 23. 5.5 S1C17624/622 Display Memory Map (Static Drive) Address COMREV = 1 COMREV = 0 COM0 COM7 COM1 COM6 Unused COM2 COM5 area...
  • Page 255 Display area 1 (DSPAR = 1) COM0 COM0 – – Unused area (general-purpose memory) – – – – SEGREV = 1 SEGREV = 0 Figure 23. 5.10 S1C17604/602/621 Display Memory Map (Static Drive) Seiko epson Corporation 23-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 256 Setting DSPREV/LCD_DCTL register to 0 inverts the display; setting to 1 returns the display to normal status. Note that the display will not be inverted if “All off” is selected using DSPC[1:0]. The display will be inverted when “All on” is selected. Seiko epson Corporation 23-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 257 LCD clock enable 1 Enable 0 Disable D[7:5] Reserved D[4:2] lCKDV[2:0]: lCD Clock Division Ratio Select Bits Selects the division ratio when HSCLK (IOSC or OSC3) is selected as the LCD clock source. Seiko epson Corporation 23-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 258 COMREV is set to 0, memory bits are assigned to COM pins in descending order. (See Figures 23.5.1 to 23.5.10.) DSPaR: Display Memory area Control Bit Selects the display area. 1 (R/W): Display area 1 0 (R/W): Display area 0 (default) Seiko epson Corporation 23-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 259 8.4 LCD Contrast Adjustment lC[3:0] Contrast High (dark) ↑ ↓ Low (light) (Default: 0x7) LC[3:0] is set to 0x7 after an initial reset. Initialization via software is required to achieve the required contrast. Seiko epson Corporation 23-16 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 260 Setting LFROUT 1 outputs the frame signal generated by the LCD module from the LFRO pin. Setting it to 0 stops output and the LFRO pin goes a low level. D[4:3] Reserved D[2:0] lDuTY[2:0]: lCD Duty Select Bits Selects the drive duty. Seiko epson Corporation 23-17 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 261 23 lCD DRiVeR (lCD) Table 23. 8.7 Drive Duty Settings (S1C17624/622) Max. number of lDuTY[2:0] Duty Valid COM pins Valid SeG pins display segments 0x7–0x5 Reserved – – – COM0 to COM7 SEG0 to SEG51 416 segments COM0 to COM3...

  • Page 262: Adclk Adclk Adclk

    24 a/D COnVeRTeR (aDC10) A/D Converter (ADC10) 24.1 aDC10 Module Overview The S1C17624/604/622/602/621 includes an A/D converter (ADC10) that converts analog input signals into 10-bit digital values. The following shows the features of the ADC10 module: • Conversion method: Successive approximation type •...
  • Page 263 The A/D conversion is generated by dividing PCLK. The division ratio can be selected from the 15 types shown in Table 24.3.1.1 using ADDF[3:0]/ADC_DIV register. note: For the A/D conversion clock frequency range that can be used for this A/D converter, see “A/D Converter Characteristics” in the “Electrical Characteristics” chapter. Seiko epson Corporation 24-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 264 The A/D converter performs A/D conversion for all analog inputs within the range from the start channel speci- fied by ADCS[2:0]/ADC10_TRG register to the end channel specified by the ADCE[2:0]/ADC10_TRG register once and then stops automatically. Seiko epson Corporation 24-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 265 2 cycles (Default: 0x7) The sampling time must satisfy the acquisition time condition (t , time required for acquiring input voltage). Fig- ure 24.3.5.1 shows an equivalent circuit of the analog input portion. Seiko epson Corporation 24-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 266 The software trigger bit ADCTL functions as an A/D conversion status bit that goes 1 while A/D conversion is un- derway even if it has started by another trigger source. The channel in which conversion is underway can be identi- fied by reading ADICH[2:0]/ADC10_CTL register. Seiko epson Corporation 24-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 267 Conversion AIN0 AIN0 A/D operation AIN0 converted data ADD[15:0] ADCF Clear Conversion result read ADOWE Interrupt request (1) Single channel (AIN0) one-time conversion mode (ADCS = 0, ADCE = 0, ADMS = 0) Seiko epson Corporation 24-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 268 • Conversion data overwrite error interrupt The A/D converter outputs one interrupt signal shared by the two above interrupt causes to the interrupt controller (ITC). Inspect the status flag to determine the interrupt cause occurred. Seiko epson Corporation 24-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 269 STMD = 1 (ADD[5:0] = 0) D[15:0] aDD[15:0]: a/D Converted Data Bits The A/D conversion results are stored. (Default: 0x0) The data alignment in this 16-bit register (conversion result storing mode) can be selected using the STMD/ADC10_TRG register. Seiko epson Corporation 24-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 270 Writing 1 to ADMS sets the A/D converter to continuous conversion mode. In this mode, A/D conver- sions in the range of the channels selected by ADCS[2:0] and ADCE[2:0] are executed continuously until stopped with software. Seiko epson Corporation 24-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 271 Indicates the channel number (0 to 7) currently being A/D-converted. (Default: 0x0 = AIN0) When A/D conversion is performed in multiple channels, read this bit to identify the channel in which conversion is underway. Reserved Seiko epson Corporation 24-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 272 Enables or disables interrupts caused by completion of conversion. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Setting ADCIE to 1 enables conversion completion interrupt requests to the ITC; setting to 0 disables interrupts. D[3:2] Reserved Seiko epson Corporation 24-11 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 273: (New) When Aden Is 0, No Trigger Will Be Accepted

    1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 D[15:4] Reserved D[3:0] aDDF[3:0]: a/D Converter Clock Division Ratio Select Bits Selects a PCLK division ratio to generate the A/D converter clock. Seiko epson Corporation 24-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 274 1/16 (Default: 0x0) note: To use the A/D converter, the clock used in the A/D converter must be supplied by turning on the peripheral module clock (PCLK) output from the clock generator (CLG). Seiko epson Corporation 24-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 275 25.1 RFC Module Overview The S1C17624/604/622/602/621 includes an R/F converter (RFC) module with two conversion channels. It is ca- pable of being used as a CR oscillation type A/D converter. A thermo-hygrometer can easily be implemented by connecting only resistive or capacitive sensors (e.g., thermistor and humidity sensor) and a few passive elements (resistors and capacitors) to the R/F converter.
  • Page 276 Setting RFTCKEN to 1 feeds the clock generated as above to the RFC circuit. If no RFC opera- tion is required, stop the clock to reduce current consumption. note: Be sure to set RFTCKEN to 0 before selecting a clock division ratio. Seiko epson Corporation 25-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 277 SENBx Current passing direction (AC driving) SENAx REFx RFINx : Reference resistor : Resistive sensor (AC bias) : Reference capacitor Figure 25. 4.1.2 Connection Example in AC Oscillation Mode for Measuring Resistive Sensors Seiko epson Corporation 25-3 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 278: Dd Ss

    1 to CONEN/RFC_CTL register enables the continuous oscillation function and CR oscillation will continue until stopped by software. Using this function with the CR oscillation monitoring function helps easily measure the CR oscillation clock frequency. Seiko epson Corporation 25-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 279 (2) Select the channel to perform conversion using CHSEL/RFC_CTL register. Setting CHSEL to 0 (default) selects Ch. 0 and setting 1 selects Ch.1. (3) Set the oscillation mode using SMODE[1:0]/RFC_CTL register. (See Section 25.4.1.) Seiko epson Corporation 25-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 280 6.2.1 Counter Operations During Reference/Sensor Oscillation 25.6.3 Sensor Oscillation Control Perform oscillation with the sensor for the period of time obtained by the time base counter in reference oscillation and count the oscillation clock by the measurement counter. Seiko epson Corporation 25-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 281 • Time base counter overflow error interrupt The RFC module outputs one interrupt signal shared by the five above interrupt causes to the interrupt controller (ITC). Inspect the interrupt flag to determine the interrupt cause occurred. Seiko epson Corporation 25-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 282 RFC Time Base Counter Low Register Time base counter data 0x53aa RFC_TCH RFC Time Base Counter High Register 0x53ac RFC_IMSK RFC Interrupt Mask Register Enables/disables interrupts. 0x53ae RFC_IFLG RFC Interrupt Flag Register Indicates/resets interrupt occurrence status. Seiko epson Corporation 25-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 283 1 Enable 0 Disable D[15:8] Reserved COnen: Continuous Oscillation enable Bit Enables continuous oscillation by disabling the automatic CR oscillation stop function. 1 (R/W): Continuous oscillation enabled 0 (R/W): Continuous oscillation disabled (default) Seiko epson Corporation 25-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 284 Trigger Register (16 bits) SSenB Sensor B oscillation control/status 1 Start/Run 0 Stop (RFC_TRG) SSena Sensor A oscillation control/status 1 Start/Run 0 Stop SReF Reference oscillation control/status 1 Start/Run 0 Stop D[15:3] Reserved Seiko epson Corporation 25-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 285 The measurement counter must be set from the low-order value (MC[15:0]/RFC_MCL register) first. The counter may not be set to the correct value if the high-order value (MC[23:16]/RFC_ MCH register) is written first. Seiko epson Corporation 25-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 286 Enables or disables sensor A oscillation completion interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) eReFie: Reference Oscillation Completion interrupt enable Bit Enables or disables reference oscillation completion interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Seiko epson Corporation 25-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 287 1 (W): Flag is reset 0 (W): Ignored EREFIF is set to 1 when the measurement counter overflows and a reference oscillation is completed normally. EREFIF is reset to 0 by writing 1. Seiko epson Corporation 25-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 288 Supply Voltage Detector (SVD) 26.1 SVD Module Overview The S1C17624/604/622/602/621 includes an SVD (supply voltage detector) circuit to monitor the power voltage supplied to the V pin. It generates an interrupt when the power supply voltage drops below the detection level set with software.
  • Page 289 SVD module to 1. Once set, SVDIF is not reset even if the power supply voltage subsequently returns to a value exceeding the comparison voltage. SVDIF is reset to 0 by writing 1. Seiko epson Corporation 26-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 290 Register name address name Function Setting init. R/W Remarks SVD enable 0x5100 D7–1 – reserved – – – 0 when being read. Register (8 bits) SVDen SVD enable 1 Enable 0 Disable (SVD_en) D[7:1] Reserved Seiko epson Corporation 26-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 291 Reserved (Default: 0x0) The SVD circuit compares the power supply voltage (V ) against the comparison voltage set by SVDC[3:0], and outputs results indicating whether the power supply voltage exceeds this comparison voltage. Seiko epson Corporation 26-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 292 No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored SVDIF is set to 1 when a power supply voltage drop is detected. SVDIF is reset to 0 by writing 1. Seiko epson Corporation 26-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 293 The start address for this debugging work area can be read from the DBRAM register (0xffff90). Debugging tools Debugging involves connecting ICDmini (S5U1C17001H) to the S1C17624/604/622/602/621 debug pins and inputting the debug instruction from the debugger on the personal computer.
  • Page 294 In this process, the S1C17 Core is designed to branch to address 0xfffc00. In addition to this branching destination, the S1C17624/604/622/602/621 also allows designation of address 0x0 (beginning address of the internal RAM) as the branching destination when debug mode is activated. The branching destination address is selected using DBADR/MISC_IRAMSZ register.
  • Page 295 0 when being read. D6–4 – reserved – – – 0x1 when being read. (S1C17624/604) – reserved – – – 0 when being read. D2–0 iRaMSZ[2:0] IRAM size select IRAMSZ[2:0] Size 0x1 R/W Other reserved Seiko epson Corporation 27-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 296 S1C17602: 0x0fc0 (S1C17624/604/ 602) D[31:24] not used (Fixed at 0) D[23:0] DBRaM[23:0]: Debug RaM Base address Bits (S1C17624/604/602) Read-only register containing the beginning address of the debugging work area (64 bytes). D[23:0] not used (undefined) (S1C17622/621) Seiko epson Corporation 27-4...
  • Page 297 If this bit is set to 1, the instruction fetch address and the value set in the IBAR0 register are compared. If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed. Seiko epson Corporation 27-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 298 D23–0 iBaR4[23:0] Instruction break address #4 0x0 to 0xffffff 0x0 R/W Register 4 IBAR423 = MSB (iBaR4) IBAR40 = LSB D[31:24] Reserved D[23:0] iBaR4[23:0]: instruction Break address #4 Bits Sets instruction break address #4. (Default: 0x000000) Seiko epson Corporation 27-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 299 28 MulTiPlieR/DiViDeR (COPRO) Multiplier/Divider (COPRO) 28.1 Overview The S1C17624/604/622/602/621 has an embedded coprocessor that provides multiplier/divider functions. The following shows the features of the multiplier/divider: • Multiplication: Supports signed/unsigned multiplications. (16 bits × 16 bits = 32 bits) Can be executed in 1 cycle.
  • Page 300 CPU registers. Another one-half should be read by setting the multiplier/divider into operation result read mode. Argument 2 Argument 1 16 bits 32 bits Operation S1C17 Core result Operation result register Selector Coprocessor output (16 bits) Flag output Figure 28. 3.1 Data Path in Multiplication Mode Seiko epson Corporation 28-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 301 %rd,imm7 res[31:0] ← %rd ÷ %rs 0x018 ld.ca %rd,%rs %rd ← res[31:16] (residue) or 0x19 res[31:0] ← %rd ÷ imm7/16 (ext imm9) %rd ← res[31:16] (residue) ld.ca %rd,imm7 res: operation result register Seiko epson Corporation 28-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 302 When repeating the MAC operation without operation result read mode inserted, send multiplicand and multiplier data for number of required times. In this case it is not necessary to set the MAC mode every time. Seiko epson Corporation 28-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 303 The overflow (V) flag that has been set will be cleared when an overflow has not been occurred during execu- tion of the “ld.ca” instruction for MAC operation or when the “ld.ca” or “ld.cf” instruction is executed in an operation mode other than operation result read mode. Seiko epson Corporation 28-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 304 (CVZN) ← 0b0000 This operation mode does not 0x03 ld.ca %rd,%rs affect the operation result reg- ld.ca %rd,imm7 %rd ← res[15:0] ister. %rd ← res[31:16] 0x13 ld.ca %rd,%rs ld.ca %rd,imm7 %rd ← res[31:16] res: operation result register Seiko epson Corporation 28-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 305 Capacitor between CA and CB *1 µF *1 The capacitors are not required when LCD driver is not used. In this case, leave the V to V , CA, and CB pins open. Seiko epson Corporation 29-1 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 306: Dd = 1.8 To 3.6V

    29 eleCTRiCal ChaRaCTeRiSTiCS 29.3 Current Consumption S1C17624/604/622 current consumption Unless otherwise specified: V = 1.8 to 3.6V, V = 0V, Ta = 25°C, C = 0.1µF, PCKEN[1:0] = 0x3 (ON), VD1MD = 0, FLCYC[2:0] = 0x4 (1 cycle), CCLKGR[1:0] = 0x0 (gear ratio 1/1)
  • Page 307 OSC1 = 32.768kHz crystal, IOSC = OFF, OSC3 = OFF, PCKEN[1:0] = 0x3, CCLKGR[1:0] = 0x0, Typ. value VD1MD = 1 VD1MD = 1 VD1MD = 0 VD1MD = 0 Ta [°C] Ta [°C] Seiko epson Corporation 29-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 308 2500 2000 2000 1500 1500 1000 1000 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 [MHz] [MHz] OSC3 OSC3 Seiko epson Corporation 29-4 S1C17624/604/622/602/621 TeChniCal Manual...

  • Page 309: Ss = 0V, Ta = 25°C, R

    Max. unit Oscillation start time Built-in drain capacitance In case of the chip *1 Crystal resonator = MC-146: manufactured by EPSON TOYOCOM (R = 65kW Max., C = 12.5pF) OSC3 crystal oscillation Unless otherwise specified: V = 1.8 to 3.6V, V = 0V, Ta = 25°C, R...
  • Page 310 High level Schmitt input threshold voltage #RESET 0.5V 0.9V Low level Schmitt input threshold voltage #RESET 0.1V 0.5V High level Schmitt input threshold voltage 0.5V 0.9V Low level Schmitt input threshold voltage 0.1V 0.5V Hysteresis voltage Pxx, #RESET Seiko epson Corporation 29-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 311 Schmitt input threshold voltage high-level output current characteristic low-level output current characteristic Ta = 70°C, Max. value Ta = 70°C, Min. value –V = 3.6 V = 1.8 V = 1.8 V = 3.6 V Seiko epson Corporation 29-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 312 = 1.8 to 3.6V, V = 0V, Ta = -25 to 70°C item Symbol Min. Typ. Max. unit SPICLKx cycle time SPCK SDIx setup time SDIx hold time SDOx output delay time 29.8 C Characteristics SCLx SDAx Seiko epson Corporation 29-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 313 1.04 LC[3:0] = 0x8 2.96 LC[3:0] = 0x9 3.02 LC[3:0] = 0xa 3.08 LC[3:0] = 0xb 3.14 LC[3:0] = 0xc 3.19 LC[3:0] = 0xd 3.25 LC[3:0] = 0xe 3.31 LC[3:0] = 0xf 3.37 Seiko epson Corporation 29-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 314 SEGH SEGxx, COMxx, V = 0.1V µA SEGL SEGL S1C17624/604/622 lCD driver circuit current consumption Unless otherwise specified: V = 1.8 to 3.6V, V = 0V, Ta = 25°C, C –C = 0.1µF, No LCD panel load, PCKEN[1:0] = 0x0 (OFF), FLCYC[2:0] = 0x4 (1 cycle), CCLKGR[1:0] = 0x0 (gear ratio 1/1)
  • Page 315 = 3.6V, sampling rate = 100ksps µA *1 This value is added to the current consumption in HALT mode (only when PCKEN[1:0] = 0x3 (ON)) or current consumption during execution when the A/D converter is active. Seiko epson Corporation 29-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 316 = 1000pF, Ta = 25°C, Typ. value = 100kW, Ta = 25°C, Typ. value 10000 1000 1000 IC deviation IC deviation = 1.8 V = 3.6 V = 1.8 V = 3.6 V 1000 10000 1000 10000 [kW] [pF] Seiko epson Corporation 29-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 317 = 1.8 V = 3.6 V = 3.6 V Ta [°C] Ta [°C] S1C17624/604/622 R/F converter current consumption Unless otherwise specified: V = 3.6V, V = 0V, Ta = 25°C, PCKEN[1:0] = 0x0 (OFF), C = 1000pF, R = 100kW,...
  • Page 318 *2 This time is required to obtain stable detection results after SVDC[3:0] is altered. SVD voltage-ambient temperature characteristic SVDC[3:0] = 0xf, Typ. value 1.05V 1.04V 1.03V 1.02V 1.01V 1.00V 0.99V 0.98V 0.97V 0.96V 0.95V Ta [°C] Seiko epson Corporation 29-14 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 319 *1 This value is added to the current consumption during execution when the Flash memory is being erased in self-programming mode. *2 This value is added to the current consumption during execution when the Flash memory is being programmed in self-program- ming mode. Seiko epson Corporation 29-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 320 30 BaSiC eXTeRnal COnneCTiOn DiaGRaM Basic External Connection Diagram LCD panel 52 SEG × 8 COM (S1C17624/622) 36 SEG × 8 COM (S1C17604/602/621) P01/REMI P02/EXCL0 P03/#ADTRG P04/SPICLK0 P05/SDO0 1.8–3.6 V P06/SDI0 P07/#SPISS0 P10/SCLK0 #TEST(S1C17604/602/621) P11/SOUT0 P12/SIN0 P13/EXCL1/AIN7 OSC1 P14/EXCL2/AIN6 X'tal1...
  • Page 321 31 PaCKaGe Package TQFP15-128pin package (Unit: mm) INDEX 0.13 /0.23 0.09 /0.2 0° /10° /0.75 TQFP14-100pin package (Unit: mm) ±0.4 ±0.1 INDEX +0.10 0.16 –0.05 +0.05 0.125 –0.025 0° 10° ±0.2 Seiko epson Corporation 31-1 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 322 – – 0.23 – – – 0.26 – 0.36 – – 0.08 – – – – A1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 – – Seiko epson Corporation 31-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 323 C Master Control Register Controls the I C master operation and indicates transfer status. 0x4344 I2CM_DAT C Master Data Register Transmit/receive data 0x4346 I2CM_ICTL C Master Interrupt Control Register Controls the I C master interrupt. Seiko epson Corporation aP-a-1 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 324 RTC Day Register Day counter data 0x5148 RTC_MONTH RTC Month Register Month counter data 0x5149 RTC_YEAR RTC Year Register Year counter data 0x514a RTC_WEEK RTC Days of Week Register Days of week counter data Seiko epson Corporation aP-a-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 325 0x524a P4_IEN P4 Port Input Enable Register Enables P4 port inputs. 0x5250 P5_IN P5 Port Input Data Register P5 port input data (S1C17624/622) 0x5251 P5_OUT P5 Port Output Data Register P5 port output data (S1C17624/622) 0x5252 P5_OEN P5 Port Output Enable Register Enables P5 port outputs.
  • Page 326 IBAR4 Instruction Break Address Register 4 Sets Instruction break address #4. note: Addresses marked as “Reserved” or unused peripheral circuit areas not marked in the table must not be accessed by application programs. Seiko epson Corporation aP-a-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 327 Parity enable 1 With parity 0 No parity Parity mode select 1 Odd 0 Even STPB Stop bit select 1 2 bits 0 1 bit SSCK Input clock select 1 External 0 Internal Seiko epson Corporation aP-a-5 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 328 Control Register D7–1 – reserved – – – 0 when being read. (T8F_inT0) T8FiF T8F interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. interrupt interrupt not occurred occurred Seiko epson Corporation aP-a-6 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 329 (16 bits) TR15 = MSB Register TR0 = LSB (T16_TR1) T16 Ch.1 0x4244 D15–0 TC[15:0] Counter data 0x0 to 0xffff 0xffff Counter Data (16 bits) TC15 = MSB Register TC0 = LSB (T16_TC1) Seiko epson Corporation aP-a-7 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 330 Control Register D7–1 – reserved – – – 0 when being read. (T16_inT2) T16iF T16 interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. interrupt interrupt not occurred occurred Seiko epson Corporation aP-a-8 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 331 D10–8 ilV11[2:0] T16 Ch.2 interrupt level 0 to 7 0x0 R/W (iTC_lV5) D7–3 – reserved – – – 0 when being read. D2–0 ilV10[2:0] T16 Ch.1 interrupt level 0 to 7 0x0 R/W Seiko epson Corporation aP-a-9 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 332 0x4346 D15–2 – reserved – – – 0 when being read. interrupt (16 bits) RinTe Receive interrupt enable 1 Enable 0 Disable Control Register TinTe Transmit interrupt enable 1 Enable 0 Disable (i2CM_iCTl) Seiko epson Corporation aP-a-10 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 333 0 when being read. Timer Control (8 bits) SWTRST Stopwatch timer reset 1 Reset 0 Ignored Register D3–1 – reserved – – – (SWT_CTl) SWTRun Stopwatch timer run/stop control 1 Run 0 Stop Seiko epson Corporation aP-a-11 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 334 Not allowed Not allowed Disable CClK Control 0x5081 D7–2 – reserved – – – 0 when being read. Register (8 bits) D1–0 CClKGR[1:0] CCLK clock gear ratio select CCLKGR[1:0] Gear ratio 0x0 R/W (ClG_CClK) Seiko epson Corporation aP-a-12 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 335 1 One shot 0 Repeat T8ORun Timer run/stop control 1 Run 0 Stop T8OSC1 0x50c1 D7–0 T8OCnT[7:0] Timer counter data 0x0 to 0xff Counter Data (8 bits) T8OCNT7 = MSB Register T8OCNT0 = LSB (T8OSC1_CnT) Seiko epson Corporation aP-a-13 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 336 D3–1 – reserved – – – 0 when being read. VD1MD Flash erase/programming mode 1 Flash (2.5 V) 0 Norm.(1.8 V) 0x506e, 0x5140–0x514a Real-time Clock (S1C17624/604) Register name address name Function Setting init. R/W Remarks RTC Clock 0x506e D7–1 –...
  • Page 337 D7–0 P0Oen[7:0] P0[7:0] port output enable 1 Enable 0 Disable Output enable (8 bits) Register (P0_Oen) P0 Port Pull-up 0x5203 D7–0 P0Pu[7:0] P0[7:0] port pull-up enable 1 Enable 0 Disable Control Register (8 bits) (0xff) (P0_Pu) Seiko epson Corporation aP-a-15 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 338 Select Register (P1_eDGe) P1 Port 0x5217 D7–0 P1iF[7:0] P1[7:0] port interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. interrupt Flag (8 bits) interrupt interrupt not Register occurred occurred (P1_iFlG) Seiko epson Corporation aP-a-16 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 339 R/W D[7:4] =reserved in Data Register (8 bits) S1C17604/602/621 (P4_OuT) P4 Port 0x5242 D7–0 P4Oen[7:0] P4[7:0] port output enable 1 Enable 0 Disable R/W D[7:4] =reserved in Output enable (8 bits) S1C17604/602/621 Register (P4_Oen) Seiko epson Corporation aP-a-17 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 340 P06MUX[1:0] Function 0x0 R/W reserved reserved SDI0 D3–2 P05MuX[1:0] P05 port function select P05MUX[1:0] Function 0x0 R/W reserved reserved SDO0 D1–0 P04MuX[1:0] P04 port function select P04MUX[1:0] Function 0x0 R/W reserved reserved SPICLK0 Seiko epson Corporation aP-a-18 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 341 P22MUX[1:0] Function 0x0 R/W reserved reserved AIN0 D3–2 P21MuX[1:0] P21 port function select P21MUX[1:0] Function 0x0 R/W reserved reserved AIN1 D1–0 P20MuX[1:0] P20 port function select P20MUX[1:0] Function 0x0 R/W reserved reserved AIN2 Seiko epson Corporation aP-a-19 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 342 (Set EXCL5S to 0 in TOUT3 S1C17624.) P36/EXCL5 D3–2 P35MuX[1:0] P35 port function select P35MUX[1:0] Function 0x0 R/W reserved #BFR FOUT1 D1–0 P34MuX[1:0] P34 port function select P34MUX[1:0] Function 0x0 R/W TOUTB6/CAPB6: TOUTB6/CAPB6 S1C17624/604 only SDA0 SDA1 Seiko epson Corporation aP-a-20 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 343 (Set EXCL6S to 1.) SCLK1 P50/EXCL6 P5[6:4] Port 0x52ab eXCl6S EXCL6 input select 1 P50/EXCL6 0 P37/EXCL6 R/W S1C17624 only Function Select (8 bits) eXCl5S EXCL5 input select 1 P47/EXCL5 0 P36/EXCL5 Register D5–4 P56MuX[1:0] P56 port function select P56MUX[1:0]...
  • Page 344 2 cycles OSC1 Peripheral 0x5322 D15–1 – reserved – – – 0 when being read. Control Register (16 bits) O1DBG Run/stop select in debug mode 1 Run 0 Stop (MiSC_OSC1) (except PCLK peripheral circuits) Seiko epson Corporation aP-a-22 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 345 PSRV PSR overflow (V) flag 1 1 (set) 0 0 (cleared) PSRZ PSR zero (Z) flag 1 1 (set) 0 0 (cleared) PSRn PSR negative (N) flag 1 1 (set) 0 0 (cleared) Seiko epson Corporation aP-a-23 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 346 – – – 0 when being read. D2–0 aDST[2:0] Sampling time setting ADST[2:0] Sampling time 0x7 R/W 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles Seiko epson Corporation aP-a-24 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 347 Register (RFC_TCl) RFC Time Base 0x53aa D15–8 – reserved – – – 0 when being read. Counter high (16 bits) D7–0 TC[23:16] Time base counter high-order 0x0–0xff 0x0 R/W Register 8-bit data (RFC_TCh) Seiko epson Corporation aP-a-25 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 348 Sensor B oscillation completion interrupt flag eSenaiF Sensor A oscillation completion interrupt flag eReFiF Reference oscillation completion interrupt flag 0x5068, 0x5400–0x540c 16-bit PWM Timer (T16a2) Ch.0 (S1C17624/604) Register name address name Function Setting init. R/W Remarks T16a Clock 0x5068 D7–4 ClKDiV...
  • Page 349 Capture Ch.0 CaPaOWiF Capture A overwrite interrupt flag occurred occurred interrupt Flag CaPBiF Capture B interrupt flag Register CaPaiF Capture A interrupt flag (T16a_iFlG0) CBiF Compare B interrupt flag CaiF Compare A interrupt flag Seiko epson Corporation aP-a-27 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 350 OF i/O ReGiSTeRS 0x5069, 0x5420–0x542c 16-bit PWM Timer (T16a2) Ch.1 (S1C17624/604) Register name address name Function Setting init. R/W Remarks T16a Clock 0x5069 D7–4 ClKDiV Clock division ratio select Division ratio 0x0 R/W Control Register [3:0] (8 bits)
  • Page 351 D31–24 – reserved – – – 0 when being read. Break address (32 bits) D23–0 iBaR4[23:0] Instruction break address #4 0x0 to 0xffffff 0x0 R/W Register 4 IBAR423 = MSB (iBaR4) IBAR40 = LSB Seiko epson Corporation aP-a-29 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 352 • 8-bit timer (T8F) • UART • SPI • I C master (I2CM) • I C slave (I2CS) • 16-bit PWM timer (T16E) • I/O port (P) • MISC register (MISC) • Power generator (VD1) Seiko epson Corporation aP-B-1 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 353 HALT and SLEEP mode cancelation methods (CPU startup method) 1. Startup by port Started up by an I/O port or debug interrupt (ICD forced break). 2. Startup by RTC (S1C17624/604) Started up by an RTC interrupt. 3. Startup by OSC1 peripheral circuit Started up by a clock timer, stopwatch timer, 8-bit OSC1 timer, or watchdog timer interrupt.
  • Page 354 • If no LCD display is being used, turn off the LCD driver. Power supply voltage detection (SVD) circuit • Operating the SVD circuit will increase current consumption. Turn off power supply voltage detection unless it is required. Seiko epson Corporation aP-B-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 355 • Components such as capacitors and resistors connected to the #RESET pin should have the shortest connec- tions possible to prevent noise-induced resets. Seiko epson Corporation aP-C-1 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 356 Perform the inspections described above using an oscilloscope capable of observing waveforms of at least 200 MHz. It may not be possible to observe high-speed noise events with a low-speed oscilloscope. Seiko epson Corporation aP-C-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 357 If the LCD driver is not used, these pins should be left open. The control registers should be fixed at the initial status (display off). The unused SEGx and COMx pins that are not required to connect should be left open even if the LCD driver is used. Seiko epson Corporation aP-C-3 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 358 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko epson Corporation aP-C-4 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 359 ; ----- Memory controller ---------------- Xld.a %r1, 0x5320 ; MISC register base address ; FLASHC Xld.a %r0, 0x04 ; 1 cycle access ...(5) ld.b [%r1], %r0 ; [0x5320] <= 0x04 ; ===== Main routine ========================================= Seiko epson Corporation aP-D-1 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 360 (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash controller access cycles. Can be set to 1-cycle access for S1C17624/604/622/602/621. (See the “Memory Map” chapter.) Seiko epson Corporation...
  • Page 361 Optimum oscillator component values vary depending on operating conditions such as a printed circuit board and power voltage. Please ask the manufacturer to evaluate the resonator mounted on the circuit board. Recommended Resonators for S1C17624/604/622 (1) OSC1 crystal resonator Oscillation frequency [khz]...
  • Page 362 : 10pF) MA-406 (C : 8pF) Ceramic3 CSTCR4M00G53-R0 (15)* (15)* CSTCR4M00G53095-R0 (15)* (15)* CSTLS4M00G53095-B0 (15)* (15)* CSTLS8M00G53095-B0 (15)* (15)* * The values enclosed with ( ) are the built-in capacitances of the resonator. Seiko epson Corporation aP-e-2 S1C17624/604/622/602/621 TeChniCal Manual...
  • Page 363 ReViSiOn hiSTORY Revision History Code no. Page Contents 411914900 New establishment 411914901 Second Notice cover (Old) No description (New) This product uses SuperFlash ® technology licensed from Silicon Storage Technology, Inc. Features: Clock generator - Other (Old) • IOSC control for quick-restart processing from SLEEP mode (New) Deleted 1-8, 1-11 Pad configuration diagram: Chip (S1C17604/S1C17622)

  • Page 364: Table Of Contents

    ReViSiOn hiSTORY Code no. Page Contents 411914901 18-4, 18-5 UART: Data reception control (Old) (2) RDRY = 1, RD2B = 0 ... This clears the data inside the buffer and resets the RDRY flag..(3) RDRY = 1, RD2B = 1 ...
  • Page 365 = 1.8 to 3.6V, ... (New) Unless otherwise specified: V = 2.5 to 3.6V, ... 29-13 Electrical characteristics: S1C17624/604/622 R/F converter current consumption, S1C17602/621 R/F con- verter current consumption (Old) Unless otherwise specified: ... PCKEN[1:0] = 0x3 (ON), ... R = 100kW (New) Unless otherwise specified: ...
  • Page 366 (S1C17621) to 1. If it is set to 0, the program cannot be booted. (New) Notes: ... • Be sure to set D0 of address 0x27ffe (S1C17624/604/622) or 0x17ffe (S1C17602/621) to 1. If it is set to 0, the program cannot be booted.
  • Page 367 411914803 Memory map: Embedded RAM (Old) The S1C17624/604 enables the RAM size used to apply restrictions to 8KB, 4KB, or 2KB. The S1C17602 enables the RAM size used to apply restrictions to 4KB or 2KB. For example, when using the S1C17624/604/602 to develop an application for a built-in ROM model ...
  • Page 368 KOnG lTD. Unit 715-723, 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 ePSOn TaiWan TeChnOlOGY & TRaDinG lTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 Fax: +886-2-8786-6660 ePSOn SinGaPORe PTe., lTD.

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