Page 1 ADVANCED AND EVER ADVANCING Preliminary -M32170-U-0003 Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/E Series 32170 Group M32170F6VFP/WG M32170F4VFP/WG M32170F3VFP/WG User’s Manual 2000-03-17 Ver0.10 NOTE Information in this manual may be changed without prior notice. Mitsubishi Electric Corporation Mitsubishi Electric Semiconductor Systems Corporation...
Page 2 All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore...
Page 3 PREFACE This manual describes the hardware specifica- tions of Mitsubishi’s 32170 group of 32-bit CMOS microcomputers. This manual was created to help you under- stand the hardware specifications of the 32170-group microcomputers so you can take full advantage of the versatile performance ca- pabilities of these microcomputers.
Page 4 How to read internal I/O register tables Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column...
Page 5: Table Of Contents
Contents CHAPTER 1 OVERVIEW 1.1 Outline of the 32170 ..................1-2 1.1.1 M32R Family CPU Core ................1-2 1.1.2 Built-in Multiply-Accumulate Operation Function ........1-3 1.1.3 Built-in Flash Memory and RAM ..............1-3 1.1.4 Built-in Clock Frequency Multiplier ............. 1-4 1.1.5 Built-in Powerful Peripheral Functions ............
Page 6 CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space ................3-2 3.2 Operation Modes ....................3-6 3.3 Internal ROM Area and Extended External Area ..........3-8 3.3.1 Internal ROM Area ..................3-8 3.3.2 Extended External Area ................3-8 3.4 Internal RAM Area and SFR Area ..............3-9 3.4.1 Internal RAM Area ..................
Page 7 4.9.3 External Interrupt (EI) ................4-18 4.10 Trap Processing .................... 4-20 4.10.1 Trap (TRAP) ................... 4-20 4.11 EIT Priority Levels ..................4-22 4.12 Example of EIT Processing ................4-23 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of Interrupt Controller (ICU) ..............5-2 5.2 Interrupt Sources of Internal Peripheral I/Os ..........
Page 8 6.4.4 Virtual Flash L Bank Registers ..............6-14 6.4.5 Virtual Flash S Bank Registers ..............6-15 6.5 Programming of the Internal Flash Memory ..........6-16 6.5.1 Outline of Programming Flash Memory ............ 6-16 6.5.2 Controlling Operation Mode during Programming Flash ......6-22 6.5.3 Programming Procedure to the Internal Flash Memory ......
Page 9 8.4 Port Peripheral Circuits .................. 8-31 CHAPTER 9 DMAC 9.1 Outline of the DMAC ..................9-2 9.2 DMAC Related Registers .................. 9-4 9.2.1 DMA Channel Control Register ..............9-6 9.2.2 DMA Software Request Generation Registers ......... 9-17 9.2.3 DMA Source Address Registers ............... 9-18 9.2.4 DMA Destination Address Registers ............
Page 10 10.2.4 Input Processing Control Unit ............... 10-18 10.2.5 Output Flip-Flop Control Unit ..............10-26 10.2.6 Interrupt Control Unit ................10-37 10.3 TOP (Output-related 16-bit Timer) ............. 10-63 10.3.1 Outline of TOP ..................10-63 10.3.2 Outline of Each Mode of TOP ............... 10-65 10.3.3 TOP Related Register Map ..............
Page 11 10.5.3 TMS Related Register Map ..............10-142 10.5.4 TMS Control Registers ............... 10-143 10.5.5 TMS Counters (TMS0CT, TMS1CT) ..........10-145 10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0) ....... 10-146 10.5.7 Operation of TMS Measure Input ............10-147 10.6 TML (Input-related 32-bit Timer) .............. 10-149 10.6.1 Outline of TML ..................
Page 12 10.8.13 Operation in TOD Continuous Output Mode (Without Correction Function) . 10-201 10.9 TOM (Output-related 16-bit Timer) ............10-203 10.9.1 Outline of TOM ................... 10-203 10.9.2 Outline of Each Mode of TOM ............10-205 10.9.3 TOM Related Register Map ..............10-207 10.9.4 TOM Control Registers ...............
Page 13 11.3 Functional Description of A-D Converters ..........11-41 11.3.1 How to Find Along Input Voltages ............11-41 11.3.2 A-D Conversion by Successive Approximation Method ....... 11-42 11.3.3 Comparator Operation ................11-44 11.3.4 Calculation of the A-D Conversion Time ..........11-45 11.3.5 Definition of the A-D Conversion Accuracy ...........
Page 14 12.4.4 About Successive Reception ..............12-39 12.4.5 Flags Indicating the Status of CSIO Receive Operation ....... 12-40 12.4.6 Typical CSIO Receive Operation ............12-41 12.5 Precautions on Using CSIO Mode ............. 12-43 12.6 Transmit Operation in UART Mode ............12-45 12.6.1 Setting the UART Baud Rate ..............
Page 15 13.2.8 CAN Interrupt Related Registers ............13-22 13.2.9 CAN Mask Registers ................13-30 13.2.10 CAN Message Slot Control Registers ..........13-34 13.2.11 CAN Message Slots ................13-38 13.3 CAN Protocol ....................13-53 13.3.1 CAN Protocol Frame ................13-53 13.4 Initializing the CAN Module ................ 13-56 13.4.1 Initialization of the CAN Module ............
Page 16 14.3.5 Operation of VEI (Interrupt Request) ............ 14-10 14.3.6 Operation of RCV (Recover from Runaway) ........14-11 14.3.7 Method to Set a Specified Address when Using the RTD ....14-12 14.3.8 Resetting the RTD ................14-13 14.4 Typical Connection with the Host ............. 14-14 CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals ............
Page 17 CHAPTER 18 OSCILLATION CIRCUIT 18.1 Oscillator Circuit ................... 18-2 18.1.1 Example of an Oscillator Circuit .............. 18-2 18.1.2 System Clock Output Function ............... 18-3 18.1.3 Oscillation Stabilization Time at Power-on ..........18-4 18.2 Clock Generator Circuit ................18-5 CHAPTER 19 JTAG 19.1 Outline of JTAG .....................
Page 18 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings ................. 21-2 21.2 Recommended Operating Conditions ............21-3 21.3 DC Characteristics ..................21-5 21.3.1 Electrical Characteristics ................ 21-5 21.3.2 Flash Related Electrical Characteristics ..........21-10 21.4 A-D Conversion Characteristics ..............21-11 21.5 AC Characteristics ..................21-12 21.5.1 Timing Requirements ................
Page 19: Chapter 1 Overview
CHAPTER 1 CHAPTER 1 OVERVIEW 1.1 Outline of the 32170 1.2 Block Diagram 1.3 Pin Function 1.4 Pin Layout...
Page 20: M32R Family Cpu Core
OVERVIEW 1.1 Outline of the 32170 1.1 Outline of the 32170 1.1.1 M32R Family CPU Core (1) Based on RISC architecture • The 32170 is a 32-bit RISC single-chip microcomputer which is built around the M32R family CPU core (hereafter referred to as the M32R) and incorporates flash memory, RAM, and various other peripheral functions-all integrated into a single chip.
Page 21: Built-In Multiply-Accumulate Operation Function
OVERVIEW 1.1 Outline of the 32170 1.1.2 Built-in Multiply-Accumulate Operation Function (1) Built-in high-speed multiplier • The M32R incorporates a 32-bit × 16-bit high-speed multiplier which enables it to execute a 32-bit × 32-bit integral multiplication instruction in three cycles (1 cycle = 25 ns when using a 40 MHz internal CPU clock).
Page 22: Built-In Clock Frequency Multiplier
OVERVIEW 1.1 Outline of the 32170 1.1.4 Built-in Clock Frequency Multiplier • The 32170 internally multiplies the input clock signal frequency by 4 and the internal peripheral clock by 2. If the input clock frequency is 10.0 MHz, the CPU clock frequency will be 40 MHz and the internal clock frequency 20 MHz.
Page 23 OVERVIEW 1.1 Outline of the 32170 (4) High-speed serial I/O • The 32170 incorporates 6 channels of serial I/O, which can be set for clock-synchronized serial I/O or UART. • When set for clock-synchronized serial I/O, the data transfer rate is a high 2 Mbits per second. •...
Page 24: Built-In Full-Can Function
OVERVIEW 1.1 Outline of the 32170 1.1.6 Built-in Full-CAN Function • The 32170 contains CAN Specification V2.0B-compliant CAN module, thereby providing 16 message slots. 1.1.7 Built-in Debug Function • The 32170 supports JTAG interface. Boundary scan test can be performed using this JTAG interface.
Page 25: Block Diagram
OVERVIEW 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32170. Features of each block are shown in Tables 1.2.1 through 1.2.3. 32170 Internal bus interface M32R CPU core (max 40MHz) DMAC Multiplier- (10 channels) accumulator (32 X 16 + 56) Multijunction timer...
Page 26 OVERVIEW 1.2 Block Diagram Table 1.2.1 Features of the M32R Family CPU Core Functional Block Features M32R family • Bus specifications CPU core Basic bus cycle: 25 ns (when operating with 40 MHz CPU clock) Logical address space: 4Gbytes, linear Extended external area: Maximum 4 Mbytes External data bus: 16 bits •...
Page 27 OVERVIEW 1.2 Block Diagram Table 1.2.3 Features of Internal Peripheral I/O Functional Block Features • 10-channel DMA • Supports transfer between internal peripheral I/Os and between internal peripheral I/O and internal RAM. • Capable of advanced DMA transfer when operating in combination with internal peripheral I/O •...
Page 28: Pin Function
OVERVIEW 1.3 Pin Function 1.3 Pin Function Figure 1.3.1 shows a pin function diagram of the 32170 in 240QFP package. Figure 1.3.2 shows a pin function diagram of the 32170 in 255FBGA package. Table 1.3.1 explains the function of each pin of the 32170. Table 1.3.2 explains the function of the dedicated debug pins of the 32170 in 255FBGA package.
Page 29 OVERVIEW 1.3 Pin Function P45/CS1 XOUT P44/CS0 Clock VCNT P43/RD Port 4 OSC-VCC P42/BHW/BHE OSC-VSS control P41/BLW/BLE Port 7 P70/BCLK/WR P71/WAIT P72/HREQ Port 7 Reset RESET P73/HACK MOD0 Mode MOD1 P224/A11 (Note2) P225/A12 (Note2) Port 22 P220/CTX Port 2 Address Port 22 Port 3 P221/CRX...
Page 30 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (1/6) Type Pin Name Signal Name Input/Output Function Power VCCE Power supply — Power supply to external I/O ports (5 V). supply VCCI Power supply — Power supply to internal logic (3.3 V). RAM power supply —...
Page 31 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (2/6) Type Pin Name Signal Name Input/Output Function Data DB0-DB15 Data bus Input/Output These pins comprise 16-bit data bus to connect external devices. In write cycles, the valid byte positions to be written on the 16-bit data bus are output as BHW/BHE and BLW/BLE.
Page 32 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (3/6) Type Pin Name Signal Name Input/Output Function VREF0, Reference Input VREF0 is the reference voltage input pin for the A-D0 converter. converter VREF1 voltage input VREF1 is the reference voltage input pin for the A-D1 converter. _____ ADTRG Conversion...
Page 33 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (4/6) Type Pin Name Signal Name Input/Output Function TXD1 Transmit data Output Transmit data output pin for serial I/O channel 1. RXD1 Receive data Input Receive data input pin for serial I/O channel 1. TXD2 Transmit data Output Transmit data output pin for serial I/O channel 2.
Page 34 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (5/6) Type Pin Name Signal Name Input/Output Function Input/ P00 – P07 Input/output Input/output Programmable input/output port. output port 0 port P10 – P17 Input/output Input/output Programmable input/output port. (Note) port 1 P20 –...
Page 35 OVERVIEW 1.3 Pin Function Table 1.3.1 Description of the 32170 Pin Function (6/6) Type Pin Name Signal Name Input/Output Function Input/ P172 Input/output Input/output Programmable input/output port. output – P177 port 17 port P180 Input/output Input/output Programmable input/output port. – P187 port 18 P190 Input/output...
Page 36: Pin Layout
OVERVIEW 1.4 Pin Layout 1.4 Pin Layout Figure 1.4.1 shows a pin layout diagram of the 32170 in 240QFP package. Figure 1.4.2 shows a pin layout diagram of the 32170 in 255FBGA package. Table 1.4.1 lists pin assignments of the 240QFP.
Page 37 OVERVIEW 1.4 Pin Layout Table 1.4.1 Pin Assignments of the 240QFP (1/2) Pin Name Pin Name Pin Name Pin Name AD1IN12 P26 / A29 P87 / SCLKI1 / SCLKO1 AD1IN13 P27 / A30 P180 / TO29 P200 / TXD4 AD1IN14 P00 / DB0 P181 / TO30 P201 / RXD4...
Page 38 OVERVIEW 1.4 Pin Layout Table 1.4.1 Pin Assignments of the 240QFP (2/2) Pin Name Pin Name Pin Name Pin Name P112 / TO2 JTMS P134 / TIN20 P156 / TIN6 P113 / TO3 JTCK P135 / TIN21 P157 / TIN7 P114 / TO4 JTRST P136 / TIN22...
Page 39 OVERVIEW 1.4 Pin Layout P216 P214 P210 P102 P116 TRDATA P112 P77/ P202 P201 TRDATA JTMS VCCE RESET VCCE /TO43 /TO41 /TO37 /TO10 /TO6 /TO2 /TO19 RTDCLK /HACK /SCLK5 /TXD5 /RXD4 P217 P215 P211 P117 TRDATA P113 P76/ P200 TRDATA JTCK MOD0 VCCI...
Page 40 OVERVIEW 1.4 Pin Layout Table 1.4.2 Pin Assignments of the 255FBGA (1/2) Pin Name Pin Name Pin Name Pin Name — AD1IN14 P220 / CTX VCNT ______ AD1IN9 AD1IN13 P47 / A14 _____ AD1IN8 AD1IN4 P46 / A13 OSC-VOC _____ AD1IN6 AD1IN5 P45 / CS1...
Page 41 OVERVIEW 1.4 Pin Layout Table 1.4.2 Pin Assignments of the 255FBGA (2/2) Pin Name Pin Name Pin Name Pin Name P36 / A21 P00 / DB0 P12 / DB10 P16 / DB14 P37 / A22 P01 / DB1 P13 / DB11 VREF0 P20 / A23 P02 / DB2...
Page 42 OVERVIEW 1.4 Pin Layout This is a blank page. 1-24 Ver.0.10...
Page 43: Cpu Registers
CHAPTER 2 CHAPTER 2 2.1 CPU Registers 2.2 General-purpose Registers 2.3 Control Registers 2.4 Accumulator 2.5 Program Counter 2.6 Data Formats...
Page 44 2.1 CPU Registers 2.1 CPU Registers The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. 2.2 General-purpose Registers General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are used to hold data and base addresses.
Page 45: Control Registers
2.3 Control Registers 2.3 Control Registers There are five control registers-Processor Status Word Register (PSW), Condition Bit Register (CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC). Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers. Control Registers Processor status Word Register Condition Bit Register...
Page 46: Processor Status Word Register: Psw (Cr0)
2.3 Control Registers 2.3.1 Processor Status Word Register: PSW (CR0) The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists of a regularly used PSW field and a special BPSW field which is used to save the PSW field when an EIT occurs.
Page 47: Condition Bit Register: Cbr (Cr1)
2.3 Control Registers 2.3.2 Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register is a read-only register (writes to this register by "MVTC"...
Page 48: Accumulator
2.4 Accumulator 2.4 Accumulator The accumulator (ACC) is a 56-bit register used by DSP function instructions. When read out or written to, it is handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When writing, bits 0--7 are ignored. Also, the accumulator is used by the multiplication instruction "MUL." Note that when executing this instruction, the value of the accumulator is destroyed.
Page 49: Data Formats
2.6 Data Formats 2.6 Data Formats 2.6.1 Data Types There are several data types that can be handled by the M32R's instruction set. These include signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by 2's complements.
Page 50: Data Formats
2.6 Data Formats 2.6.2 Data Formats (1) Data formats in register Data sizes in M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign- extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) into word (32-bit) data before being stored in the register.
Page 51 2.6 Data Formats (2) Data formats in memory Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can be located at any address. However, halfword data must be located at halfword boundaries (where the LSB address bit = "0"), and word data must be located at word boundaries (where two LSB address bits = "00").
Page 52 2.6 Data Formats (3) Endian The following shows the generally used endian methods and the M32R family endian. Bit endian Byte endian (H'01) (H'01234567) B'0000001 Big endian H'01 H'23 H'45 H'67 Little endian B'0000001 H'45 H'23 H'01 H'67 Note: Even for bit big endian, H'01 is not B'10000000. Figure 2.6.4 Endian Methods M32R family 7700 family...
Page 53 2.6 Data Formats (4) Transfer instructions • Constant transfer LD24 Rdest, #imm24 imm24 LD24 Rdest, #imm24 Rdest, #imm16 Rdest Rdest, #imm8 SETH Rdest, #imm16 SETH Rdest, #imm16 imm16 Rdest • Register to register transfer Rdest, Rsrc Rdest, Rsrc Rsrc Rdest •...
Page 54 2.6 Data Formats (5) Memory (signed) to register transfer Memory Register • Signed 32 bits label Rdest LD24 Rsrc, #label Rdest, @Rsrc • Signed 16 bits label Rdest LD24 Rsrc, #label Rdest, @Rsrc Check the MSB 0 = positive 1 = negative •...
Page 55 2.6 Data Formats (7) Things to be noted for data transfer Note that in data transfer, data arrangements in registers and those in memory are different. Data in memory Data in register (R0-R15) Word data (32 bits) (R0-R15) Half-word data (16 bits) (R0-R15) Byte data (8 bits) MSB LSB...
Page 56 This is a blank page. 2-14 Ver.0.10...
Page 57: Chapter 3 Address Space
CHAPTER 3 CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space 3.2 Operation Modes 3.3 Internal ROM Area and Extended External Area 3.4 Internal RAM Area and SFR Area 3.5 EIT Vector Entry 3.6 ICU Vector Table 3.7 Note about Address Space...
Page 58: Internal Rom Area
ADDRESS SPACE 3.1 Outline of Address Space 3.1 Outline of Address Space The M32R's logical addresses are always handled in 32 bits, providing 4 Gbytes of linear ad- dress space. The M32R/E's address space consists of the following: (1) User space •...
Page 59 ADDRESS SPACE 3.1 Outline of Address Space Extended external area EIT vector entry (4 Mbytes) Logical address H'0000 0000 H'0000 0000 Internal ROM area (768 Kbytes) (16 Mbytes) (Note 1) H'000B FFFF Reserved area (256 Kbytes) H'000F FFFF H'0010 0000 CS0 area...
Page 60 ADDRESS SPACE 3.1 Outline of Address Space Extended external area EIT vector entry (4 Mbytes) Logical address H'0000 0000 H'0000 0000 Internal ROM area (512 Kbytes) (16 Mbytes) (Note 1) H'0007 FFFF Reserved area (512 Kbytes) H'000F FFFF H'0010 0000 CS0 area...
Page 61 ADDRESS SPACE 3.1 Outline of Address Space Extended external area EIT vector entry (4 Mbytes) Logical address H'0000 0000 H'0000 0000 Internal ROM area (384 Kbytes) (16 Mbytes) (Note 1) H'0005 FFFF Reserved area (640 Kbytes) H'000F FFFF H'0010 0000 CS0 area...
Page 62 ADDRESS SPACE 3.2 Operation Modes 3.2 Operation Modes The 32170 is placed in one of the following modes by setting its operation mode (using MOD0 and MOD1 pins). For details about the mode used to rewrite the internal flash memory, refer to Section 6.5, "Programming of Internal Flash Memory."...
Page 63 ADDRESS SPACE 3.2 Operation Modes Non-CS0 area H'0000 0000 Internal ROM Internal ROM area area (512 Kbytes) (512 Kbytes) H'0007 FFFF H'0008 0000 Reserved area (512 Kbytes) CS0 area H'000F FFFF (2 Mbytes) H'0010 0000 CS0 area (1 Mbyte) H'001F FFFF H'0020 0000 CS1 area CS1 area...
Page 64 ADDRESS SPACE 3.3 Internal ROM/Extended External Area 3.3 Internal ROM Area and Extended External Area The 8 Mbyte area at addresses H'0000 0000 to H'007F FFFF in the user space accommodates the internal ROM and extended external areas. Of this, a 4 Mbytes of address space from H'0000 0000 to H'0003 FFFF is the area that the user can actually use.
Page 65: Internal Ram Area And Sfr Area
ADDRESS SPACE 3.4 Internal ROM/SFR Area 3.4 Internal RAM Area and SFR Area The 8 Mbyte area at addresses H'0080 0000 to H'00FF FFFF in the user space accommodates the internal RAM area and Special Function Register (SFR) area. Of this, a 128 Kbytes of address space from H'0080 0000 to H'0081 FFFF is the area that the user can actually use.
Page 66 ADDRESS SPACE 3.4 Internal ROM/SFR Area H'0080 0000 SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 Pseudo-flash emulation areas separated in units of Internal RAM 8 Kbytes or 4 Kbytes can (32 Kbytes) be allocated here. For details, refer to Section 6.7. H'0080 BFFF Figure 3.4.2 Internal RAM Area and Special Function Register (SFR) Area of the M32170F4 and M32170F3...
Page 67 ADDRESS SPACE 3.4 Internal ROM/SFR Area +0 address +1 address +0 address +1 address H'0080 0000 H'0080 078C MJT (TID0) H'0080 078E Multijunction timer H'0080 0790 Interrupt (MJT) controller (ICU) MJT (TOD0) H'0080 07DE H'0080 007E H'0080 07E0 H'0080 0080 A-D0 converter Flash control H'0080 00EE...
Page 68 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 H'0080 0004 Interrupt Mask Register (IMASK) H'0080 0006 SBI Control Register (SBICR) TML1 Input Interrupt Control Register (ITML1CR) H'0080 0060 CAN0 Transmit/Receive &...
Page 69 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 00D2 8-bit A-D0 Data Register 1 (AD08DT1) H'0080 00D4 8-bit A-D0 Data Register 2 (AD08DT2) H'0080 00D6 8-bit A-D0 Data Register 3 (AD08DT3) H'0080 00D8 8-bit A-D0 Data Register 4 (AD08DT4) H'0080 00DA 8-bit A-D0 Data Register 5 (AD08DT5) H'0080 00DC...
Page 70 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0216 TIN Input Processing Control Register 2 (TINCR2) H'0080 0218 TIN Input Processing Control Register 3 (TINCR3) H'0080 021A TIN Input Processing Control Register 4 (TINCR4) H'0080 021C H'0080 021E H'0080 0220...
Page 71 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0296 TOP5 Correction Register (TOP5CC) H'0080 0298 H'0080 029A TOP0-5 Control Register 0 (TOP05CR0) H'0080 029C TOP0-5 Control Register 1 (TOP05CR1) H'0080 029E H'0080 02A0 TOP6 Counter (TOP6CT) H'0080 02A2 TOP6 Reload Register (TOP6RL) H'0080 02A4...
Page 72 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 031C TIO0-3 Control Register 1 (TIO03CR1) H'0080 0320 TIO2 Counter (TIO2CT) H'0080 0322 H'0080 0324 TIO2 Reload 1 Register (TIO2RL1) H'0080 0326 TIO2 Reload 0/Measure Register (TIO2RL0) H'0080 0330 TIO3 Counter (TIO3CT) H'0080 0332...
Page 73 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 03BC TIO0-9 Enable Protect Register (TIOPRO) TIO0-9 Count Enable Register (TIOCEN) H'0080 03BE H'0080 03C0 TMS0 Counter (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register (TMS0MR3) H'0080 03C4 TMS0 Measure 2 Register (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register (TMS0MR1)
Page 74 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 DMA2 Transfer Count Register (DM2TCT) H'0080 0430 DMA2 Channel Control Register (DM2CNT) H'0080 0432 DMA2 Source Address Register (DM2SA) H'0080 0434 DMA2 Destination Address Register (DM2DA) H'0080 0436 DMA7 Transfer Count Register (DM7TCT) H'0080 0438 DMA7 Channel Control Register (DM7CNT)
Page 75 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0716 P22 Data Register (P22DATA) P1 Direction Register (P1DIR) H'0080 0720 P0 Direction Register (P0DIR) P3 Direction Register (P3DIR) P2 Direction Register (P2DIR) H'0080 0722 P4 Direction Register (P4DIR) H'0080 0724 P7 Direction Register (P7DIR) H'0080 0726...
Page 76 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 07B0 TOD0_4 Counter (TOD04CT) H'0080 07B2 H'0080 07B4 TOD0_4 Reload 1 Register (TOD04RL1) H'0080 07B6 TOD0_4 Reload 0 Register (TOD04RL0) H'0080 07B8 TOD0_5 Counter (TOD05CT) H'0080 07BA H'0080 07BC TOD0_5 Reload 1 Register (TOD05RL1) H'0080 07BE...
Page 77 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0A80 A-D1 Single Mode Register 0 (AD1SIM0) A-D1 Single Mode Register 1 (AD1SIM1) H'0080 0A82 H'0080 0A84 A-D1 Scan Mode Register 0 (AD1SCM0) A-D1 Scan Mode Register 1 (AD1SCM1) H'0080 0A86 H'0080 0A88 A-D1 Successive Approximation Register (AD1SAR)
Page 78 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 0B96 TOD1_0 Reload 0 Register (TOD10RL0) H'0080 0B98 TOD1_1 Counter (TOD11CT) H'0080 0B9A H'0080 0B9C TOD1_1 Reload 1 Register (TOD11RL1) H'0080 0B9E TOD1_1 Reload 0 Register (TOD11RL0) TOD1_2 Counter (TOD12CT) H'0080 0BA0 H'0080 0BA2...
Page 79 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 TOM0_1 Reload 0 Register (TOM01RL0) H'0080 0C9E H'0080 0CA0 TOM0_2 Counter (TOM02CT) H'0080 0CA2 H'0080 0CA4 TOM0_2 Reload 1 Register (TOM02RL1) H'0080 0CA6 TOM0_2 Reload 0 Register (TOM02RL0) H'0080 0CA8 TOM0_3 Counter (TOM03CT) H'0080 0CAA...
Page 80 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 1000 CAN0 Control Register (CAN0CNT) H'0080 1002 CAN0 Status Register (CAN0STAT) H'0080 1004 CAN0 Extension ID Register (CAN0EXTID) H'0080 1006 CAN0 Configuration Register (CAN0CONF) H'0080 1008 CAN0 Time Stamp Count Register (CAN0TSTMP) H'0080 100A CAN0 Transmit Error Count Register (CAN0TEC)
Page 81 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) H'0080 1100 H'0080 1102 CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) H'0080 1104 CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2)
Page 82 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 H'0080 1154 CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) H'0080 1156 CAN0 Message Slot 5 Data 1 (C0MSL5DT1) CAN0 Message Slot 5 Data 0 (C0MSL5DT0) H'0080 1158 CAN0 Message Slot 5 Data 3 (C0MSL5DT3) CAN0 Message Slot 5 Data 2 (C0MSL5DT2)
Page 83 ADDRESS SPACE 3.4 Internal ROM/SFR Area Address +0 Address +1 Address D7 D8 CAN0 Message Slot 10 Data 3 (C0MSL10DT3) H'0080 11A8 CAN0 Message Slot 10 Data 2 (C0MSL10DT2) H'0080 11AA CAN0 Message Slot 10 Data 5 (C0MSL10DT5) CAN0 Message Slot 10 Data 4 (C0MSL10DT4) H'0080 11AC CAN0 Message Slot 10 Data 6 (C0MSL10DT6) CAN0 Message Slot 10 Data 7 (C0MSL10DT7)
Page 84: Eit Vector Entry
ADDRESS SPACE 3.5 EIT Vector Entry 3.5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/extended external areas. Instructions for branching to the start addresses of respective EIT event handlers are written here. Note that it is branch instructions and not the jump addresses that are written here.
Page 85: Icu Vector Table
ADDRESS SPACE 3.6 ICU Vector Table 3.6 ICU Vector Table The ICU vector table is used by the internal interrupt controller. The start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set at the ad- dresses shown below.
Page 86 ADDRESS SPACE 3.6 ICU Vector Table Address +0 Address +1 Address DMA0-4 Interrupt Handler Start Address (A0-A15) H'0000 00C8 DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CA SIO1 Receive Interrupt Handler Start Address (A0-A15) H'0000 00CC H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16-A31) H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31)
Page 87: Note About Address Space
ADDRESS SPACE 3.7 Notes on Address Space 3.7 Note about Address Space • Virtual flash emulation function The 32170 has a special function, called the "Virtual Flash Emulation Function," which allows the internal RAM to be mapped in blocks of 8 Kbytes from the beginning (up to four blocks for the M32170F6, up to three blocks for the M32170F4 and M32170F3) into internal flash memory areas divided in 8 Kbytes (L banks).
Page 88 ADDRESS SPACE 3.7 Notes on Address Space This is a blank page. 3-32 Ver.0.10...
Page 89: Chapter 4 Eit
CHAPTER 4 CHAPTER 4 Outline of EIT EIT Event EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring the PC and PSW EIT Vector Entry Exception Processing Interrupt Processing 4.10 Trap Processing 4.11 EIT Priority Levels 4.12 Example of EIT Processing...
Page 90 4.1 Outline of EIT 4.1 Outline of EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt, and Trap). (1) Exception This is an event related to the context being executed.
Page 91: Eit Event
4.2 EIT Event 4.2 EIT Event 4.2.1 Exception (1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions.
Page 92: Eit Processing Procedure
4.3 EIT Processing Procedure 4.3 EIT Processing Procedure EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below. EIT request generated Program execution restarted...
Page 93 4.3 EIT Processing Procedure When an EIT is accepted, the M32R/E saves the PC and PSW (as will be described later) and branches to the EIT vector. The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction (note that these are not branch address) for the EIT handler is written.
Page 94: Eit Processing Mechanism
4.4 EIT Processing Mechanism 4.4 EIT Processing Mechanism The M32R/E's EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (BPC register and the BPSW field of the PSW register). The M32R/E's internal EIT processing mechanism is shown below.
Page 95: Acceptance Of Eit Event
4.5 Acceptance of EIT Events 4.5 Acceptance of EIT Event When an EIT event occurs, the M32R/E suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below.
Page 96: Saving And Restoring The Pc And Psw
4.6 Saving and Restoring the PC and PSW 4.6 Saving and Restoring the PC and PSW The following describes operation of the M32R at the time when it accepts an EIT and when it executes the "RTE" instruction. (1) Hardware preprocessing when an EIT is accepted Save the SM, IE, and C bits of the PSW register ←...
Page 97 4.6 Saving and Restoring the PC and PSW Save SM, IE, and C bits Save PC Set vector address in PC Vector address Update SM, IE, and C bits Unchanged/0 Restore BSM, BIE, and BC bits Restore PC value from BPC from backup bits The value of BPC after execution of the "RTE"...
Page 98: Eit Vector Entry
4.7 EIT Vector Entry 4.7 EIT Vector Entry The EIT vector entry is located in the user space starting from address H'0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address Reset Interrupt H'0000 0000 (Note 1) Indeterminate...
Page 99: Exception Processing
4.8 Exception Processing 4.8 Exception Processing 4.8.1 Reserved Instruction Exception (RIE) [Occurrence Conditions] Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction which generated it is not executed.
Page 100 4.8 Exception Processing Address Address H'00 H'00 Return H'04 RIE occurred Return H'04 RIE occurred address address H'08 H'08 H'0C H'0C H'04 H'06 Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0020 in the user space.
Page 101: Address Exception (Ae)
4.8 Exception Processing 4.8.2 Address Exception (AE) [Occurrence Conditions] Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur: •...
Page 102 4.8 Exception Processing Address Address H'00 H'00 Return AE occurred Return AE occurred H'04 H'04 address address H'08 H'08 H'0C H'0C H'04 H'06 Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0030 in the user space.
Page 103: Interrupt Processing
4.9 Interrupt Processing 4.9 Interrupt Processing 4.9.1 Reset Interrupt (RI) [Occurrence Conditions] ____________ Reset Interrupt (RI) is unconditionally accepted in any machine cycle by pulling the RESET input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE, and C bits The SM, IE, and C bits of the PSW register are initialized in the manner shown below.
Page 104: System Break Interrupt (Sbi)
4.9 Interrupt Processing 4.9.2 System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when some fatal event has already occurred to the system when the interrupt is detected.
Page 105 4.9 Interrupt Processing [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits-the BSM, BIE, and BC bits. ← SM ← IE ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below.
Page 106: External Interrupt (Ei)
4.9 Interrupt Processing 4.9.3 External Interrupt (EI) An external interrupt is generated upon an interrupt request which is output by the 32170's internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, refer to Chapter 5, "Interrupt Controller." For details about the interrupt sources, refer to each section in which the relevant internal peripheral I/O is described.
Page 107 4.9 Interrupt Processing [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE, and BC bits. ← SM ← IE ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below.
Page 108: Trap Processing
4.10 Trap Processing 4.10 Trap Processing 4.10.1 Trap (TRAP) [Occurrence Conditions] Traps refer to software interrupts which are generated by executing the "TRAP" instruction. Sixteen distinct traps are generated, each corresponding to one of "TRAP" instruction operands 0-15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits –...
Page 109 4.10 Trap Processing Address Address H'00 H'00 H'04 H'04 TRAP occurred TRAP occurred Return Return H'08 H'08 address address H'0C H'0C H'08 H'0A Figure 4.10.1 Example of a Return Address for Trap (TRAP) (4) Branching to the EIT vector entry Control branches to the addresses H'0000 0040 through H'0000 007C in the user space.
Page 110: Eit Priority Levels
4.11 EIT Priority Levels 4.11 EIT Priority Levels The table below lists the priority levels of EIT events. When multiple EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority EIT Event Type of Processing...
Page 111: Example Of Eit Processing
4.12 Example of EIT Processing 4.12 Example of EIT Processing (1) When RIE, AE, SBI, EI, or TRAP occurs singly IE=1 BPC register = Return address A IE=0 RIE, AE, SBI, EI, If IE = 0, no events but reset or TRAP occurrs Singly and SBI are accepted Return address A:...
Page 112 4.12 Example of EIT Processing EIT vector entry BRA instruction (Any event other than SBI) (SBI) EIT handler Save BPC to stack Hardware (B)PSW preprocessing Save PSW to stack System Break Interrupt processing Save general-purpose Program registers to stack being executed •...
Page 113: Chapter 5 Interrupt Controller (Icu)
CHAPTER 5 CHAPTER 5 INTERRUPT CONTROLLER (ICU) Outline of the Interrupt Controller (ICU) Interrupt Sources of Internal Peripheral I/Os ICU-Related Registers ICU Vector Table Description of Interrupt Operation Description of System Break Interrupt (SBI) Operation...
Page 114: Outline Of Interrupt Controller (Icu)
INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) 5.1 Outline of Interrupt Controller (ICU) The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to the M32R CPU as external interrupts (EI).
Page 115 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) Interrupt controller System Break Interrupt request generated SBI Control Register SBIREQ (SBICR) the CPU core Peripheral circuits Interrupt Edge- recognized request IREQ Maskable interrupt Edge- ILEVEL Interrupt recognized request generated request IREQ Edge-...
Page 116: Interrupt Sources Of Internal Peripheral I/Os
INTERRUPT CONTROLLER (ICU) 5.2 Interrupt Sources of Internal Peripheral I/Os 5.2 Interrupt Sources of Internal Peripheral I/Os The interrupt controller receives as its inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD, and CAN. For details about these interrupts, refer to each section in which the relevant internal peripheral I/O is described.
Page 117 INTERRUPT CONTROLLER (ICU) 5.2 Interrupt Sources of Internal Peripheral I/Os Table 5.2.2 Interrupt Sources of Internal Peripheral I/Os (2/2) Interrupt Source Content Number of Input ICU Type of Input Sources Source (Note) MJT output interrupt 7 MJT output interrupt group 7 (TMS0, TMS1 output) Level-recognized MJT output interrupt 6 MJT output interrupt group 6 (TOP8, TOP9 output)
Page 118: Icu-Related Registers
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3 ICU-Related Registers The diagram below shows a map of the Interrupt Controller (ICU)'s related registers. Address +0 Address +1 Address H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 Interrupt Mask Register (IMASK) H'0080 0004 SBI Control Register (SBICR) H'0080 0006 TML1 Input Interrupt Control Register...
Page 119: Interrupt Vector Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.1 Interrupt Vector Register Interrupt Vector Register (IVECT) IVECT Bit Name Function 0 – 15 IVECT (16 low-order When an interrupt is accepted, the 16 low-order bits – bits of ICU vector in ICU vector table address for the accepted table address) interrupt source is stored in this register.
Page 120: Interrupt Mask Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.2 Interrupt Mask Register Interrupt Mask Register (IMASK) IMASK Bit Name Function 0 – 4 No functions assigned – 5– 7 IMASK (Interrupt mask) 000 : Maskable interrupts are disabled 001 : Level 0 interrupts can be accepted 010 : Level 0-1 interrupts can be accepted 011 : Level 0-2 interrupts can be accepted...
Page 121: Sbi (System Break Interrupt) Control Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.3 SBI (System Break Interrupt) Control Register SBI (System Break Interrupt) Control Register SBIREQ Bit Name Function 0 – 6 No functions assigned – SBI REQ (SBI request) 0 : SBI is not requested 1 : SBI is requested : Writable for only clearing operation (see the description below) _______...
Page 122: Interrupt Control Registers
INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers 5.3.4 Interrupt Control Registers CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) TML1 Interrupt Control Register (ITML1CR) TID2 Output Interrupt Control Register (ITID2CR) A-D1 Converter Interrupt Control Register (IAD1CCR) ...
Page 123 INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers D15) IREQ ILEVEL Bit Name Function 0 – 2 No functions assigned – (8-10) IREQ (Interrupt request) 0 : Interrupt is not requested (11) 1 : Interrupt is requested No functions assigned –...
Page 124 INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers Interrupt request from each peripheral function IREQ D3,11 set/clear Data bus Interrupt enabled D5-7,13-15 ILEVEL Interrupt priority (Levels 0-7) resolving circuit Figure 5.3.2 Interrupt Control Register Configuration (Edge-recognized Type) Group Interrupt request from each Group interrupt peripheral function Read-only circuit...
Page 125 INTERRUPT CONTROLLER (ICU) 5.3 ICU-Related Registers (2) ILEVEL (Interrupt Priority Level) (D5-D7 or D13-D15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set priority level 7 to disable interrupts from some internal peripheral I/O or priority levels 0-6 to enable interrupts.
Page 126: Icu Vector Table
INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table 5.4 ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 31-source interrupts are assigned the following addresses: Table 5.4.1 ICU Vector Table Addresses Interrupt Source ICU Vector Table Address MJT Input Interrupt 4...
Page 127 INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table Address +0 Address +1 Address MJT Input Interrupt 4 Handler Start Address (A0-A15) H'0000 0094 MJT Input Interrupt 4 Handler Start Address (A16-A31) H'0000 0096 MJT Input Interrupt 3 Handler Start Address (A0-A15) H'0000 0098 MJT Input Interrupt 3 Handler Start Address (A16-A31) H'0000 009A...
Page 128 INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table Address +0 Address +1 Address DMA0-4 Interrupt Handler Start Address (A0-A15) H'0000 00C8 DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CA SIO1 Receive Interrupt Handler Start Address (A0-A15) H'0000 00CC H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16-A31) H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31)
Page 129: Description Of Interrupt Operation
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5 Description of Interrupt Operation 5.5.1 Acceptance of Internal Peripheral I/O Interrupts An interrupt from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set by the Interrupt Control Register and the IMASK value of the Interrupt Mask Register.
Page 130 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.1 Hardware-fixed Priority Levels Priority Interrupt Source ICU Vector Table Address Type of Input Source High MJT Input Interrupt 4 (IRQ12) H'0000 0094-H'0000 0097 Level-recognized MJT Input Interrupt 3 (IRQ11) H'0000 0098-H'0000 009B Level-recognized MJT Input Interrupt 2 (IRQ10) H'0000 009C-H'0000 009F...
Page 131 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.2 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL="000") Accepted when IMASK is 1-7 1 (ILEVEL="001") Accepted when IMASK is 2-7 2 (ILEVEL="010") Accepted when IMASK is 3-7 3 (ILEVEL="011")
Page 132: Processing Of Internal Peripheral I/O Interrupts By Handlers
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.2 Processing of Internal Peripheral I/O Interrupts by Handlers (1) Branching to the interrupt handler When the CPU accepts an interrupt, control branches to the EIT vector entry after hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry for External Interrupt (EI) is located at address H'0000 0080.
Page 133 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation EI (External Interrupt) vector entry H'0000 0080 BRA instruction EI (External Interrupt) handler Save BPC to stack Save PSW to stack (Note) Save general-purpose Program register to stack being executed Read Interrupt Mask IMASK H'0080 0004 Register (IMASK) and...
Page 134: Description Of System Break Interrupt (Sbi) Operation
INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation 5.6 Description of System Break Interrupt (SBI) Operation 5.6.1 Acceptance of SBI System Break Interrupt (SBI) is an emergency interrupt which is used when power failure is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is _______ accepted anytime upon detection of a falling edge on the SBI signal regardless of how the PSW register IE bit is set, and cannot be masked.
Page 135: Chapter 6 Internal Memory
CHAPTER 6 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.2 Internal RAM 6.3 Internal Flash Memory 6.4 Registers Associated with the Internal Flash Memory 6.5 Programming of the Internal Flash Memory 6.6 Boot ROM 6.7 Virtual Flash Emulation Function 6.8 Connecting to A Serial Programmer...
Page 136 INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.1 Outline of the Internal Memory The 32170 internally contains the following types of memory: • 40 Kbyte or 32 Kbyte RAM • 768 Kbyte, 512 Kbyte, or 384 Kbyte flash memory 6.2 Internal RAM Specifications of the 32170's internal RAM are shown below.
Page 137 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4 Registers Associated with the Internal Flash Memory The diagram below shows a register map associated with the internal flash memory. Address +0 Address +1 Address Flash Mode Register Flash Status Register 1 H'0080 07E0 (FMOD) (FSTAT1)
Page 138: Flash Mode Register
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.1 Flash Mode Register Flash Mode Register (FMOD) FPMOD Bit Name Function 0 - 6 No functions assigned — FPMOD 0 : FP pin = low —...
Page 139: Flash Status Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.2 Flash Status Registers The 32170 has two registers to indicate the flash memory status, one of which is Flash Status Register 1 (FSTAT1) located in the SFR area (address: H'0080 07E1), and the other is Flash Status Register 2 (FSTAT2) included in the flash memory itself.
Page 140 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Status Register 2 (FSTAT2) FBUSY ERASE WRERR1 WRERR2 Bit Name Function FBUSY 0 : Program or erase under way — (Flash busy) 1 : Ready state No functions assigned —...
Page 141 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory (4) WRERR2 (Program operating condition) bit (D12) The WRERR2 bit is used to determine after execution whether the flash memory program operation resulted in an error. When WRERR2 = 0, it means the program operation terminated normally;...
Page 142: Flash Controle Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.3 Flash Controle Registers Flash Controle Register 1 (FCNT1) FENTRY FEMMOD Bit Name Function 0 - 2 No functions assigned — FENTRY 0 : Normal read (Flash mode entry) 1 : Erase/program enable 4 - 6...
Page 143 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory When using a program in the flash memory while the FENTRY bit = 0, the EI vector entry is located at address H'0000 0080 of the flash memory. When running a flash rewrite program in RAM while the FENTRY bit = 1, the EI vector entry is located at address H'0080 4000 of the RAM, allowing for flash rewrite operation to be controlled using interrupts.
Page 144 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Controle Register 2 (FCNT2) FPROT Bit Name Function 8 - 14 No functions assigned — FPROT 0 : Protection by lock bit effective (Unlock) 1 : Protection by lock bit not effective The Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection...
Page 145 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Controle Register 3 (FCNT3) FELEVEL Bit Name Function 0 - 6 No functions assigned — FELEVEL 0 : Normal level (Raise erase margin) 1 : Raise erase margin The Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands.
Page 146 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Controle Register 4 (FCNT4) FRESET Bit Name Function 8 - 14 No functions assigned — FRESET 0 : No operation performed (Reset flash) 1 : Reset the flash memory The Flash Control Register 4 (FCNT4) controls canceling program/erase operation in the middle and initializing each status bit of Flash Status Register 2 (FSTAT2).
Page 147 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory FENTRY=0 FENTRY=1 Program/erase flash memory Error found Program/erase terminated normally FRESET=1 FRESET=0 Program/erase flash memory Figure 6.4.3 Example for Using the FCNT4 Register 6-13 Ver.0.10...
Page 148: Virtual Flash L Bank Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.4 Virtual Flash L Bank Registers Virtual Flash L Bank Register 0 (FELBANK0) Virtual Flash L Bank Register 1 (FELBANK1) Virtual Flash L Bank Register 2 (FELBANK2) ...
Page 149: Virtual Flash S Bank Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.5 Virtual Flash S Bank Registers Virtual Flash S Bank Register 0 (FESBANK0) Virtual Flash S Bank Register 1 (FESBANK1) SBANKAD Bit Name Function MODENS...
Page 150: Programming Of The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5 Programming of the Internal Flash Memory 6.5.1 Outline of Programming Flash Memory When writing to the internal flash memory, there are following two methods to use depending on situation: (1) When the write program does not exist in the internal flash memory (2) When the write program already exists in the internal flash memory For (1), set the FP pin = high, MOD0 = high, and MOD1 = low to enter boot flash E/W enable mode.
Page 151 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Flash E/W enable mode Normal mode (FENTRY=1) (FENTRY=0) H'0000 0000 H'0000 0000 EI vector entry (H'0000 0080) Internal ROM area Internal ROM area EI vector entry H'0080 3FFF H'0080 3FFF (H'0080 4000) H'0080 4000 H'0080 4000 Internal RAM...
Page 152 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (1) When the write program does not exist in the internal flash memory Use a program in the boot ROM located on memory map to write to the flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode.
Page 153 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Reset deasserted (Boot program starts) Reset deasserted Mode selected Mode selected POWER ON RESET MOD0 MOD1 Settings by boot program FENTRY Writes to flash memory by boot program Figure 6.5.3 Internal Flash Memory Write Timings (when the write program does not exist in the flash memory) 6-19 Ver.0.10...
Page 154 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (2) When the write program already exists in the internal flash memory Use the flash write program already stored in the internal flash memory to write to the flash memory. For write to the flash memory, use the internal peripheral circuits according to your programming system.
Page 155 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Flash mode Flash rewrite Flash mode turned off starts turned on RESET "H" or "L" "L" MOD0 "H" or "L" (Single-chip or extended external) MOD1 "H" or "L" FENTRY Write to flash memory by flash rewrite program Flash rewrite program transferred to RAM...
Page 156: Controlling Operation Mode During Programming Flash
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.2 Controlling Operation Mode during Programming Flash The device's operation modes are set by MOD0, MOD1, and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be set during flash write. Table 6.5.1 Operation Modes Set during Flash Write MOD0 MOD1 FENTRY Operation Mode...
Page 157 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (2) Entering flash E/W enable mode Flash E/W enable mode can be entered only when the device is operating in single-chip mode or extended external mode. Namely, you can enter flash E/W enable mode only when the FP pin = high and the Flash Control Register 1 (FCNT1) FENTRY bit = 1.
Page 158 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Enter one of the following modes: • Single-chip mode + flash E/W enable mode • Boot mode + flash E/W enable mode FMOD(H'0080 07E0) • Extended external mode + flash E/W FPMOD enable mode P8DATA(H'0080 0708)
Page 159: Programming Procedure To The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.3 Programming Procedure to the Internal Flash Memory To write to the internal flash memory, set the device's operation mode to enter flash E/W enable mode first and then use the flash write program that has already been transferred from the flash memory into the internal RAM.
Page 160 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (2) Page Program command Flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H'00 to H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then the program data to the address to which you want to write.
Page 161 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.3 M32170F6 Target Blocks and Specified Addresses Target Block Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE H'0008 FFFE H'0009 FFFE...
Page 162 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.5 M32170F3 Target Blocks and Specified Addresses Target Block Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE 6-28 Ver.0.10...
Page 163 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F6's Internal Flash Memory Area (768KB) H'0000 0000 Block 0 16KB H'0000 3FFF H'0000 4000 Block 1 H'0000 5FFF H'0000 6000 Block 2 H'0000 7FFF Uneven blocks H'0000 8000 32KB Block 3 H'0000 FFFF H'0001 0000 64KB...
Page 164 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F4's Internal Flash Memory Area (512KB) H'0000 0000 Block 0 16KB H'0000 3FFF H'0000 4000 Block 1 H'0000 5FFF Uneven blocks H'0000 6000 Block 2 H'0000 7FFF H'0000 8000 32KB Block 3 H'0000 FFFF H'0001 0000 64KB...
Page 165 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32170F3's Internal Flash Memory Area (384KB) H'0000 0000 Block 0 16KB H'0000 3FFF H'0000 4000 Block 1 H'0000 5FFF Uneven blocks H'0000 6000 Block 2 H'0000 7FFF H'0000 8000 32KB Block 3 H'0000 FFFF H'0001 0000 64KB...
Page 166 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (4) Block Erase command The Block Erase command erases the contents of internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the memory block you want to erase (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses").
Page 167 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (8) Read Lock Bit Status command The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program/erase. Write the command data H'7171 to any address of the internal flash memory.
Page 168 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Follow the procedure described below to write to the lock bits. a) Setting the lock bit to 0 (protect the block) Issue the Lock Bit Program command (H'7777) to the memory block you want to protect. b) Setting the lock bit to 1 (unprotect the block) After setting the Flash Control Register 2 FPROT bit to invalidate lock bit-effectuated protection, use the Block Erase command (H'2020) or Erase All Unprotect Block command...
Page 169 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Page Program command (H'4141) to any address of internal flash memory. Write data to the internal flash memory address to which you want to write. (Note 1) Increment the previous write address by 2 and write the next data to the new address.
Page 170 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Lock Bit Program command (H'7777) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to protect. Written to the lock bit by program (Note 1) 1 µs wait (by hardware timer or software timer)
Page 171 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Erase command (H'2020) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer)
Page 172 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Erase All Unlock Block command (H'A7A7) to any address of internal flash memory. Write Verify command (H'D0D0) to any address in memory blocks you want to erase. Flash memory contents erased by Erase program (Note 1) 1 µs wait (by hardware timer or software timer)
Page 173 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Read Status command (H'7070) to any address of internal flash memory. Read any address of internal flash memory. Figure 6.5.15 Read Status Register START Write Clear Status command (H'5050) to any address of internal flash memory.
Page 174: Flash Write Time (For Reference)
INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.4 Flash Write Time (for Reference) The time required for writing to the internal flash memory is shown below for your reference. (1) M32170F6 Transfer time by SIO (for a transfer data size of 768 KB) 1/57600 bps ×...
Page 175 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (3) M32170F3 Transfer time by SIO (for a transfer data size of 384 KB) 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 384 KB 75.1 [s] Flash write time 384 KB/256-byte block ×...
Page 176: Boot Rom
INTERNAL MEMORY 6.6 Boot ROM 6.6 Boot ROM The table below shows boot memory specifications of the 32170. Table 6.6.1 Boot Memory Specifications Item Specification Capacity 8 Kbytes Location address H'8000 0000 - H'8000 1FFF Wait insertion Operates with no wait states (with 40 MHz internal CPU memory clock) Internal bus connection Connected by 32-bit bus Read...
Page 177: Virtual Flash Emulation Function
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7 Virtual Flash Emulation Function The 32170 has a special function, called the "Virtual Flash Emulation Function," which allows the internal RAM to be mapped in blocks of 8 Kbytes from the beginning (up to four blocks for the M32170F6, up to three blocks for the M32170F4 and M32170F3) into the internal flash memory area divided in units of 8 Kbytes (L banks).
Page 178 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0080 4000 RAM bank L block 0 (FELBANK0) 8 Kbytes H'0080 6000 RAM bank L block 1 (FELBANK1) 8 Kbytes H'0080 8000 RAM bank L block 2 (FELBANK2) 8 Kbytes RAM bank S block 0 H'0080 A000 (FESBANK0) 4 Kbytes...
Page 179: Virtual Flash Emulation Area
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.1 Virtual Flash Emulation Area The following shows the areas for which the Virtual Flash Emulation Function is effective. The Virtual Flash L Bank Registers (FELBANK0 to FELBANK3 for the M32170F6, FELBANK0 to FELBANK2 for the M32170F4 and M32170F3) allow one among all L banks of flash memory divided in 8 Kbytes each to be selected by setting the seven bits A12-A18 of the start address of the desired L bank in the Virtual Flash L Bank Register LBANKAD bits.
Page 180 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 L bank 0 (8 Kbytes) L bank 1 H'0000 2000 H'0080 4000 (8 Kbytes) 8 Kbytes L bank 2 H'0000 4000 H'0080 6000 (8 Kbytes) 8 Kbytes H'0080 8000 8 Kbytes H'0080 A000...
Page 181 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 L bank 0 (8 Kbytes) L bank 1 H'0000 2000 H'0080 4000 (8 Kbytes) 8 Kbytes L bank 2 H'0000 4000 H'0080 6000 (8 Kbytes) 8 Kbytes H'0080 8000 8 Kbytes 4 Kbytes...
Page 182 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 L bank 0 (8 Kbytes) L bank 1 H'0000 2000 H'0080 4000 (8 Kbytes) 8 Kbytes L bank 2 H'0000 4000 H'0080 6000 (8 Kbytes) 8 Kbytes H'0080 8000 8 Kbytes 4 Kbytes...
Page 183 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Start address of bank in L bank address (LBANKAD) L bank flash memory bit set value H'0000 0000 H'00 L bank 0 (NOTE) H'0000 2000 H'02 L bank 1 L bank 2 H'0000 4000 H'04 L bank 94 H'000B C000...
Page 184 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Start address of bank in L bank address (LBANKAD) L bank flash memory bit set value H'0000 0000 H'00 L bank 0 (NOTE) H'0000 2000 H'02 L bank 1 L bank 2 H'0000 4000 H'04 L bank 62 H'0007 C000...
Page 185 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Start address of bank in L bank address (LBANKAD) L bank flash memory bit set value H'0000 0000 H'00 L bank 0 (NOTE) H'0000 2000 H'02 L bank 1 L bank 2 H'0000 4000 H'04 L bank 46 H'0005 C000...
Page 186: Entering Virtual Flash Emulation Mode
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.2 Entering Virtual Flash Emulation Mode To enter Virtual Flash Emulation Mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering Virtual Flash Emulation Mode, set the Virtual Flash Bank Register MODEN bit to 1 to enable the Virtual Flash Emulation Function.
Page 187: Application Example Of Virtual Flash Emulation Mode
INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.3 Application Example of Virtual Flash Emulation Mode By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function, you can rewrite data in the flash memory successively. (1) Operation when reset Flash Bank xx...
Page 188 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function (4) Program operation using RAM block 1 Flash Replace Bank xx Initial value RAM block 1 Bank xx specified RAM block 0 Data write to RAM0 RAM block 1 (5) Program operation changed from RAM block 1 to RAM block 0 Flash Replace Bank xx...
Page 189: Connecting To A Serial Programmer
INTERNAL MEMORY 6.8 Connecting to A Serial Programmer 6.8 Connecting to A Serial Programmer When you rewrite the internal flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode, you need to process the pins on the 32170 shown below to make them suitable for the serial programmer.
Page 190 INTERNAL MEMORY 6.8 Connecting to A Serial Programmer The diagram below shows an example of user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the flash memory in clock-synchronized serial mode. No communication problems associated with the oscillation frequency may occur.
Page 191: Precautions To Be Taken When Rewriting Flash Memory
INTERNAL MEMORY 6.9 Precautions to Be Taken When Rewriting Flash Memory 6.9 Precautions to Be Taken When Rewriting Flash Memory The following describes precautions to be taken when you rewrite the flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode. •...
Page 192 INTERNAL MEMORY 6.9 Precautions to Be Taken When Rewriting Flash Memory This is a blank page. 6-58 Ver.0.10...
Page 193: Outline Of Reset
CHAPTER 7 CHAPTER 7 RESET 7.1 Outline of Reset 7.2 Reset Operation 7.3 Internal State Immediately after Reset Release 7.4 Things To Be Considered after Reset Release...
Page 194: Reset At Power-On
RESET 7.1 Outline of Reset 7.1 Outline of Reset _____ The device is reset by applying a low-level signal to the RESET input pin. The device is gotten out _____ of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry.
Page 195: Internal State Immediately After Reset Release
RESET 7.3 Internal State Immediately after Reset Release 7.3 Internal State Immediately after Reset Release The table below lists the register state of the device immediately after it has gotten out of reset. For details about the initial register state of each internal peripheral I/O, refer to each section in this manual where the relevant internal peripheral I/O is described.
Page 196: Things To Be Considered After Reset Release
RESET 7.4 Things To Be Considered after Reset Release 7.4 Things To Be Considered after Reset Release • Input/output ports After reset release, the 32170's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN) PIEN0 bit.
Page 197: Outline Of Input/Output Ports
CHAPTER 8 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.2 Selecting Pin Functions 8.3 Input/Output Port Related Registers 8.4 Port Peripheral Circuits...
Page 198 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32170 has a total of 157 input/output ports from P0 to P22 (of which P5 is reserved for future use, however). These input/output ports can be set for input or output mode by a direction register. Each input/output port serves as a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line.
Page 199 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports Table 8.1.1 Outline of Input/Output Ports Item Specification Number of ports Total 157 lines P00 - P07 (8 lines) P10 - P17 (8 lines) P20 - P27 (8 lines) P30 - P37 (8 lines) P41 - P47 (7 lines)
Page 200 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 8.2 Selecting Pin Functions Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions).
Page 201 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions DB10 DB11 DB12 DB13 DB14 DB15 Settings of CPU operation mode (Note 1) BLW/ BHW/ (Reserved) SCLKI4/ SCLKI5/ (P61) (P62) (P63) ADTRG SCLKO4 SCLKO5 BCLK/ WAIT HREQ HACK RTDTXD RTDRXD RTDACK RTDCLK SCLKI0/ SCLKI1/ TXD0...
Page 202 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers Included in the 32170 as input/output port related registers are the Port Data Registers, Port Direction Registers, and Port Operation Mode Registers. Of these, the Port Operation Mode Registers are provided for only P6-P22.
Page 203 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +1 Address +0 Address Address H'0080 0744 Port Input Function Enable Register (PIEN) P6 Operation Mode Register (P6MOD) P7 Operation Mode Register (P7MOD) H'0080 0746 P8 Operation Mode Register (P8MOD) H'0080 0748 P9 Operation Mode Register (P9MOD) P10 Operation Mode Register (P10MOD)
Page 204: Port Data Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.1 Port Data Registers P0 Data Register (P0DATA) P1 Data Register (P1DATA) P2 Data Register (P2DATA) P3 Data Register (P3DATA) P4 Data Register (P4DATA) ...
Page 205 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Bit Name Function Pn0DT (Port Pn0 data) Depending on how the Port Direction Register is set Pn1DT (Port Pn1 data) • When direction bit = 0 (input mode) Pn2DT (Port Pn2 data) 0: Port input pin = low Pn3DT (Port Pn3 data)
Page 206: Port Direction Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.2 Port Direction Registers P0 Direction Register (P0DIR) P1 Direction Register (P1DIR) P2 Direction Register (P2DIR) P3 Direction Register (P3DIR) P4 Direction Register (P4DIR) ...
Page 207 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Bit Name Function Pn0DIR (Port Pn0 direction bit) 0: Input mode (when reset) Pn1DIR (Port Pn1 direction bit) 1: Output mode Pn2DIR (Port Pn2 direction bit) Pn3DIR (Port Pn3 direction bit) Pn4DIR (Port Pn4 direction bit) Pn5DIR (Port Pn5 direction bit)
Page 208: Port Operation Mode Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.3 Port Operation Mode Registers P6 Operation Mode Register (P6MOD) P65MOD P66MOD P67MOD Bit Name Function 0 - 4 No functions assigned — P65MOD 0 : P65 (Port P65 operation mode)
Page 209 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P7 Operation Mode Register (P7MOD) P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD Bit Name Function P70MOD 0 : P70 (Port P70 operation mode) 1 : BCLK / WR P71MOD 0 : P71...
Page 210 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P8 Operation Mode Register (P8MOD) P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD Bit Name Function 0, 1 No functions assigned — P82MOD 0 : P82 (Port P82 operation mode) 1 : TXD0 P83MOD...
Page 211 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P9 Operation Mode Register (P9MOD) P93MOD P94MOD P95MOD P96MOD P97MOD Bit Name Function 8 - 10 No functions assigned — P93MOD 0 : P93 (Port P93 operation mode) 1 : TO16 P94MOD...
Page 212 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P10 Operation Mode Register (P10MOD) P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD Bit Name Function P100MOD 0 : P100 (Port P100 operation mode) 1 : TO8 P101MOD 0 : P101...
Page 213 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P11 Operation Mode Register (P11MOD) P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD Bit Name Function P110MOD 0 : P110 (Port P110 operation mode) 1 : TO0 P111MOD 0 : P111...
Page 214 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P12 Operation Mode Register (P12MOD) P124MOD P125MOD P126MOD P127MOD Bit Name Function 0 - 3 No functions assigned — P124MOD 0 : P124 (Port P124 operation mode) 1 : TCLK0 P125MOD...
Page 215 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P13 Operation Mode Register (P13MOD) P130MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD Bit Name Function P130MOD 0 : P130 (Port P130 operation mode) 1 : TIN16 P131MOD 0 : P131...
Page 216 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P14 Operation Mode Register (P14MOD) P140MOD P141MOD P142MOD P143MOD P144MOD P145MOD P146MOD P147MOD Bit Name Function P140MOD 0 : P140 (Port P140 operation mode) 1 : TIN8 P141MOD 0 : P141...
Page 217 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P15 Operation Mode Register (P15MOD) P150MOD P151MOD P152MOD P153MOD P154MOD P155MOD P156MOD P157MOD Bit Name Function P150MOD 0 : P150 (Port P150 operation mode) 1 : TIN0 P151MOD 0 : P151...
Page 218 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P16 Operation Mode Register (P16MOD) P160MOD P161MOD P162MOD P163MOD P164MOD P165MOD P166MOD P167MOD Bit Name Function P160MOD 0 : P160 (Port P160 operation mode) 1 : TO21 P161MOD 0 : P161...
Page 219 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P17 Operation Mode Register (P17MOD) P172MOD P173MOD P174MOD P175MOD P176MOD P177MOD Bit Name Function 8, 9 No functions assigned — P172MOD 0 : P172 (Port P172 operation mode) 1 : TIN24 P173MOD...
Page 220 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P18 Operation Mode Register (P18MOD) P180MOD P181MOD P182MOD P183MOD P184MOD P185MOD P186MOD P187MOD Bit Name Function P180MOD 0 : P180 (Port P180 operation mode) 1 : TO29 P181MOD 0 : P181...
Page 221 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P19 Operation Mode Register (P19MOD) P190MOD P191MOD P192MOD P193MOD P194MOD P195MOD P196MOD P197MOD Bit Name Function P190MOD 0 : P190 (Port P190 operation mode) 1 : TIN26 P191MOD 0 : P191...
Page 222 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P20 Operation Mode Register (P20MOD) P200MOD P201MOD P202MOD P203MOD Bit Name Function P200MOD 0 : P200 (Port P200 operation mode) 1 :TXD4 P201MOD 0 : P201 (Port P201 operation mode) 1 : RXD4...
Page 223 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P21 Operation Mode Register (P21MOD) P210MOD P211MOD P212MOD P213MOD P214MOD P215MOD P216MOD P217MOD Bit Name Function P210MOD 0 : P210 (Port P210 operation mode) 1 : TO37 P211MOD 0 : P211...
Page 224 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P22 Operation Mode Register (P22MOD) P220MOD P224MOD P225MOD Bit Name Function P220MOD 0 : P220 (Port P220 operation mode) 1 : CTX 1 - 3 No functions assigned —...
Page 225 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Port Input Function Enable Register (PIEN) PIEN0 Bit Name Function 8 - 14 No functions assigned — PIEN0 0 : Disables input (to prevent current from flowing in) (Port input function enable bit) 1 : Enables input This register is provided to prevent current from flowing into the port input pin.
Page 226 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Mode Name Controllable Pins Noncontrollable Pins P00 - P07, P10 - P17, P20 - P27 P64, P221, FP P30 -P37 , P41 - P47, P61 - P63 Single chip P65 - P67, P70 - P77, P82 - P87 P93 - P97, P100 - P107, P110 - P117 P124 - P127, P130 - P137, P140 - P147 P150 - P157, P160 - P167, P172 - P177...
Page 227: Port Peripheral Circuits
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits 8.4 Port Peripheral Circuits Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. P00 - P07 (DB0-DB7) P10 - P17 (DB8-DB15) Direction P20 - P27 (A23-A30) register P30 - P37 (A15-A22)
Page 228 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P64 (SBI) P221 / CRX Data bus (DB0 - DB15) Direction ____ P72 (HREQ) register Port output Data bus latch (DB0 - DB15) Operation mode register HREQ Input function enable Note : denotes pins.
Page 229 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits ____ P71 (WAIT) Direction register Port output Data bus latch (DB0 - DB15) Operation mode register WAIT Input function enable P70 (BCLK / WR) ____ P73 (HACK) P74 (RTDTXD) Direction P76 (RTDACK) register P82 (TXD0) Data bus...
Page 230 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P84 (SCLKI0, SCLKO0) P87 (SCLKI1, SCLKO1) P65 (SCLKI14, SCLKO4) P66 (SCLKI15, SCLKO5) Direction register Data bus Port output (DB0 - DB15) latch Operation mode register UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input Input function...
Page 231: Chapter 9 Dmac
CHAPTER 9 CHAPTER 9 DMAC 9.1 Outline of the DMAC 9.2 DMAC Related Registers 9.3 Functional Description of the DMAC 9.4 Precautions about the DMAC...
Page 232 DMAC 9.1 Outline of the DMAC 9.1 Outline of the DMAC The 32170 contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O.
Page 233 DMAC 9.1 Outline of the DMAC DMA channel 0 Software start Source address register One DMA2 transfer completed Destination address A-D conversion completed request register MJT (TIO8_udf) selector Transfer count MJT (input event bus 2) register DMA channel 1 Software start Source MJT (output event bus 0) request...
Page 234 DMAC 9.2 DMAC Related Registers 9.2 DMAC Related Registers The diagram below shows a memory map of DMAC related registers. +0 Address +1 Address Address DMA0-4 Interrupt Mask DMA0-4 Interrupt Request Status H'0080 0400 Register (DM04ITMK) Register (DM04ITST) DMA5-9 Interrupt Request Status DMA5-9 Interrupt Mask H'0080 0408 Register (DM59ITST)
Page 235 DMAC 9.2 DMAC Related Registers +0 Address +1 Address Address DMA3 Channel Control DMA3 Transfer Count H'0080 0440 Register (DM3CNT) Register (DM3TCT) H'0080 0442 DMA3 Source Address Register (DM3SA) H'0080 0444 DMA3 Destination Address Register (DM3DA) H'0080 0446 DMA8 Channel Control DMA8 Transfer Count H'0080 0448 Register (DM8CNT)
Page 236: Dma Channel Control Register
DMAC 9.2 DMAC Related Registers 9.2.1 DMA Channel Control Register DMA0 Channel Control Register (DM0CNT) MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 SADSL0 DADSL0 Bit Name Function MDSEL0 0 : Normal mode (Selects DMA0 transfer mode) 1 : Ring buffer mode TREQF0 0 : Not requested...
Page 237 DMAC 9.2 DMAC Related Registers DMA1 Channel Control Register (DM1CNT) MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 SADSL1 DADSL1 Bit Name Function MDSEL1 0 : Normal mode (Selects DMA1 transfer mode) 1 : Ring buffer mode TREQF1 0 : Not requested (DMA1 transfer request flag)
Page 238 DMAC 9.2 DMAC Related Registers DMA2 Channel Control Register (DM2CNT) MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 SADSL2 DADSL2 Bit Name Function MDSEL2 0 : Normal mode (Selects DMA2 transfer mode) 1 : Ring buffer mode TREQF2 0 : Not requested (DMA2 transfer request flag)
Page 239 DMAC 9.2 DMAC Related Registers DMA3 Channel Control Register (DM3CNT) MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 SADSL3 DADSL3 Bit Name Function MDSEL3 0 : Normal mode (Selects DMA3 transfer mode) 1 : Ring buffer mode TREQF3 0 : Not requested (DMA3 transfer request flag)
Page 240 DMAC 9.2 DMAC Related Registers DMA4 Channel Control Register (DM4CNT) MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 SADSL4 DADSL4 Bit Name Function MDSEL4 0 : Normal mode (Selects DMA4 transfer mode) 1 : Ring buffer mode TREQF4 0 : Not requested (DMA4 transfer request flag)
Page 241 DMAC 9.2 DMAC Related Registers DMA5 Channel Control Register (DM5CNT) MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 SADSL5 DADSL5 Bit Name Function MDSEL5 0 : Normal mode (Selects DMA5 transfer mode) 1 : Ring buffer mode TREQF5 0 : Not requested (DMA5 transfer request flag)
Page 242 DMAC 9.2 DMAC Related Registers DMA6 Channel Control Register (DM6CNT) MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 SADSL6 DADSL6 Bit Name Function MDSEL6 0 : Normal mode (Selects DMA6 transfer mode) 1 : Ring buffer mode TREQF6 0 : Not requested (DMA6 transfer request flag)
Page 243 DMAC 9.2 DMAC Related Registers DMA7 Channel Control Register (DM7CNT) MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 SADSL7 DADSL7 Bit Name Function MDSEL7 0 : Normal mode (Selects DMA7 transfer mode) 1 : Ring buffer mode TREQF7 0 : Not requested (DMA7 transfer request flag)
Page 244 DMAC 9.2 DMAC Related Registers DMA8 Channel Control Register (DM8CNT) MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 SADSL8 DADSL8 Bit Name Function MDSEL8 0 : Normal mode (Selects DMA8 transfer mode) 1 : Ring buffer mode TREQF8 0 : Not requested (DMA8 transfer request flag)
Page 245 DMAC 9.2 DMAC Related Registers DMA9 Channel Control Register (DM9CNT) MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 SADSL9 DADSL9 Bit Name Function MDSEL9 0 : Normal mode (Selects DMA9 transfer mode) 1 : Ring buffer mode TREQF9 0 : Not requested (DMA9 transfer request flag)
Page 246 DMAC 9.2 DMAC Related Registers The DMA Channel Control Register consists of bits to select DMA transfer mode in each channel, set DMA transfer request flag, and the bits to select the cause of DMA request, enable DMA transfer, and set the transfer size and the source/destination address directions. (1) MDSELn (DMAn transfer mode select) bit (D0) This bit when in single transfer mode selects normal mode or ring buffer mode.
Page 247: Dma Software Request Generation Registers
DMAC 9.2 DMAC Related Registers 9.2.2 DMA Software Request Generation Registers DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) ...
Page 248: Dma Source Address Registers
DMAC 9.2 DMAC Related Registers 9.2.3 DMA Source Address Registers DMA0 Source Address Register (DM0SA) DMA1 Source Address Register (DM1SA) DMA2 Source Address Register (DM2SA) DMA3 Source Address Register (DM3SA) DMA4 Source Address Register (DM4SA) ...
Page 249: Dma Destination Address Registers
DMAC 9.2 DMAC Related Registers 9.2.4 DMA Destination Address Registers DMA0 Destination Address Register (DM0DA) DMA1 Destination Address Register (DM1DA) DMA2 Destination Address Register (DM2DA) DMA3 Destination Address Register (DM3DA) DMA4 Destination Address Register (DM4DA) ...
Page 250: Dma Transfer Count Registers
DMAC 9.2 DMAC Related Registers 9.2.5 DMA Transfer Count Registers DMA0 Transfer Count Register (DM0TCT) DMA1 Transfer Count Register (DM1TCT) DMA2 Transfer Count Register (DM2TCT) DMA3 Transfer Count Register (DM3TCT) DMA4 Transfer Count Register (DM4TCT) ...
Page 251: Dma Interrupt Request Status Registers
DMAC 9.2 DMAC Related Registers 9.2.6 DMA Interrupt Request Status Registers DMA0-4 Interrupt Request Status Register (DM04ITST) DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 Bit Name Function 0 - 2 No functions assigned — DMITST4 (DMA4 interrupt request status) 0 : No interrupt request DMITST3 (DMA3 interrupt request status) 1 : Interrupt requested...
Page 252 DMAC 9.2 DMAC Related Registers DMA5-9 Interrupt Request Status Register (DM59ITST) DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 Bit Name Function 0 - 2 No functions assigned — DMITST9 (DMA9 interrupt request status) 0 : No interrupt request DMITST8 (DMA8 interrupt request status) 1 : Interrupt requested DMITST7 (DMA7 interrupt request status)
Page 253: Dma Interrupt Mask Registers
DMAC 9.2 DMAC Related Registers 9.2.7 DMA Interrupt Mask Registers DMA0-4 Interrupt Mask Register (DM04ITMK) DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 Bit Name Function 8 - 10 No functions assigned — DMITMK4 (DMA4 interrupt request mask) 0 : Enables interrupt request DMITMK3 (DMA3 interrupt request mask) 1 : Masks (disables) interrupt request...
Page 254 DMAC 9.2 DMAC Related Registers DMA5-9 Interrupt Mask Register (DM59ITMK) DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 Bit Name Function 8 - 10 No functions assigned — DMITMK9 (DMA9 interrupt request mask) 0 : Enables interrupt request DMITMK8 (DMA8 interrupt request mask) 1 : Masks (disables) interrupt request DMITMK7 (DMA7 interrupt request mask)
Page 255 DMAC 9.2 DMAC Related Registers DM04ITST DM04ITMK DMA4UDF 5-source inputs Data bus DMITST4 DMA transfer interrupt 0 (Level) DMITMK4 DMA3UDF DMITST3 DMITMK3 DMA2UDF DMITST2 DMITMK2 DMA1UDF DMITST1 DMITMK1 DMA0UDF DMITST0 DMITMK0 Figure 9.2.3 Block Diagram of DMA Transfer Interrupt 0 9-25 Ver.0.10...
Page 256 DMAC 9.2 DMAC Related Registers DM59ITST DM59ITMK DMA9UDF 5-source inputs Data bus DMITST9 DMA transfer interrupt 1 (Level) DMITMK9 DMA8UDF DMITST8 DMITMK8 DMA7UDF DMITST7 DMITMK7 DMA6UDF DMITST6 DMITMK6 DMA5UDF DMITST5 DMITMK5 Figure 9.2.4 Block Diagram of DMA Transfer Interrupt 1 9-26 Ver.0.10...
Page 257: Functional Description Of The Dmac
DMAC 9.3 Functional Description of the DMAC 9.3 Functional Description of the DMAC 9.3.1 Cause of DMA Request For each DMA channel (channels 0 to 9), DMA transfer can be requested from multiple sources. There are various causes (or sources) of DMA transfer, so that DMA transfer can be started by a request from internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers in a DMA channel (cascade mode).
Page 258 DMAC 9.3 Functional Description of the DMAC Table 9.3.3 Causes of DMA Requests in DMA2 and Generation Timings REQSL2 Cause of DMA Request DMA Request Generation Timing Software start When any data is written to DMA2 Software Request Generation Register MJT (output event bus 1) When MJT's output event bus 1 signal is generated MJT (TIN18 input signal)
Page 259 DMAC 9.3 Functional Description of the DMAC Table 9.3.6 Causes of DMA Requests in DMA5 and Generation Timings REQSL5 Cause of DMA Request DMA Request Generation Timing Software start When any data is written to DMA5 Software Request or one DMA7 transfer completed Generation Register or one DMA7 transfer is completed (cascade mode) All DMA0 transfers completed...
Page 260 DMAC 9.3 Functional Description of the DMAC Table 9.3.9 Causes of DMA Requests in DMA8 and Generation Timings REQSL8 Cause of DMA Request DMA Request Generation Timing Software start When any data is written to DMA8 Software Request Generation Register MJT (input event bus 0) When MJT's input event bus 0 signal is generated Serial I/O3 (reception completed)
Page 261: Dma Transfer Processing Procedure
DMAC 9.3 Functional Description of the DMAC 9.3.2 DMA Transfer Processing Procedure Shown below is an example of how to control DMA transfer in cases when performing transfer in DMA channel 0. DMA transfer processing starts Setting interrupt Set the interrupt controller's DMA0-4 controller related •...
Page 262: Starting Dma
DMAC 9.3 Functional Description of the DMAC 9.3.3 Starting DMA Use the REQSL (cause of DMA request select) bit to set the cause of DMA request. To enable DMA, set the TENL (DMA transfer enable) bit to 1. DMA transfer begins when the specified cause of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1.
Page 263: Transfer Counts
DMAC 9.3 Functional Description of the DMAC 9.3.6 Transfer Units Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer. 9.3.7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel.
Page 264 DMAC 9.3 Functional Description of the DMAC (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds ("Address fixed" or "Address incremental") is set for each channel using the SADSL (source address direction select) and DADSL (destination address select) bits.
Page 265 DMAC 9.3 Functional Description of the DMAC (6) Transfer byte positions When the transfer unit = 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address, or from odd address to even address.) When the transfer unit = 8 bits, the LSB of the address register (D15 of the address register) is...
Page 266: Transfer Operation
DMAC 9.3 Functional Description of the DMAC (7) Ring buffer mode When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated.
Page 267: End Of Dma And Interrupt
DMAC 9.3 Functional Description of the DMAC 9.3.10 End of DMA and Interrupt In normal mode, DMA transfer is terminated when the transfer count register underflows. When transfer finishes, the transfer enable bit is cleared to 0 and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer.
Page 268: Precautions About The Dmac
DMAC 9.4 Precautions about the DMAC 9.4 Precautions about the DMAC • About writing to DMAC related registers Because DMA transfer involves exchanging data via the internal bus, basically you only can write to the DMAC related registers immediately after reset or when transfer is disabled (transfer enable bit = 0).
Page 269 DMAC 9.4 Precautions about the DMAC 9.4 Precautions about the DMAC • Manipulating DMAC related registers by DMA transfer When manipulating DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers' initial values by DMA transfer), do not write to the DMAC related registers on the local channel itself through that channel.
Page 270 DMAC 9.4 Precautions about the DMAC * This is a blank page.* 9-40 Ver.0.10...
Page 271: Chapter 10 Multijunction Timers
CHAPTER 10 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers 10.2 Common Units of Multijunction Timer 10.3 TOP (Output-related 16-bit Timer) 10.4 TIO (Input/Output-related 16-bit Timer) 10.5 TMS (Input-related 16-bit Timer) 10.6 TML (Input-related 32-bit Timer) 10.7 TID (Input-related 16-bit Timer) 10.8 TOD (Output-related 16-bit Timer) 10.9 TOM (Output-related 16-bit Timer)
Page 272 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers 10.1 Outline of Multijunction Timers The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs.
Page 273 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Table 10.1.1 Outline of Multijunction Timers (2/2) Name Type Number of Channels Description Input-related One of three input modes can be selected by software. (Timer Input 16-bit timer • Fixed period mode Derivation) (up/down-counter) •...
Page 274 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Table 10.1.3 DMA Transfer Request Generation by MJT Signal Name Source of DMA Request Generated DMAC Input Channel DRQ0 TIO8 underflow Channel 0 DRQ1 Input event bus 2 Channel 0 DRQ2 Output event bus 0 Channel 1 DRQ3 TIN13 input...
Page 275 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Clock bus Input event bus Output event bus 0 12 3 3 21 0 3 21 0 IRQ2 F/F0 TO 0 TOP 0 IRQ2 TCLK0 TCLK0S F/F1 TO 1 TOP 1 (Note 1) IRQ2 IRQ9 F/F2...
Page 276 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Clock bus Input event bus Output event bus 0 12 3 3 21 0 3 21 0 TCLK3 TCLK3S IRQ7 TMS 0 cap3 cap2 cap1 cap0 IRQ10 TIN12 TIN12S IRQ10 TIN13 TIN13S DRQ3 IRQ10 TIN14 TIN14S...
Page 277 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers (Note) Output event bus Clock bus Input event bus IRQ13 3 2 1 0 3 21 0 0 12 3 TOD0_0 F/F21 TO21 IRQ13 TOD0_1 F/F22 TO22 IRQ13 TOD0_2 F/F23 TO23 IRQ13 TOD0_3 F/F24 TO24 IRQ13...
Page 278 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Clock bus Input event bus Output event bus 3 21 0 3 2 1 0 0 1 2 3 (Note 3) completed DMAIRQ0 TIO8-udf DMA0 (Note 3) DMAIRQ0 DMA1 TIN13 (Note 2) DMAIRQ0 TIN18 DMA2 (Note 2)
Page 279: Timer Common Register Map
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2 Common Units of Multijunction Timer The common units of the multijunction timer include the following: • Prescaler unit • Clock bus/input-output event bus control unit • Input processing control unit • Output flip-flop control unit •...
Page 280 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer +0 Address +1 Address Address Clock Bus & Input Event Bus H'0080 0200 Control Register (CKIEBCR) H'0080 0202 Prescaler Register 0 (PRS0) Prescaler Register 1 (PRS1) Output Event Bus Control Register Prescaler Register 2 (PRS2) H'0080 0204 (OEBCR) TCLK Input Processing Control Register (TCLKCR)
Page 281 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer +0 Address +1 Address Address TID1 Control & Prescaler 4 H'0080 0BD0 Prescaler Register 4 (PRS4) Enable Register (TID1PRS4EN) TOD1 Interrupt Mask Register TOD1 Interrupt Status Register H'0080 0BD2 (TOD1IMA) (TOD1IST) F/F Protect Register 3 (FFP3) H'0080 0BD4 H'0080 0BD6 F/F Data Register 3 (FFD3)
Page 282: Prescaler Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2.2 Prescaler Unit The prescalers PRS0-5 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML, TID, TOD, and TOM) from the divide-by-2 frequency of the internal peripheral clock (10.0 MHz when the internal peripheral clock = 20 MHz).
Page 283: Clock Bus/Input-Output Event Bus Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2.3 Clock Bus/Input-Output Event Bus Control Unit (1) Clock bus The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0-3. Each timer can use this clock bus signal as clock input signal. The table below lists the signals that can be fed to the clock bus.
Page 284 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer (3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0-3. Output event bus signals are connected to output flip-flops, and can also be connected to other peripheral circuits-output event bus 3 to A-D0 converter, output event bus 0 to DMA channel 1, and output event bus 1 to DMA channel 2.
Page 285 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Table 10.2.4 Timings at Which Signals Are Generated to the Output Event Bus by Each Timer (2/2) Timer Mode Timings at which signals are generated to the output event bus PWM output mode No signal generation function Single-shot PWM output mode No signal generation function...
Page 286 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The clock bus/input-output bus control unit has the following registers: • Clock Bus & Input Event Bus Control Register (CKIEBCR) • Output Event Bus Control Register (OEBCR) Clock Bus & Input Event Bus Control Register (CKIEBCR) IEB3S IEB2S IEB1S...
Page 287 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Output Event Bus Control Register (OEBCR) OEB3S OEB2S OEB1S OEB0S Bit Name Function 8, 9 OEB3S 00 : Selects TOP8 output (output event bus 3 input selection) 01 : Selects TIO3 output 10 : Selects TIO4 output 11 : Selects TIO8 output No functions assigned...
Page 288: Input Processing Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2.4 Input Processing Control Unit The input processing control unit processes the TCLK and TIN signals fed into the MJT. In the TCLK input processing unit, selection is made of the source of TCLK signal, or for external input, the active edge (rising or falling or both) or level (high or low) of the signal, with or at which to generate the clock signal fed to the clock bus.
Page 289 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer (1) Functions of TCLK input processing control registers Item Function 1/2 internal peripheral clock 1/2 internal peripheral clock Count clock Rising clock edge TCLK Count clock Falling clock edge TCLK Count clock Both edges TCLK Count...
Page 290 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer (2) Functions of TIN input processing control registers Item Function Rising edge Internal edge signal Falling edge Internal edge signal Both edges Internal edge signal Low level TCLK PSC x clock width or TCLK x input Internal edge signal...
Page 291 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TLCK Input Processing Control Register (TCLKCR) TCLK3S TCLK2S TCLK1S TCLK0S Bit Name Function 0, 1 No functions assigned — 2, 3 TCLK3S 00 : 1/2 internal peripheral clock (TCLK3 input 01 : Rising edge processing selection)
Page 292 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Input Processing Control Register 0 (TINCR0) TIN4S TIN3S TIN2S TIN1S TIN0S Bit Name Function No functions assigned — 1 - 3 TIN4S 000 : Invalidates input (TIN4 input 001 : Rising edge processing selection)
Page 293 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Input Processing Control Register 1 (TINCR1) TIN8S TIN7S TIN6S TIN5S Bit Name Function No functions assigned — 1 - 3 TIN8S 000 : Invalidates input (TIN8 input 001 : Rising edge processing selection)
Page 294 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Input Processing Control Register 2 (TINCR2) TIN11S TIN10S TIN9S Bit Name Function 0 - 4 No functions assigned — 5 - 7 TIN11S 000 : Invalidates input (TIN11 input 001 : Rising edge processing selection)
Page 295 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Input Processing Control Register 3 (TINCR3) TIN19S TIN18S TIN17S TIN16S TIN15S TIN14S TIN13S TIN12S Bit Name Function 0, 1 TIN19S (TIN19 input processing selection) 00 : Invalidates input 2, 3 TIN18S (TIN18 input processing selection)
Page 296: Output Flip-Flop Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2.5 Output Flip-Flop Control Unit The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. Following flip-flop control registers are included: • F/F Source Select Register 0 (FFS0) •...
Page 297 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Table 10.2.5 Timings at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timer Mode Timings at which signals are generated to the output flip-flop Single-shot output mode When counter is enabled and when underflows Delayed single-shot output mode When counter underflows Continuous output mode...
Page 298 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Port operation mode F/F source register(PnMOD) selection (FFn) Output event bus 0 Internal edge signal Output event bus 1 Output event bus 2 Output event bus 3 F/Fn output data (FDn) Output control (ON/OFF) F/F protect (FPn) Note: Dn denotes the data bus.
Page 299 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Source Select Register 0 (FFS0) FF15 FF14 FF13 FF12 FF11 FF10 Bit Name Function 0 - 2 No functions assigned — FF15 (F/F15 source selection) 0 : TIO4 output 1 : Output event bus 0 FF14 (F/F14 source selection)
Page 300 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Source Select Register 1 (FFS1) FF19 FF18 FF17 FF16 Bit Name Function 8, 9 FF19 (F/F19 source selection) 0X : TIO8 output 10 : Output event bus 0 11 : Output event bus 1 10, 11 FF18 (F/F18 source selection)
Page 301 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Protect Register 0 (FFP0) FP15 FP14 FP13 FP12 FP11 FP10 Bit Name Function FP15 (F/F15 protect) 0 : Enables write to F/F output bit FP14 (F/F14 protect) 1 : Disables write to F/F output bit FP13 (F/F13 protect)
Page 302 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Protect Register 1 (FFP1) FP20 FP19 FP18 FP17 FP16 Bit Name Function 8 - 10 No functions assigned — FP20 (F/F20 protect) 0 : Enables write to F/F output bit FP19 (F/F19 protect) 1 : Disables write to F/F output bit FP18 (F/F18 protect)
Page 303 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Protect Register 3 (FFP3) FP29 FP30 FP31 FP32 FP33 FP34 FP35 FP36 Bit Name Function FP29 (F/F29 protect) 0 : Enables write to F/F output bit FP30 (F/F30 protect) 1 : Disables write to F/F output bit FP31 (F/F31 protect)
Page 304 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Data Register 0 (FFD0) FD15 FD14 FD13 FD12 FD11 FD10 Bit Name Function FD15 (F/F15 output data) 0 : F/F output data = 0 FD14 (F/F14 output data) 1 : F/F output data = 1 FD13 (F/F13 output data)
Page 305 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Data Register 1 (FFD1) FD20 FD19 FD18 FD17 FD16 Bit Name Function 8 - 10 No functions assigned — FD20 (F/F20 output data) 0 : F/F output data = 0 FD19 (F/F19 output data) 1 : F/F output data = 1 FD18 (F/F18 output data)
Page 306 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer F/F Data Register 3 (FFD3) FD29 FD30 FD31 FD32 FD33 FD34 FD35 FD36 Bit Name Function FD29 (F/F29 output data) 0 : F/F output data = 0 FD30 (F/F30 output data) 1 : F/F output data = 1 FD31 (F/F31 output data)
Page 307: Interrupt Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer 10.2.6 Interrupt Control Unit The interrupt control unit controls the interrupt signals sent to the interrupt controller by each timer. Following 22 timer interrupt control registers are provided for each timer. • TOP Interrupt Control Register 0 (TOPIR0) •...
Page 308 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer For interrupts which have two or more sources of interrupt in one interrupt table, interrupt control registers are provided, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the interrupt controller function only as a bit to show whether an interrupt-enabled interrupt request occurred and cannot be written to.
Page 309 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer Example for clearing the interrupt status Interrupt status flag Initial state Interrupt request b6 event occurred b4 event occurred Write to the interrupt status Only b6 cleared b4 data retained Figure 10.2.6 Example for Clearing the Interrupt Status 10-39 Ver.0.10...
Page 310 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer The table below shows the relationship between the interrupt signals generated by multijunction timers and the interrupt sources input to the interrupt controller. Table 10.2.6 Interrupt Signals Generated by MJT Signal Name Source of Interrupt Generated Interrupt Sources Input to ICU Number of Input Sources (Note 1)
Page 311 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOP Interrupt Control Register 0 (TOPIR0) TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0 Bit Name Function 0, 1 No functions assigned — TOPIS5 (TOP5 interrupt status) 0 : No interrupt request TOPIS4 (TOP4 interrupt status) 1 : Interrupt request generated...
Page 312 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOPIR0 TOPIR1 TOP5udf Data bus 6-source inputs TOPIS5 MJT output interrupt 2 TOPIM5 (Level) IRQ2 TOP4udf TOPIS4 TOPIM4 TOP3udf TOPIS3 TOPIM3 TOP2udf TOPIS2 TOPIM2 TOP1udf TOPIS1 TOPIM1 TOP0udf TOPIS0 TOPIM0 Figure 10.2.7 Block Diagram of MJT Output Interrupt 2...
Page 313 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOP Interrupt Control Register 2 (TOPIR2) TOPIS7 TOPIS6 TOPIM7 TOPIM6 Bit Name Function 0, 1 No functions assigned — TOPIS7 (TOP7 interrupt status) 0 : No interrupt request TOPIS6 (TOP6 interrupt status) 1 : Interrupt request generated 4, 5...
Page 314 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOP Interrupt Control Register 3 (TOPIR3) TOPIS9 TOPIS8 TOPIM9 TOPIM8 Bit Name Function 8, 9 No functions assigned — TOPIS9 (TOP9 interrupt status) 0 : No interrupt request TOPIS8 (TOP8 interrupt status) 1 : Interrupt request generated 12, 13...
Page 315 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIO Interrupt Control Register 0 (TIOIR0) TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0 Bit Name Function TIOIS3 (TIO3 interrupt status) 0 : No interrupt request TIOIS2 (TIO2 interrupt status) 1 : Interrupt request generated TIOIS1 (TIO1 interrupt status)
Page 316 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIO Interrupt Control Register 1 (TIOIR1) TIOIS7 TIOIS6 TIOIS5 TIOIS4 TIOIM7 TIOIM6 TIOIM5 TIOIM4 Bit Name Function TIOIS7 (TIO7 interrupt status) 0 : No interrupt request TIOIS6 (TIO6 interrupt status) 1 : Interrupt request generated TIOIS5 (TIO5 interrupt status)
Page 317 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIO Interrupt Control Register 2 (TIOIR2) TIOIS9 TIOIS8 TIOIM9 TIOIM8 Bit Name Function 0, 1 No functions assigned — TIOIS9 (TIO9 interrupt status) 0 : No interrupt request TIOIS8 (TIO8 interrupt status) 1 : Interrupt request generated 4, 5...
Page 318 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TMS Interrupt Control Register (TMSIR) TMSIS1 TMSIS0 TMSIM1 TMSIM0 Bit Name Function 8, 9 No functions assigned — TMSIS1 (TMS1 interrupt status) 0 : No interrupt request TMSIS0 (TMS0 interrupt status) 1 : Interrupt request generated 12, 13...
Page 319 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Interrupt Control Register 0 (TINIR0) TINIS2 TINIS1 TINIS0 TINIM2 TINIM1 TINIM0 Bit Name Function No functions assigned — TINIS2 (TIN2 interrupt status) 0 : No interrupt request TINIS1 (TIN1 interrupt status) 1 : Interrupt request generated TINIS0 (TIN0 interrupt status)
Page 320 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Interrupt Control Register 1 (TINIR1) TINIS6 TINIS5 TINIS4 TINIS3 TINIM6 TINIM5 TINIM4 TINIM3 Bit Name Function TINIS6 (TIN6 interrupt status) 0 : No interrupt request TINIS5 (TIN5 interrupt status) 1 : Interrupt request generated TINIS4 (TIN4 interrupt status)
Page 321 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Interrupt Control Register 2 (TINIR2) TINIS11 TINIS10 TINIS9 TINIS8 TINIS7 Bit Name Function 0,1,2 No functions assigned — TINIS11 (TIN11 interrupt status) 0 : No interrupt request TINIS10 (TIN10 interrupt status) 1 : Interrupt request generated TINIS9 (TIN9 interrupt status)
Page 322 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TINIR2 TINIR3 TIN11edge 5-source inputs Data bus TINIS11 MJT input interrupt 0 IRQ8 (Level) TINIM11 TIN10edge TINIS10 TINIM4 TIN9edge TINIS9 TINIM9 TIN8edge TINIS8 TINIM8 TIN7edge TINIS7 TINIM7 Figure 10.2.16 Block Diagram of MJT Input Interrupt 0 10-52 Ver.0.10...
Page 323 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Interrupt Control Register 4 (TINIR4) TINIS19 TINIS18 TINIS17 TINIS16 TINIS15 TINIS14 TINIS13 TINIS12 Bit Name Function TINIS19 (TIN19 interrupt status) 0 : No interrupt request TINIS18 (TIN18 interrupt status) 1 : Interrupt request generated TINIS17 (TIN17 interrupt status)
Page 324 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TINIR4 TINIR5 TIN19edge Data bus 8-source inputs TINIS19 MJT input interrupt 2 IRQ10 TINIM19 (Level) TIN18edge TINIS18 TINIM18 TIN17edge TINIS17 TINIM17 TIN16edge TINIS16 TINIM16 TIN15edge TINIS15 TINIM15 TIN14edge TINIS14 TINIM14 TIN13edge...
Page 325 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TIN Interrupt Control Register 6 (TINIR6) TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20 Bit Name Function TINIS23 (TIN23 interrupt status) 0 : No interrupt request TINIS22 (TIN22 interrupt status) 1 : Interrupt request generated TINIS21 (TIN21 interrupt status)
Page 326 TIN Interrupt Control Register 7 (TINIR7) TINIS33 TINIS32 TINIS31 TINIS30 TINIM33 TINIM32 TINIM31 TINIM30 Bit Name Function TINIS33 (TIN33 interrupt status) 0 : No interrupt request TINIS32 (TIN32 interrupt status) 1 : Interrupt request generated TINIS31 (TIN31 interrupt status) TINIS30 (TIN30 interrupt status) TINIM33 (TIN33 interrupt mask)
Page 327 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOD0 Interrupt Mask Register (TOD0IMA) TOD07IMA TOD06IMA TOD05IMA TOD04IMA TOD03IMA TOD02IMA TOD01IMA TOD00IMA Bit Name Function TOD07IMA (TOD0_7 interrupt mask) 0 : Enables interrupt request TOD06IMA (TOD0_6 interrupt mask) 1 : Masks (disables) interrupt request TOD05IMA (TOD0_5 interrupt mask)
Page 328 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOD0IMA TOD0IST TOD07udf Data bus 8-source inputs TOD07IST TOD0 output interrupt 2 TOD07IMA IRQ13 (Level) TOD06udf TOD06IST TOD06IMA TOD05udf TOD05IST TOD05IMA TOD04udf TOD04IST TOD04IMA TOD03udf TOD03IST TOD03IMA TOD02udf TOD02IST TOD02IMA TOD01udf...
Page 329 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOD1 Interrupt Mask Register (TOD1IMA) TOD17IMA TOD16IMA TOD15IMA TOD14IMA TOD13IMA TOD12IMA TOD11IMA TOD10IMA Bit Name Function TOD17IMA (TOD1_7 interrupt mask) 0 : Enables interrupt request TOD16IMA (TOD1_6 interrupt mask) 1 : Masks (disables) interrupt request TOD15IMA (TOD1_5 interrupt mask)
Page 330 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOM0 Interrupt Mask Register (TOM0IMA) TOM07IMA TOM06IMA TOM05IMA TOM04IMA TOM03IMA TOM02IMA TOM01IMA TOM00IMA Bit Name Function TOM07IMA (TOM0_7 interrupt mask) 0 : Enables interrupt request TOM06IMA (TOM0_6 interrupt mask) 1 : Masks (disables) interrupt request TOM05IMA (TOM0_5 interrupt mask)
Page 331 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOD1IMA TOD1IST TOD17udf Data bus 16-source inputs TOD17IST TOD1 + TOM0 output interrupt TOD17IMA (Level) IRQ16 TOD16udf TOD16IST TOD16IMA TOD15udf TOD15IST TOD15IMA TOD14udf TOD14IST TOD14IMA TOD13udf TOD13IST TOD13IMA TOD12udf TOD12IST TOD12IMA...
Page 332 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timer TOM0IMA TOM0IST TOM07udf Data bus TOM07IST To the preceding page TOM07IMA TOM06udf TOM06IST TOM06IMA TOM05udf TOM05IST TOM05IMA TOM04udf TOM04IST TOM04IMA TOM03udf TOM03IST TOM03IMA TOM02udf TOM02IST TOM02IMA TOM01udf TOM01IST TOM01IMA TOM00udf TOM00IST...
Page 333: Top (Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3 TOP (Output-related 16-bit Timer) 10.3.1 Outline of TOP TOP (Timer Output) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Single-shot output mode •...
Page 334 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TOP 0 Reload register IRQ2 Down-counter F/F0 TO 0 Correction register (16 bits) IRQ2 TCLK0 TCLK0S...
Page 335: Outline Of Each Mode Of Top
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.2 Outline of Each Mode of TOP Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. (1) Single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops without performing any operation.
Page 336 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow.
Page 337: Top Related Register Map
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.3 TOP Related Register Map The diagram below shows a TOP-related register map. Address +0 Address +1 Address H'0080 0240 TOP0 Counter (TOP0CT) H'0080 0242 TOP0 Reload Register (TOP0RL) H'0080 0244 TOP0 Correction Register (TOP0CC) H'0080 0246 H'0080 0250 TOP1 Counter (TOP1CT)
Page 338 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) +0 Address +1 Address Address D7 D8 TOP4 Counter (TOP4CT) H'0080 0280 H'0080 0282 TOP4 Reload Register (TOP4RL) H'0080 0284 TOP4 Correction Register (TOP4CC) H'0080 0286 H'0080 0290 TOP5 Counter (TOP5CT) H'0080 0292 TOP5 Reload Register (TOP5RL) H'0080 0294 TOP5 Correction Register (TOP5CC)
Page 339 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) +0 Address +1 Address Address D7 D8 TOP8 Counter (TOP8CT) H'0080 02C0 H'0080 02C2 TOP8 Reload Register (TOP8RL) H'0080 02C4 TOP8 Correction Register (TOP8CC) H'0080 02C6 H'0080 02D0 TOP9 Counter (TOP9CT) TOP9 Counter (TOP9CT) H'0080 02D2 TOP9 Reload Register (TOP9RL) TOP9 Reload Register (TOP9RL)
Page 340: Top Control Registers
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.4 TOP Control Registers The TOP control registers are used to select operation modes of TOP0-10 (single-shot, delayed single-shot, or continuous mode), as well as select the counter enable and counter clock sources. Following four TOP control registers are provided for each timer group.
Page 341 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOP0-5 Control Register 0 (TOP05CR0) TOP3M TOP2M TOP1M TOP0M TOP05ENS TOP05CKS Bit Name Function TOP3M (TOP3 operation mode selection) 00: Single-shot output mode TOP2M (TOP2 operation mode selection) 01: Delayed single-shot output mode TOP1M (TOP1 operation mode selection) 1X: Continuous output mode TOP0M (TOP0 operation mode selection)
Page 342 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOP0-5 Control Register 1 (TOP05CR1) TOP5M TOP4M Bit Name Function 8-11 No functions assigned – 12,13 TOP5M (TOP5 operation mode selection) 00: Single-shot output mode 14,15 TOP4M (TOP4 operation mode selection) 01: Delayed single-shot output mode 1X: Continuous output mode Note: Always make sure the counter has stopped and is idle before setting or changing operation modes.
Page 343 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOP6,7 Control Register (TOP67CR) TOP7 TOP7M TOP6M TOP67ENS TOP67CKS Bit Name Function No functions assigned – TOP7ENS 0: Result selected by TOP67ENS bit (TOP7 enable source selection) 1: TOP6 output TOP7M (TOP7 operation mode selection) 00: Single-shot output mode 01: Delayed single-shot output mode...
Page 344 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Clock bus Input event bus 3 2 1 0 3 2 1 0 TOP 6 TOP 7 TIN1 TIN1S : Selector Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted. Figure 10.3.6 Outline Diagram of TOP6, TOP7 Clock/Enable Inputs 10-74 Ver.0.10...
Page 345 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOP8-10 Control Register (TOP810CR) TOP10M TOP9M TOP8M TOP810CKS Bit Name Function No functions assigned – TOP10M (TOP10 operation mode selection) 00: Single-shot output mode TOP9M (TOP9 operation mode selection) 01: Delayed single-shot output mode TOP8M (TOP8 operation mode selection) 1X: Continuous output mode...
Page 346 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Clock bus Input event bus 3 2 1 0 3 2 1 0 TOP 8 TOP 9 TOP 10 TIN2 TIN2S : Selector Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted. Figure 10.3.7 Outline Diagram of TOP8-10 Clock/Enable Inputs 10-76 Ver.0.10...
Page 347: Top Counters (Top0Ct-Top10Ct)
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.5 TOP Counters (TOP0CT-TOP10CT) TOP0 Counter (TOP0CT) TOP1 Counter (TOP1CT) TOP2 Counter (TOP2CT) TOP3 Counter (TOP3CT) TOP4 Counter (TOP4CT) TOP5 Counter (TOP5CT) TOP6 Counter (TOP6CT) ...
Page 348: Top Reload Registers (Top0Rl-Top10Rl)
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.6 TOP Reload Registers (TOP0RL-TOP10RL) TOP0 Reload Register (TOP0RL) TOP1 Reload Register (TOP1RL) TOP2 Reload Register (TOP2RL) TOP3 Reload Register (TOP3RL) TOP4 Reload Register (TOP4RL) ...
Page 349: Top Correction Registers (Top0Cc-Top10Cc)
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.7 TOP Correction Registers (TOP0CC-TOP10CC) TOP0 Correction Register (TOP0CC) TOP1 Correction Register (TOP1CC) TOP2 Correction Register (TOP2CC) TOP3 Correction Register (TOP3CC) TOP4 Correction Register (TOP4CC) ...
Page 350: Top Enable Control Register
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.8 TOP Enable Control Register TOP0-10 External Enable Permit Register (TOPEEN) TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 Bit Name Function No functions assigned – TOP10EEN (TOP10 external enable permit) 0: Disables external enable TOP9EEN (TOP9 external enable permit) 1: Enables external enable TOP8EEN (TOP8 external enable permit)
Page 351 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOP0-10 Enable Protect Register (TOPPRO) TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 Bit Name Function No functions assigned – TOP10PRO (TOP10 enable protect) 0: Enables rewrite TOP9PRO (TOP9 enable protect) 1: Disables rewrite TOP8PRO (TOP8 enable protect)
Page 352 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOP0-10 Count Enable Register (TOPCEN) TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 Bit Name Function No functions assigned – TOP10CEN (TOP10 count enable) 0: Stops count TOP9CEN (TOP9 count enable) 1: Enables count TOP8CEN (TOP8 count enable)
Page 353 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) TOPm external enable (TOPmEEN) Edge selection EN-ON TINnS Event bus TOPm enable (TOPmCEN) TOP enable control TOPm enable protect (TOPmPRO) Figure 10.3.8 Configuration of the TOP Enable Circuit 10-83 Ver.0.10...
Page 354: Operation In Top Single-Shot Output Mode (With Correction Function)
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) (1) Outline of TOP single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register value + 1) only once and stops without performing any operation.
Page 355 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the reload register has the initial value H'A000 set in it. (The initial value of the counter can be indeterminate, and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter causing it to start counting.
Page 356 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Correction function of TOP single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter.
Page 357 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. In the example below, the reload register has the initial value H'8000 set in it.
Page 358 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Enabled (by writing to enable bit Disabled (by underflow) or by external input) Count clock Enable bit Write to correction register H'FFFF H'FFFF H'5000+H'4000 Counter H'8000 H'5000 H'0000 H'8000 Reload register Correction register H'4000 Indeterminate F/F output...
Page 359 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (3) Precautions to be observed when using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
Page 360 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Enabled (by writing to enable bit or by external input) Disabled (by underflow) Count clock Enable bit Write to correction register Overflow occurs H'(FFF0+0014) H'FFFF H'FFFF H'FFF8 Indeterminate H'FFF0 Counter Actual count H'0004 after overflow H'0000 Reload register...
Page 361: Operation In Top Delayed Single-Shot Output Mode (With Correction Function)
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.10 Operation in TOP Delayed Single-shot Output Mode (With Correction Function) (1) Outline of TOP delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation.
Page 362 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'F000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register.
Page 363 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Correction function of TOP delayed single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter.
Page 364 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) Underflow Underflow (first time) (second time) Count clock Enable bit Write to correction register H'FFFF H'(F000+0008+1) H'F000 Counter corrected Counter H'A000 H'0000 H'F000 Reload register Correction register Indeterminate H'0008 F/F output Data inverted by Data inverted by underflow underflow...
Page 365 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (3) Precautions to be observed when using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode. • If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
Page 366: Operation In Top Continuous Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) 10.3.11 Operation in TOP Continuous Output Mode (Without Correction Function) (1) Outline of TOP continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload register value.
Page 367 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) The valid count values are the (counter set value + 1) and (reload register set value + 1). The diagram below shows timer operation as an example when the initial counter value = 4 and the initial reload register value = 5.
Page 368 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'E000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register and continues counting down.
Page 369 MULTIJUNCTION TIMERS 10.3 TOP (Output-related 16-bit Timer) (2) Precautions to be observed when using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
Page 370: Tio (Input/Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.1 Outline of TIO TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: •...
Page 371 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TIO 0 Reload 0/measure register IRQ0 TO 11 F/F11 Down-counter Reload 1 register (note) (16 bits) IRQ12 en/cap...
Page 372: Outline Of Each Mode Of Tio
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.2 Outline of Each Mode of TIO Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered.
Page 373 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down.
Page 374 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1).
Page 375: Tio Related Register Map
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.3 TIO Related Register Map The diagram below shows a TIO related register map. Address +0 Address +1 Address TIO0 Counter (TIO0CT) H'0080 0300 H'0080 0302 TIO0 Reload 1 Register (TIO0RL) H'0080 0304 TIO0 Reload 0/ Measure Register (TIO0RL0) H'0080 0306 TIO1 Counter (TIO1CT)
Page 376 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Address +0 Address +1 Address D7 D8 TIO4 Counter (TIO4CT) H'0080 0340 H'0080 0342 TIO4 Reload 1 Register (TIO4RL) H'0080 0344 TIO4 Reload 0/ Measure Register (TIO4RL0) H'0080 0346 H'0080 0348 TIO4 Control Register TIO5 Control Register H'0080 034A (TIO4CR)
Page 377 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Address +0 Address +1 Address D7 D8 TIO8 Counter (TIO8CT) H'0080 0380 H'0080 0382 TIO8 Reload 1 Register (TIO8RL) H'0080 0384 TIO8 Reload 0/ Measure Register (TIO8RL0) H'0080 0386 H'0080 0388 TIO8 Control Register TIO9 Control Register H'0080 038A (TIO8CR)
Page 378: Tio Control Registers
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.4 TIO Control Registers The TIO control registers are used to select TIO0-9 operation modes (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output, or continuous output mode), as well as select the counter enable and counter clock sources. Following eight TIO control registers are provided for each timer group.
Page 379 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO0-3 Control Register 0 (TIO3CR0) TIO3 TIO2 TIO1 TIO0 TIO3M TIO2M TIO1M TIO0M Bit Name Function TIO3EEN (TIO3 external input enable) 0: Disables external input (Note 2) 1: Enables external input TIO3M (TIO3 operation mode selection) 000: Single-shot output mode 001: Delayed single-shot output mode...
Page 380 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (Continued from the preceding page) Bit Name Function 9-11 TIO1M 000: Single-shot output mode (TIO1 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode TIO0ENS (TIO0 enable/...
Page 381 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO0-3 Control Register 1 (TIO03CR1) TIO03CKS Bit Name Function 8-13 No functions assigned – 14,15 TIO03CKS 00: Clock bus 0 (TIO0-3 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 10-111 Ver.0.10...
Page 382 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO4 Control Register (TIO4CR) TIO4CKS TIO4EEN TIO34ENS TIO4M Bit Name Function 0, 1 TIO4CKS 00: Clock bus 0 (TIO4 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 TIO4EEN (Note 1) 0: Disables external input...
Page 383 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Clock bus Input event bus 3 2 1 0 3 2 1 0 TCLK1 TCLK1S TIO 5 en/cap TIN7 TIN7S TCLK2 TCLK2S TIO 6 en/cap TIN8 TIN8S TIO 7 en/cap TIN9 TIN9S TIO 8 en/cap TIN10 TIN10S...
Page 384 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO5 Control Register (TIO5CR) TIO5CKS TIO5ENS TIO5M Bit Name Function 8-10 TIO5CKS 0XX: External input TCLK1 (TIO5 clock source selection) 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11,12 TIO5ENS...
Page 385 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO6 Control Register (TIO6CR) TIO6CKS TIO6ENS TIO6M Bit Name Function TIO6CKS 0XX: External input TCLK2 (TIO6 clock source selection) 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 TIO6ENS 00: No selection...
Page 386 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO7 Control Register (TIO7CR) TIO7CKS TIO7ENS TIO7M Bit Name Function No functions assigned – 9,10 TIO7CKS 00: Clock bus 0 (TIO7 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO7ENS...
Page 387 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO8 Control Register (TIO8CR) TIO8CKS TIO8ENS TIO8M Bit Name Function TIO8CKS 00: Clock bus 0 (TIO8 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 TIO8ENS 0XX: No selection (TIO8 enable/measure...
Page 388 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO9 Control Register (TIO9CR) TIO9CKS TIO9ENS TIO9M Bit Name Function No functions assigned – 9,10 TIO9CKS 00: Clock bus 0 (TIO9 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO9ENS...
Page 389: Tio Counter (Tio0Ct-Tio9Ct)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.5 TIO Counter (TIO0CT-TIO9CT) TIO0 Counter (TIO0CT) TIO1 Counter (TIO1CT) TIO2 Counter (TIO2CT) TIO3 Counter (TIO3CT) TIO4 Counter (TIO4CT) TIO5 Counter (TIO5CT) TIO6 Counter (TIO6CT) ...
Page 390: Tio Reload 0/ Measure Register (Tio0Rl0-Tio9Rl0)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.6 TIO Reload 0/ Measure Register (TIO0RL0-TIO9RL0) TIO0 Reload 0/ Measure Register (TIO0RL0) TIO1 Reload 0/ Measure Register (TIO1RL0) TIO2 Reload 0/ Measure Register (TIO2RL0) TIO3 Reload 0/ Measure Register (TIO3RL0) ...
Page 391: Tio Reload 1 Registers (Tio0Rl1-Tio9Rl1)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.7 TIO Reload 1 Registers (TIO0RL1-TIO9RL1) TIO0 Reload 1 Register (TIO0RL1) TIO1 Reload 1 Register (TIO1RL1) TIO2 Reload 1 Register (TIO2RL1) TIO3 Reload 1 Register (TIO3RL1) TIO4 Reload 1 Register (TIO4RL1) ...
Page 392: Tio Enable Control Registers
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.8 TIO Enable Control Registers TIO0-9 Enable Protect Register (TIOPRO) TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 Bit Name Function No functions assigned – TIO9PRO (TIO9 Enable Protect) 0: Enables rewrite TIO8PRO (TIO8 Enable Protect) 1: Disables rewrite...
Page 393 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIO0-9 Count Enable Register (TIOCEN) TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 Bit Name Function No functions assigned – TIO9CEN (TIO9 count enable) 0: Stops count TIO8CEN (TIO8 count enable) 1: Enables count TIO7CEN (TIO7 count enable)
Page 394 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) TIOm external enable (TIOmEEN or TIOmENS) Edge selection EN-ON TINnS Event bus TIOm enable (TIOmCEN) TIO enable control TIOm enable protect (TIOmPRO) Figure 10.4.7 Configuration of the TIO Enable Circuit 10-124 Ver.0.10...
Page 395: Operation In Tio Measure Free-Run/Clear Input Modes
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.9 Operation in TIO Measure Free-run/Clear Input Modes (1) Outline of TIO measure free-run/clear input modes In TIO measure free-run/clear input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered. An interrupt can be generated by a counter underflow or execution of measure operation.
Page 396 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Measure event Measure event Enabled (capture) (capture) (by writing to enable bit) occurs occurs Count clock Enable bit H'FFFF H'9000 Counter H'7000 H'0000 H'7000 H'9000 Measure register Indeterminate TIN interrupt TIN interrupt by TIN interrupt by external event input external event input...
Page 397 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Measure event Enabled (capture) (by writing to enable bit) occurs Count clock Enable bit H'FFFF Counter H'7000 H'0000 H'7000 Indeterminate Measure register TIN interrupt TIN interrupt by external event input TIO interrupt TIO interrupt by underflow Note: This diagram does not show detail timing information.
Page 398 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (2) Precautions to be observed when using TIO measure free-run/clear input modes The following describes precautions to be observed when using TIO measure free-run/clear input modes. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched into the measure register.
Page 399: Operation In Tio Noise Processing Input Mode
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.10 Operation in TIO Noise Processing Input Mode In noise processing input mode, the timer detects the status of an input signal that it remained in the same state for over a predetermined time. In noise processing input mode, the counter is started by entering a high or low-level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows, the counter stops after generating an interrupt.
Page 400: Operation In Tio Pwm Output Mode
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.11 Operation in TIO PWM Output Mode (1) Outline of TIO PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down.
Page 401 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit Down-count Down-count starting from Down-count starting starting from reload 0 register from reload 1 register reload 0 register set value set value...
Page 402 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register.
Page 403 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 Write to reload 1 (reload 1 data latched) H'1000 H'8000 Reload 0 register H'2000 H'9000 Reload 1 register...
Page 404: Operation In Tio Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) (1) Outline of TIO single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation.
Page 405 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled Disabled (by writing to enable bit (by underflow) or by external input) Count clock Enable bit H'FFFF Counts down starting H'A000 from reload 0 register set value Counter H'0000 Reload 0 register H'A000 Reload 1 register (Not used)
Page 406: Operation In Tio Delayed Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) (1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation.
Page 407 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit H'FFFF H'F000 H'EFFF Down-count starting Down-count starting from reload 0 register H'A000 from counter set value Counter set value...
Page 408: Operation In Tio Continuous Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) 10.4.14 Operation in TIO Continuous Output Mode (Without Correction Function) (1) Outline of TIO continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value.
Page 409 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit H'FFFF H'DFFF H'DFFF H'E000 Down-count Down-count Down-count starting from starting from H'A000 starting from reload 0 register reload 0 register counter...
Page 410: Tms (Input-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5 TMS (Input-related 16-bit Timer) 10.5.1 Outline of TMS TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total eight channels. The table below shows specifications of TMS. The diagram in the next page shows a block diagram of TMS.
Page 411 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TMS 0 IRQ7 TCLK3 TCLK3S Counter Measure register 3 (16 bits) Measure register 2 Measure register 1 Measure register 0 cap3...
Page 412: Tms Related Register Map
MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5.3 TMS Related Register Map The diagram below shows a TMS related register map. Address +0 Address +1 Address D7 D8 TMS Counter (TMS0CT) H'0080 03C0 TMS0 Measure 3 Register (TMS0MR3) H'0080 03C2 TMS0 Measure 2 Register (TMS0MR2) H'0080 03C4 TMS0 Measure 1 Register (TMS0MR1)
Page 413 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5.4 TMS Control Registers The TMS control registers are used to select TMS0/1 input events and the counter clock source, as well as control counter startup. Following two TMS control registers are included: •...
Page 414 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) TMS1 Control Register (TMS1CR) TMS1 TMS1 TMS1 TMS1 TMS1CKS TMS1CEN Bit Name Function TMS1SS0 0: External input TIN19 (TMS1measure 0 source selection) 1: Input event bus 0 TMS1SS1 0: External input TIN18 (TMS1 measure 1 source selection) 1: Input event bus 1...
Page 415: Tms Counters (Tms0Ct, Tms1Ct)
MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5.5 TMS Counter (TMS0CT, TMS1CT) TMS0 Counter (TMS0CT) TMS1 Counter (TMS1CT) TMS0CT, TMS1CT Bit Name Function 0-15 TMS0CT, TMS1CT 16-bit counter value Note: This register must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software).
Page 416: Tms Measure Registers (Tms0Mr3-0, Tms1Mr3-0)
MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) ...
Page 417: Operation Of Tms Measure Input
MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) 10.5.7 Operation of TMS Measure Input (1) Outline of TMS measure input In TMS measure input, the counter starts counting up clock pulses when the timer is actuated by writing to the enable bit in software. When event input is entered to TMS while the timer is operating, the counter value is latched into measure registers 0-3.
Page 418 MULTIJUNCTION TIMERS 10.5 TMS (Input-related 16-bit Timer) (2) Precautions to be observed when using TMS measure input The following describes precautions to be observed when using TMS measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched to the measure register.
Page 419: Tml (Input-Related 32-Bit Timer)
MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10.6 TML (Input-related 32-bit Timer) 10.6.1 Outline of TML TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TML.
Page 420: Outline Of Tml Operation
MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) Output event bus Clock bus Input event bus 3 2 1 0 3 2 1 0 0 1 2 3 TML0 1/2 internal Counter Measure register 3 peripheral clock (32 bits) Measure register 2 Measure register 1 Measure register 0 cap3...
Page 421: Tml Related Register Map
MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10.6.3 TML Related Register Map The diagram below shows a TML related register map. Address +0 Address +1 Address D7 D8 H'0080 03E0 TML0 Counter, High (TML0CTH) TML0 Counter, Low (TML0CTL) H'0080 03E2 TML0 Control Register H'0080 03EA (TML0CR)
Page 422: Tml Control Registers
MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10.6.4 TML Control Registers TML0 Control Register (TML0CR) TML0SS0 TML0SS1 TML0SS2 TML0SS3 TML0CKS Bit Name Function TML0SS0 0: External input TIN23 (TML0 measure 0 source selection) 1: Input event bus 0 TML0SS1 0: External input TIN22 (TML0 measure 1 source selection)
Page 423 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) TML1 Control Register (TML1CR) TML1SS0 TML1SS1 TML1SS2 TML1SS3 TML1CKS Bit Name Function TML1SS0 0: External input TIN33 (TML1 measure 0 source selection) 1: Input event bus 0 TML1SS1 0: External input TIN32 (TML1 measure 1 source selection) 1: Input event bus 1...
Page 424: Tml Counters
MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10.6.5 TML Counters TML0 Counter, High (TML0CTH) TML0 Counter, Low (TML0CTL) TML0CTH (16 high-order bits) TML0CTL (16 low-order bits) Bit Name Function 0-15 TML0CTH 32-bit counter value (16 high-order bits) TML0CTL 32-bit counter value (16 low-order bits)
Page 425 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) TML1 Counter, High (TML1CTH) TML1 Counter, Low (TML1CTL) TML1CTH (16 high-order bits) TML1CTL (16 low-order bits) Bit Name Function 0-15 TML1CTH 32-bit counter value (16 high-order bits) TML1CTL 32-bit counter value (16 low-order bits) Note: This register must always be accessed in words (32 bits) beginning with the address of TML1CTH.
Page 426: Tml Measure Registers
MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10.6.6 TML Measure Registers TML0 Measure 3 Register (TML0MR3H) TML0 Measure 3 Register (TML0MR3L) TML0 Measure 2 Register (TML0MR2H) TML0 Measure 2 Register (TML0MR2L) ...
Page 427 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) TML1 Measure 3 Register (TML1MR3H) TML1 Measure 3 Register (TML1MR3L) TML1 Measure 2 Register (TML1MR2H) TML1 Measure 2 Register (TML1MR2L) TML1 Measure 1 Register (TML1MR1H) ...
Page 428: Operation Of Tml Measure Input
MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) 10.6.7 Operation of TML Measure Input (1) Outline of TML measure input In TML measure input, the counter starts counting up clock pulses upon deassertion of reset. When event input is entered to measure registers 0-3, the counter value is latched into the measure registers.
Page 429 MULTIJUNCTION TIMERS 10.6 TML (Input-related 32-bit Timer) (2) Precautions to be observed when using TML measure input The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched to the measure register.
Page 430: Tid (Input-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) 10.7 TID (Input-related 16-bit Timer) 10.7.1 Outline of TID TID (Timer Input Derivation) is an input-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Fixed period count mode •...
Page 431 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) TID0 Reload register Built-in edge control circuit CLK1 TIN24 Up/down-counter IRQ14 CLK2 TIN25 1/2 internal PSC3 peripheral clock TOD0_0 - 7 TID1 IRQ15 Reload register Built-in edge control circuit CLK1 AD1TRG TIN26 Up/down-counter CLK2 (To A-D1 converter) TIN27...
Page 432: Tid Related Register Map
MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) 10.7.2 TID Related Register Map The diagram below shows a TID related register map. +0 Address +1 Address Address H'0080 078C TID0 Counter (TID0CT) H'0080 078E TID0 Reload Register (TID0RL) TID0 Control & Prescaler 3 H'0080 07D0 Prescaler Register 3 (PRS3) Enable Register (TID0PRS3EN)
Page 433: Tid Control &Prescaler Enable Registers
MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) 10.7.3 TID Control &Prescaler Enable Registers TID0 Control &Prescaler 3 Enable Register (TID0PRS3EN) TID0M TID0CEN PRS3EN Bit Name Function No functions assigned — 9, 10 TID0M 0X : Fixed period count mode (TID0 operation mode selection) 10 : Multiply-by-4 event count mode...
Page 434 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) TID1 Control &Prescaler 4 Enable Register (TID1PRS4EN) TID1M TID1CEN TID1ENO PRS4EN Bit Name Function No functions assigned — 9, 10 TID1M 0X : Fixed period count mode (TID1 operation mode selection) 10 : Multiply-by-4 event count mode 11 : Event count mode...
Page 435 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) TID2 Control &Prescaler 5 Enable Register (TID2PRS5EN) TID2M TID2CEN TID2ENO PRS5EN Bit Name Function No functions assigned — 9, 10 TID2M 0X : Fixed period count mode (TID2 operation mode selection) 10 : Multiply-by-4 event count mode 11 : Event count mode...
Page 436: Tid Counters (Tid0Ct, Tid1Ct, Tid2Ct)
MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) 10.7.4 TID Counters (TID0CT, TID1CT, TID2CT) TID0 Counter (TID0CT) TID1 Counter (TID1CT) TID2 Counter (TID2CT) TID0CT, TID1CT, TID2CT Bit Name Function 0 - 15 TID0CT, TID1CT, TID2CT...
Page 437: Tid Reload Registers (Tid0Rl, Tid1Rl, Tid2Rl)
MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) 10.7.5 TID Reload Registers (TID0RL, TID1RL, TID2RL) TID0 Reload Register (TID0RL) TID1 Reload Register (TID1RL) TID2 Reload Register (TID2RL) TID0RL, TID1RL, TID2RL Bit Name Function 0 - 15...
Page 438: Outline Of Each Mode Of Tid
MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) 10.7.6 Outline of Each Mode of TID Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time: (1) Fixed period count mode In fixed period count mode, the timer uses a reload register to generate an interrupt at intervals of (reload register set value + 1).
Page 439 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) (2) Event count mode In event count mode, the timer uses an external input signal (TIN24, TIN26, or TIN28) as the clock source with which to operate the counter. Note: TIN25, TIN27, and TIN29 cannot be used as the clock source. By detecting rising and falling edges of the external input signal (TIN24, TIN26, or TIN28), the timer generates clock pulses synchronized to the internal clock.
Page 440 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) (3) Multiply-by-4 event count mode In multiply-by-4 event count mode, the timer uses two external input signals in pairs (TIN24 and TIN25, TIN26 and TIN27, or TIN28 and TIN29) as the clock sources with which to operate the counter.
Page 441 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) TIN24 TIN25 Counter value 7FFE 7FFF 8000 8001 8002 8003 8002 8001 8000 7FFF 7FFE Switched over 8003 Counter 7FFE Up-count Down-count Figure 10.7.6 Up/Down Count Operation (Switchover Timing) TIN24 TIN25 Counter value 7FFE 7FFF 8000...
Page 442 MULTIJUNCTION TIMERS 10.7 TID (Input-related 16-bit Timer) TIN24 TIN25 Counter value FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF FFFE FFFD Switched over FFFF Counter 0000 TID Interrupt Up-count Down-count Figure 10.7.8 Up/Down Count Operation (Interrupt Timing) 10-172 Ver.0.10...
Page 443: Tod (Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8 TOD (Output-related 16-bit Timer) 10.8.1 Outline of TOD TOD (Timer Output Derivation) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software. This timer is a variation of TIO, with TIO input modes removed. ...
Page 444 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD0_0 F/F21 TO 21 TOD0_1 F/F22 TO 22 TOD0_2 TO 23 F/F23 TOD0_3 F/F24 TO 24 1/2 internal PSC3 peripheral TOD0_4 F/F25 TO 25 clock TOD0_5 F/F26 TO 26 TOD0_6 F/F27 TO 27 TOD0_7 TO 28 F/F28...
Page 445: Outline Of Each Mode Of Tod
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.2 Outline of Each Mode of TOD Each mode of TOD is outlined below. For each TOD channel, only one of the following modes can be selected. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
Page 446 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) (3) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation.
Page 447: Tod Related Register Map
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.3 TOD Related Register Map The diagram below shows a TOD related register map. +0 Address +1 Address Address H'0080 0790 TOD0_0 Counter (TOD00CT) H'0080 0792 TOD0_0 Reload 1 Register (TOD00RL1) H'0080 0794 TOD0_0 Reload 0 Register (TOD00RL0) H'0080 0796 TID0_1 Counter (TOD01CT)
Page 448 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) +0 Address +1 Address Address H'0080 07C0 TOD0_6 Counter (TOD06CT) H'0080 07C2 H'0080 07C4 TOD0_6 Reload 1 Register (TOD06RL1) H'0080 07C6 TOD0_6 Reload 0 Register (TOD06RL0) TID0_7 Counter (TOD07CT) H'0080 07C8 H'0080 07CA H'0080 07CC TOD0_7 Reload 1 Register (TOD07RL1) TOD0_7 Reload 0 Register (TOD07RL0)
Page 449 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) +0 Address +1 Address Address H'0080 0BB0 TOD1_4 Counter (TOD14CT) H'0080 0BB2 H'0080 0BB4 TOD1_4 Reload 1 Register (TOD14RL1) H'0080 0BB6 TOD1_4 Reload 0 Register (TOD14RL0) H'0080 0BB8 TID1_5 Counter (TOD15CT) H'0080 0BBA TOD1_5 Reload 1 Register (TOD15RL1) H'0080 0BBC TOD1_5 Reload 0 Register (TOD15RL0)
Page 450: Tod Control Registers (Tod0Cr)
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.4 TOD Control Registers (TOD0CR) TOD0 Control Registers (TOD0CR) TOD00M TOD01M TOD02M TOD03M TOD04M TOD05M TOD06M TOD07M Bit Name Function 0, 1 TOD00M 00 : Single-shot output mode (TOD0_0 operation mode selection) 01 :Delayed single-shot output mode 2, 3...
Page 451 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD1 Control Registers (TOD1CR) TOD10M TOD11M TOD12M TOD13M TOD14M TOD15M TOD16M TOD17M Bit Name Function 0, 1 TOD10M 00 : Single-shot output mode (TOD1_0 operation mode selection) 01 :Delayed single-shot output mode 2, 3 TOD11M...
Page 452: Tod Counters
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.5 TOD Counters TOD0_0 Counter (TOD00CT) TOD0_1 Counter (TOD01CT) TOD0_2 Counter (TOD02CT) TOD0_3 Counter (TOD03CT) TOD0_4 Counter (TOD04CT) TOD0_5 Counter (TOD05CT) ...
Page 453 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD1_0 Counter (TOD10CT) TOD1_1 Counter (TOD11CT) TOD1_2 Counter (TOD12CT) TOD1_3 Counter (TOD13CT) TOD1_4 Counter (TOD14CT) TOD1_5 Counter (TOD15CT) ...
Page 454: Tod Reload 0 Registers
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.6 TOD Reload 0 Registers TOD0_0 Reload 0 Register (TOD00RL0) TOD0_1 Reload 0 Register (TOD01RL0) TOD0_2 Reload 0 Register (TOD02RL0) TOD0_3 Reload 0 Register (TOD03RL0) ...
Page 455 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD1_0 Reload 0 Register (TOD10RL0) TOD1_1 Reload 0 Register (TOD11RL0) TOD1_2 Reload 0 Register (TOD12RL0) TOD1_3 Reload 0 Register (TOD13RL0) TOD1_4 Reload 0 Register (TOD14RL0) ...
Page 456: Tod Reload 1 Registers
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.7 TOD Reload 1 Registers TOD0_0 Reload 1 Register (TOD00RL1) TOD0_1 Reload 1 Register (TOD01RL1) TOD0_2 Reload 1 Register (TOD02RL1) TOD0_3 Reload 1 Register (TOD03RL1) ...
Page 457 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD1_0 Reload 1 Register (TOD10RL1) TOD1_1 Reload 1 Register (TOD11RL1) TOD1_2 Reload 1 Register (TOD12RL1) TOD1_3 Reload 1 Register (TOD13RL1) TOD1_4 Reload 1 Register (TOD14RL1) ...
Page 458: Tod Enable Protect Registers
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.8 TOD Enable Protect Registers TOD0 Enable Protect Register (TOD0PRO) TOD00PRO TOD01PRO TOD02PRO TOD03PRO TOD04PRO TOD05PRO TOD06PRO TOD07PRO Bit Name Function TOD00PRO 0 : Enables rewrite (TOD0_0 enable protect) 1 :Disables rewrite TOD01PRO...
Page 459 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD1 Enable Protect Register (TOD1PRO) TOD10PRO TOD11PRO TOD12PRO TOD13PRO TOD14PRO TOD15PRO TOD16PRO TOD17PRO Bit Name Function TOD10PRO 0 : Enables rewrite (TOD1_0 enable protect) 1 :Disables rewrite TOD11PRO (TOD1_1 enable protect) TOD12PRO...
Page 460: Tod Cout Enable Registers
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.9 TOD Cout Enable Registers TOD0 Count Enable Register (TOD0CEN) TOD00CEN TOD01CEN TOD02CEN TOD03CEN TOD04CEN TOD05CEN TOD06CEN TOD07CEN Bit Name Function TOD00CEN 0 : Stops count (TOD0_0 count enable) 1 :Enables count TOD01CEN...
Page 461 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD1 Count Enable Register (TOD0CEN) TOD10CEN TOD11CEN TOD12CEN TOD13CEN TOD14CEN TOD15CEN TOD16CEN TOD17CEN Bit Name Function TOD10CEN 0 : Stops count (TOD1_0 count enable) 1 :Enables count TOD11CEN (TOD1_1 count enable) TOD12CEN...
Page 462 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) TOD0m enable (TOD0mCEN) TOD0m enable control TOD0m enable protect (TOD0mPRO) Figure 10.8.5 Configuration of TOD0 Enable Circuit TID1 enable output enable (TID1EN0) EN-ON TID1 output TOD1m enable (TOD1mCEN) TOD1m enable control TOD1m enable protect (TOD1mPRO) Figure 10.8.6 Configuration of TOD1 Enable Circuit 10-192...
Page 463: Operation In Tod Pwm Output Mode
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.10 Operation in TOD PWM Output Mode (1) Outline of TOD PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start...
Page 464 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit Down-count Down-count Down-count starting starting from starting from from reload 1 register reload 0 register reload 0 register set value set value...
Page 465 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) (2) Reload register updates in TOD PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register.
Page 466 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 Write to reload 1 (reload 1 data latched) H'1000 H'8000 Reload 0 register H'2000 H'9000 Reload 1 register...
Page 467: Operation In Tod Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.11 Operation in TOD Single-shot Output Mode (without Correction Function) (1) Outline of TOD single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation.
Page 468 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Enabled Disabled (by writing to enable bit (by underflow) or by external input) Count clock Enable bit H'FFFF Counts down starting from reload 0 register set value H'A000 Counter H'0000 Reload 0 register H'A000 Reload 1 register (Not used)
Page 469: Operation In Tod Delayed Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.12 Operation in TOD Delayed Single-shot Output Mode (without Correction Function) (1) Outline of TOD delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation.
Page 470 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit H'FFFF H'F000 H'EFFF Down-count starting Down-count from reload 0 register starting from set value counter set value H'A000 Counter...
Page 471: Operation In Tod Continuous Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) 10.8.13 Operation in TOD Continuous Output Mode (Without Correction Function) (1) Outline of TOD continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value.
Page 472 MULTIJUNCTION TIMERS 10.8 TOD (Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (second time) (first time) or by external input) Count clock H'FFFF H'DFFF H'DFFF H'E000 Down-count Down-count Down-count starting from starting from starting from reload 0 register reload 0 register H'A000 counter...
Page 473: Tom (Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9 TOM (Output-related 16-bit Timer) 10.9.1 Outline of TOM TOM (Timer Output Modification) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software. •...
Page 474 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) TOM0_0 TO 37 F/F37 TOM0_1 TO 38 F/F38 F/F39 TOM0_2 TO 39 TOM0_3 F/F40 TO 40 1/2 internal peripheral PSC5 TOM0_4 F/F41 TO 41 clock TOM0_5 F/F42 TO 42 TOM0_6 F/F43 TO 43 TOM0_7 F/F44 TO 44...
Page 475: Outline Of Each Mode Of Tom
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.2 Outline of Each Mode of TOM Each mode of TOM is outlined below. For each TOM channel, only one of the following modes can be selected. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
Page 476 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) (3) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down.
Page 477: Tom Related Register Map
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.3 TOM Related Register Map The diagram below shows a TOM related register map. Address +0 Address +1 Address D7 D8 H'0080 0C90 TOM0_0 Counter (TOM00CT) H'0080 0C92 TOM0_0 Reload 1 Register (TOM00RL1) H'0080 0C94 TOM0_0 Reload 0 Register (TOM00RL0) H'0080 0C96...
Page 478 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Address +0 Address +1 Address D7 D8 TOM0_6 Counter (TOM06CT) H'0080 0CC0 H'0080 0CC2 H'0080 0CC4 TOM0_6 Reload 1 Register (TOM06RL1) H'0080 0CC6 TOM0_6 Reload 0 Register (TOM06RL0) H'0080 0CC8 TOM0_7 Counter (TOM07CT) H'0080 0CCA TOM0_7 Reload 1 Register (TOM07RL1) H'0080 0CCC...
Page 479: Tom Control Registers
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.4 TOM Control Registers TOM0 Control Register (TOM0CR) TOM00M TOM01M TOM02M TOM03M TOM04M TOM05M TOM06M TOM07M Bit Name Function TOM00M 00: Single-shot output mode (TOM0_0 operation mode selection) 01: Single-shot PWM output mode TOM01M 10: Continuous output mode...
Page 480: Tom Counters
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.5 TOM Counters TOM0_0 Counter (TOM00CT) TOM0_1 Counter (TOM01CT) TOM0_2 Counter (TOM02CT) TOM0_3 Counter (TOM03CT) TOM0_4 Counter (TOM04CT) TOM0_5 Counter (TOM05CT) ...
Page 481: Tom Reload 0 Registers
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.6 TOM Reload 0 Registers TOM0_0 Reload 0 Register (TOM00RL0) TOM0_1 Reload 0 Register (TOM01RL0) TOM0_2 Reload 0 Register (TOM02RL0) TOM0_3 Reload 0 Register (TOM03RL0) ...
Page 482: Tom Reload 1 Registers
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.7 TOM Reload 1 Registers TOM0_0 Reload 1 Register (TOM00RL1) TOM0_1 Reload 1 Register (TOM01RL1) TOM0_2 Reload 1 Register (TOM02RL1) TOM0_3 Reload 1 Register (TOM03RL1) ...
Page 483: Tom Enable Protect Registers
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.8 TOM Enable Protect Registers TOM0 Enable Protect Register (TOM0PRO) TOM00PRO TOM01PRO TOM02PRO TOM03PRO TOM04PRO TOM05PRO TOM06PRO TOM07PRO Bit Name Function TOM00PRO 0: Enables rewrite (TOM0_0 enable protect) 1: Disables rewrite TOM01PRO (TOM0_1 enable protect)
Page 484: Tom Count Enable Registers
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.9 TOM Count Enable Registers TOM0 Count Enable Register (TOM0CEN) TOM00CEN TOM01CEN TOM02CEN TOM03CEN TOM04CEN TOM05CEN TOM06CEN TOM07CEN Bit Name Function TOM00CEN 0: Stops count (TOM0_0 count enable) 1: Enables count TOM01CEN (TOM0_1 count enable)
Page 485 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) TID2 enable output enable (TID2EN0) EN-ON TID2 output TOM0m enable (TOM0mCEN) TOM0m enable control TOM0m enable protect (TOM0mPRO) Figure 10.9.4 Configuration of the TOM Enable Circuit 10-215 Ver.0.10...
Page 486: Operation In Tom Pwm Output Mode
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.10 Operation in TOM PWM Output Mode (1) Outline of TOM PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start...
Page 487 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit Down-count Down-count starting from Down-count starting starting from reload 0 register from reload 1 register reload 0 register set value set value...
Page 488 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) (2) Reload register updates in TOM PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register.
Page 489 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 Write to reload 1 (reload 1 data latched) Reload 0 register H'1000 H'8000 Reload 1 register H'2000 H'9000...
Page 490: Operation In Tom Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.11 Operation in TOM Single-shot Output Mode (without Correction Function) (1) Outline of TOM single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation.
Page 491 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Enabled Disabled (by writing to enable bit (by underflow) or by external input) Count clock Enable bit H'FFFF Counts down starting from reload 0 register set value H'A000 Counter H'0000 H'A000 Reload 0 register Reload 1 register (Not used) F/F output...
Page 492: Operation In Tom Single-Shot Pwm Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.12 Operation in TOM Single-shot PWM Output Mode (without Correction Function) (1) Outline of TOM single-shot PWM output mode In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once.
Page 493 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit H'FFFF H'F000 H'EFFF Down-count Down-count starting starting from from reload 1 register reload 0 register set value H'A000 set value...
Page 494: Operation In Tom Continuous Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.13 Operation in TOM Continuous Output Mode (Without Correction Function) (1) Outline of TOM continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value.
Page 495 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) Enabled Underflow Underflow (by writing to enable bit (first time) (second time) or by external input) Count clock Enable bit H'FFFF H'DFFF H'DFFF H'E000 Down-count Down-count Down-count starting from starting from starting from reload 0 register reload 0 register H'A000...
Page 496: Example Application For Using The 32170 In Motor Control
MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) 10.9.14 Example Application for Using the 32170 in Motor Control The 16-bit timer TOM incorporated in the 32170 helps to reduce software burdens during motor control. The following shows an example application for using the 32170 in motor control. The three-phase motor control waveform is materialized by starting TOM in 20 kHz fixed cycles generated by TID2.
Page 497 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) TOM start 20KHz : Shorting prevention time Single-shot Delay TOM(U) Delay TOM(/U) Single-shot TOM(V) TOM(/V) TOM(W) TOM(/W) Figure 10.9.13 Diagram of Control Image 10-227 Ver.0.10...
Page 498 MULTIJUNCTION TIMERS 10.9 TOM (Output-related 16-bit Timer) This is a blank page. 10-228 Ver.0.10...
Page 499: Chapter 11 A-D Converters
CHAPTER 11 A-D CONVERTERS 11.1 Outline of A-D Converters 11.2 A-D Converter Related Registers 11.3 Functional Description of A-D Converters 11.4 Precautions on Using A-D Converters...
Page 500: Outline Of A-D Converter
A-D CONVERTERS 11.1 Outline of A-D Converters 11.1 Outline of A-D Converter The 32170 contains two 10-bit A-D converters of a successive approximation type (A-D0 and A-D1 converters). These converters have 32 analog input pins (channels) AD0IN0 to AD0IN15 and AD1IN0 to AD1IN 15.
Page 501 A-D CONVERTERS 11.1 Outline of A-D Converters Table 11.1.1 outlines the A-D converters. Figures 11.1.1 and 11.1.2 show block diagrams of A-D0 and A-D1 converters, respectively. Table 11.1.1 Outline of A-D Converters Item Content Analog input 16 channels x 2 A-D conversion method Successive approximation method Resolution...
Page 502 A-D CONVERTERS 11.1 Outline of A-D Converters Internal data bus 8-bit readout Shifter 10-bit readout AD0DT0 10-bit A-D0 Data Register 0 AD0DT1 10-bit A-D0 Data Register 1 AD0SIM0,1 A-D0 Single Mode Register AD0DT2 10-bit A-D0 Data Register 2 A-D0 Scan Mode Register AD0SCM0,1 AD0DT3 10-bit A-D0 Data Register 3...
Page 503 A-D CONVERTERS 11.1 Outline of A-D Converters Internal data bus 8-bit readout Shifter 10-bit readout 10-bit A-D1 Data Register 0 AD1DT0 10-bit A-D1 Data Register 1 AD1DT1 AD1SIM0,1 A-D1 Single Mode Register 10-bit A-D1 Data Register 2 AD1DT2 AD1SCM0,1 A-D1 Scan Mode Register 10-bit A-D1 Data Register 3 AD1DT3 10-bit A-D1 Data Register 4...
Page 504: Conversion Modes
A-D CONVERTERS 11.1 Outline of A-D Converters 11.1.1 Conversion Modes The A-D converters have two conversion modes: "A-D conversion mode" and "Comparator mode." (1) A-D conversion mode In A-D conversion mode, the analog input voltage in a specified channel is converted into digital quantity.
Page 505: Operation Modes
A-D CONVERTERS 11.1 Outline of A-D Converters 11.1.2 Operation Modes The A-D converters operate in two modes: "Single mode" and "Scan mode." (1) Single mode In single mode, the analog input voltage in one selected channel is A-D converted once or comparated with a given quantity.
Page 506 A-D CONVERTERS 11.1 Outline of A-D Converters (2) Scan mode In scan mode, analog input voltages in multiple selected channels (4, 8, or 16 channels) are sequentially A-D converted. There are two types of scan modes: "Single-shot scan mode" in which A-D conversion is completed by performing one cycle of scan operation, and "Continuous scan mode"...
Page 507 A-D CONVERTERS 11.1 Outline of A-D Converters <8-channel scan> During continuous scan mode Conversion ADiIN0 ADiIN1 ADiIN2 ADiIN3 starts (Note 1) 10-bit A-Di data register ADiDT0 ADiDT1 ADiDT2 ADiDT3 Completed here when ADiIN4 ADiIN5 ADiIN6 ADiIN7 operating in single-shot scan mode ADiDT4 ADiDT5 ADiDT6...
Page 508 A-D CONVERTERS 11.1 Outline of A-D Converters Table 11.1.2 Registers in Which Scan Mode A-D Conversion Results Are Stored Scan loop Selected channels Selected channels A-D conversion result selection for single-shot scan for continue scan storage register 4-channel scan ADiIN0 ADiIN0 10-bit A-Di Data Register 0 ADiIN1...
Page 509: Special Operation Modes
A-D CONVERTERS 11.1 Outline of A-D Converters 11.1.3 Special Operation Modes (1) Forcible single mode execution during scan mode This special operation mode forcibly executes single mode conversion (A-D conversion or comparate) in a specified channel during scan mode operation. For A-D conversion mode, the conversion result is stored in the 10-bit A-D Data Register corresponding to the specified channel.
Page 510 A-D CONVERTERS 11.1 Outline of A-D Converters (2) Scan mode start after single mode execution This special operation mode starts scan operation subsequently after executing conversion in single mode (A-D conversion or comparate). To start this mode in software, choose a software trigger using the Scan Mode Register 0 A-D conversion start trigger select bit.
Page 511 A-D CONVERTERS 11.1 Outline of A-D Converters (3) Conversion restart This special operation mode stops operation being executed in single mode or scan mode and reexecutes the operation from the beginning. When in single mode, set the Single Mode Register 0 A-D conversion start bit to 1 again or enter ____________ ____________ a hardware trigger (ADTRG signal or output event bus 3 for the A-D0 converter, or ADTRG signal...
Page 512: A-D Converter Interrupt And Dma Transfer Requests
A-D CONVERTERS 11.1 Outline of A-D Converters 11.1.4 A-D Converter Interrupt and DMA Transfer Requests The A-D converters can generate an A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) each time A-D conversion, comparate operation, single-shot scan, or one cycle of continuous scan mode is completed.
Page 513: A-D Converter Related Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2 A-D Converter Related Registers The diagrams below show an A-D converter related register map. Address +0 Address +1 Address A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 H'0080 0080 (AD0SIM0) (AD0SIM1) H'0080 0082 A-D0 Scan Mode Register 0...
Page 514 A-D CONVERTERS 11.2 A-D Converter Related Registers Address +0 Address +1 Address 8-bit A-D0 Data Register 0 H'0080 00D0 (AD08DT0) 8-bit A-D0 Data Register 1 H'0080 00D2 (AD08DT1) 8-bit A-D0 Data Register 2 H'0080 00D4 (AD08DT2) 8-bit A-D0 Data Register 3 H'0080 00D6 (AD08DT3) 8-bit A-D0 Data Register 4...
Page 515 A-D CONVERTERS 11.2 A-D Converter Related Registers Address +0 Address +1 Address A-D1 Single Mode Register 0 A-D1 Single Mode Register 1 H'0080 0A80 (AD1SIM0) (AD1SIM1) H'0080 0A82 A-D1 Scan Mode Register 0 A-D1 Scan Mode Register 1 H'0080 0A84 (AD1SCM0) (AD1SCM1) H'0080 0A86...
Page 516 A-D CONVERTERS 11.2 A-D Converter Related Registers Address +0 Address +1 Address 8-bit A-D1 Data Register 0 H'0080 0AD0 (AD18DT0) 8-bit A-D1 Data Register 1 H'0080 0AD2 (AD18DT1) 8-bit A-D1 Data Register 2 H'0080 0AD4 (AD18DT2) 8-bit A-D1 Data Register 3 H'0080 0AD6 (AD18DT3) 8-bit A-D1 Data Register 4...
Page 517: A-D Single Mode Register 0
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.1 A-D Single Mode Register 0 A-D0 Single Mode Register 0 (AD0SIM0) AD0STRG AD0SSEL AD0SREQ AD0SCMP AD0SSTP AD0SSTT Bit Name Function No functions assigned – __________ AD0STRG 0: ADTRG signal input (A-D0 hardware trigger selection) 1: Output event bus 3 AD0SSEL...
Page 518 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Single Mode Register 0 (AD1SIM0) AD1STRG AD1SSEL AD1SREQ AD1SCMP AD1SSTP AD1SSTT Bit Name Function No functions assigned – __________ AD1STRG 0: ADTRG signal input (A-D1 hardware trigger selection) 1: TID1 overflow/underflow AD1SSEL 0: Software trigger...
Page 519 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnSTRG (A-Dn hardware trigger selection) bit (D2) When starting A-D conversion of the A-Dn converter in hardware, this bit selects whether to use external ADTRG signal input or MJT output (output event bus 3 for A-D0, or TID1 overflow/ underflow for A-D1) to start the operation.
Page 520 A-D CONVERTERS 11.2 A-D Converter Related Registers (6) ADnSSTT (A-Dn conversion start) bit (D7) When this bit is set to 1 while a software trigger has been selected by the ADnSSEL (A-Dn conversion start trigger selection) bit, the A-Dn converter starts A-D conversion. If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the A- Dn conversion stop bit has priority.
Page 521: A-D Single Mode Register 1
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.2 A-D Single Mode Register 1 A-D0 Single Mode Register 1 (AD0SIM1) AD0SMSL AD0SSPD AN0SEL Bit Name Function AD0SMSL 0: A-D0 conversion mode (A-D0 conversion mode selection) 1: Comparator mode AD0SSPD 0: Normal rate (A-D0 conversion rate selection)
Page 522 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Single Mode Register 1 (AD1SIM1) AD1SMSL AD1SSPD AN1SEL Bit Name Function AD1SMSL 0: A-D1 conversion mode (A-D1 conversion mode selection) 1: Comparator mode AD1SSPD 0: Normal rate (A-D1 conversion rate selection) 1: Double rate 10,11...
Page 523 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnSMSL (A-Dn conversion mode selection) bit (D8) This bit selects A-D conversion mode for the A-Dn converter during single mode. Setting this bit to 0 selects A-D conversion mode, and setting this bit to 1 selects comparator mode. (2) ADnSSPD (A-Dn conversion rate selection) bit (D9) This bit selects an A-D conversion rate for the A-Dn converter during single mode.
Page 524: A-D Scan Mode Register 0
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.3 A-D Scan Mode Register 0 A-D0 Scan Mode Register 0 (AD0SCM0) AD0CMSL AD0CTRG AD0CSEL AD0CREQ AD0CCMP AD0CSTP AD0CSTT Bit Name Function No functions assigned – AD0CMSL 0: Single-shot mode (A-D0 scan mode selection) 1: Continuous mode _________...
Page 525 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Scan Mode Register 0 (AD1SCM0) AD1CMSL AD1CTRG AD1CSEL AD1CREQ AD1CCMP AD1CSTP AD1CSTT Bit Name Function No functions assigned – AD1CMSL 0: Single-shot mode (A-D1 scan mode selection) 1: Continuous mode _________ AD1CTRG...
Page 526 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnCMSL (A-Dn scan mode selection) bit (D1) This bit selects scan mode of the A-Dn converter between single-shot scan and continuous scan. Setting this bit to 0 selects single-shot scan mode, so that the channels selected by the ANnSCAN (scan loop selection) bits are sequentially A-D converted and when A-D conversion in all selected channels are completed, the conversion operation stops.
Page 527 A-D CONVERTERS 11.2 A-D Converter Related Registers (6) ADnCSTP (A-Dn conversion stop) bit (D6) Scan mode A-D conversion of the A-Dn converter can be halted by setting this bit to 1 while the operation is in progress. This bit is effective only when operating in scan mode. If single mode and scan mode both are active in special operation mode, manipulation of this bit does not affect single mode operation.
Page 528: A-D Scan Mode Register 1
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.4 A-D Scan Mode Register 1 A-D0 Scan Mode Register 1 (AD0SCM1) AD0CSPD AN0SCAN Bit Name Function No functions assigned – AD0CSPD 0: Normal (A-D0 conversion rate selection) 1: x2 10,11 No functions assigned...
Page 529 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Scan Mode Register 1 (AD1SCM1) AD1CSPD AN1SCAN Bit Name Function No functions assigned – AD1CSPD 0: Normal (A-D1 conversion rate selection) 1: x2 10,11 No functions assigned –...
Page 530 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnCSPD (A-Dn conversion rate selection) bit (D9) This bit selects an A-D conversion rate for the A-Dn converter during scan mode. Setting this bit to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed (two times normal speed). (2) ANnSCAN (A-Dn scan loop selection) bits (D12-D15) The ANnSCAN (A-Dn scan loop selection) bits set the channels to be scanned during scan mode of the A-Dn converter.
Page 531: A-D Successive Approximation Register
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.5 A-D Successive Approximation Register A-D0 Successive Approximation Register (AD0SAR) AD0SAR Bit Name Function No functions assigned – 6-15 AD0SAR • A-D successive approximation value (A-D0 successive approximation (A-D conversion mode) value/comparison value) •...
Page 532 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Successive Approximation Register (AD1SAR) AD1SAR Bit Name Function No functions assigned – 6-15 AD1SAR • A-D successive approximation value (A-D1 successive approximation (A-D conversion mode) value/comparison value) •...
Page 533: A-D0 Comparate Data Register
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.6 A-D0 Comparate Data Register A-D0 Comparate Data Register (AD0CMP) CMP0 CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP8 CMP9 CMP10 CMP11 CMP12 CMP13 CMP14 CMP15 Bit Name Function 0-15 AD0CMP0-AD0CMP15 (Note 2)
Page 534 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Comparate Data Register (AD1CMP) CMP0 CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP8 CMP9 CMP10 CMP11 CMP12 CMP13 CMP14 CMP15 Bit Name Function 0-15 AD1CMP0-AD1CMP15 (Note 2) 0: Analog input voltage >...
Page 535: 10-Bit A-D Data Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.7 10-bit A-D Data Registers 10-bit A-D0 Data Register 0 (AD0DT0) 10-bit A-D0 Data Register 1 (AD0DT1) 10-bit A-D0 Data Register 2 (AD0DT2) 10-bit A-D0 Data Register 3 (AD0DT3) ...
Page 536 A-D CONVERTERS 11.2 A-D Converter Related Registers 10-bit A-D1 Data Register 0 (AD1DT0) 10-bit A-D1 Data Register 1 (AD1DT1) 10-bit A-D1 Data Register 2 (AD1DT2) 10-bit A-D1 Data Register 3 (AD1DT3) ...
Page 537: 8-Bit A-D Data Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.8 8-bit A-D Data Registers 8-bit A-D0 Data Register 0 (AD08DT0) 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 3 (AD08DT3) ...
Page 538 A-D CONVERTERS 11.2 A-D Converter Related Registers 8-bit A-D1 Data Register 0 (AD18DT0) 8-bit A-D1 Data Register 1 (AD18DT1) 8-bit A-D1 Data Register 2 (AD18DT2) 8-bit A-D1 Data Register 3 (AD18DT3) ...
Page 539: Functional Description Of A-D Converters
A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3 Functional Description of A-D Converters 11.3.1 How to Find Along Input Voltages The A-D converters use a 10-bit successive approximation method, and find the actual analog input voltage from the value (digital quantity) obtained through execution of A-D conversion by performing the following calculation.
Page 540: A-D Conversion By Successive Approximation Method
A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3.2 A-D Conversion by Successive Approximation Method The A-D converter has A-D convert operation started by an A-D conversion start trigger (in software or hardware). Once A-D conversion begins, the following operation is automatically executed. During single mode, Single Mode Register 0's A-D conversion/comparate completion bit is cleared to 0.
Page 541 A-D CONVERTERS 11.3 Functional Description of A-D Converters The comparison result finally is stored in the 10-bit A-D Data Register (AD0DTn, AD1DTn) corresponding to each converted channel. Also, the 8-bit A-D Data Register (AD08DTn, AD18DTn) contains the 8 high-order bits of the 10-bit A-D conversion result. The following shows the procedure for A-D conversion by successive approximation in each operation mode.
Page 542: Comparator Operation
A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3.3 Comparator Operation When comparator mode (single mode only) is selected, the A-D converter functions as a comparator that compares analog input voltages with a preset comparison voltage. When a comparison value is written to the successive approximation register, the A-D converter starts 'comparating' the analog input voltage selected by the Single Mode Register 1 analog input selection bit with the value written to the successive approximation register.
Page 543: Calculation Of The A-D Conversion Time
A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3.4 Calculation of the A-D Conversion Time The A-D conversion time is expressed by the sum of dummy cycle time and the actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. Start dummy time A time from when the CPU executed the A-D conversion start instruction to when the A-D converter starts A-D conversion...
Page 544 A-D CONVERTERS 11.3 Functional Description of A-D Converters Transferred to A-D Convert operation conversion Completed data register begins start trigger Start dummy Execution cycle End dummy (Channel 0) (Channel 1) Scan to scan Start dummy Execution cycle Execution cycle dummy (Last channel)
Page 545 A-D CONVERTERS 11.3 Functional Description of A-D Converters Table 11.3.2 Total A-D Conversion Time Conversion started by Conversion rate Conversion mode (Note 1) Conversion time [BCLK] Software trigger Normal Single mode (Note 2) Single-shot scan 4-channel scan 1193 /Continuous 8-channel scan 2385 16-channel scan 4769...
Page 546: Definition Of The A-D Conversion Accuracy
A-D CONVERTERS 11.3 Functional Description of A-D Converters 11.3.5 Definition of the A-D Conversion Accuracy The following defines the A-D conversion accuracy. (1) Resolution ....Number of digital converted codes output by the A-D converter (2) Nonlinearity error ..Deviation from ideal conversion characteristics after the offset and full- scale errors are adjusted to 0.
Page 547 A-D CONVERTERS 11.3 Functional Description of A-D Converters Full scale Nonlinearity error Actual A-D conversion characteristic that contains nonlinearity error Ideal conversion line Full scale Along input level Figure 11.3.5 A-D Converter's Nonlinearity Error Full scale Conversion line offset to the positive side Ideal conversion line Conversion line offset...
Page 548 A-D CONVERTERS 11.3 Functional Description of A-D Converters Full scale Conversion line where the output code reaches the full scale for analog inputs lower than the fullscale Full-scale error Ideal conversion line Conversion line where the output code does not reach the full scale even for full-scale equivalent analog inputs Full scale...
Page 549: Precautions On Using A-D Converters
A-D CONVERTERS 11.4 Precautions on Using A-D Converters 11.4 Precautions on Using A-D Converters • Forcible termination during scan operation If A-D conversion is halted by setting the A-D conversion stop bit (AD0CSTP, AD1CSTP) to 1 during scan mode operation and you read the content of the A-D data register for the channel in which conversion was in progress, it shows the last conversion result that had been transferred to the A-D data register before the conversion was forcibly terminated.
Page 550 A-D CONVERTERS 11.4 Precautions on Using A-D Converters * This is a blank page. * 11-52 Ver.0.10...
Page 551: Chapter 12 Serial I/O
CHAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O 12.2 Serial I/O Related Registers 12.3 Transmit Operation in CSIO Mode 12.4 Receive Operation in CSIO Mode 12.5 Precautions on Using CSIO Mode 12.6 Transmit Operation in UART Mode 12.7 Receive Operation in UART Mode 12.8 Fixed Period Clock Output Function 12.9 Precautions on Using UART...
Page 552 SERIAL I/O 12.1 Outline of Serial I/O 12.1 Outline of Serial I/O The 32170 contains a total of six channels of serial I/O-SIO0, SIO1, SIO2, SIO3, SIO4, and SIO5. SIO0, SIO1, SIO4, and SIO5 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (asynchronous serial I/O).
Page 553 SERIAL I/O 12.1 Outline of Serial I/O Table 12.1.1 Outline of Serial I/O Item Content Number of channels CSIO/UART : 4 channels (SIO0, SIO1, SIO4, SIO5) UART only : 2 channels (SIO2, SIO3) Clock During CSIO mode : Internal clock or external clock as selected (Note 1) During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex...
Page 554 SERIAL I/O 12.1 Outline of Serial I/O Table 12.1.2 Serial I/O Interrupt Request Generation Function Serial I/O Interrupt Request ICU Interrupt Cause SIO0 transmit buffer empty interrupt SIO0 transmit interrupt SIO0 receive-finished SIO0 receive interrupt or receive error interrupt (selectable) SIO1 transmit buffer empty interrupt SIO1 transmit interrupt SIO1 receive-finished...
Page 555 SERIAL I/O 12.1 Outline of Serial I/O SIO0 SIO0 Transmit Buffer Register Transmit interrupt To interrupt TXD0 SIO0 Transmit Shift Register Receive interrupt controller Transmit/receive control circuit Transmit DMA transfer request To DMAC3 SIO0 Receive Shift Register RXD0 Receive DMA transfer request To DMAC4 SIO0 Receive Buffer Register UART...
Page 556 SERIAL I/O 12.2 Serial I/O Related Registers 12.2 Serial I/O Related Registers The diagram below shows a serial I/O related register map. +0 Address +1 Address Address SIO23 Interrupt Status Register SIO03 Interrupt Mask Register H'0080 0100 (SI23STAT) (SI03MASK) SIO03 Cause of Receive Interrupt H'0080 0102 Select Register (SI03SEL) SIO0 Transmit Control Register...
Page 557: Sio Interrupt Related Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.1 SIO Interrupt Related Registers (1) Selecting the cause of interrupt Interrupt signals sent from each SIO to the ICU (Interrupt Controller) are broadly classified into transmit interrupts and receive interrupts. Transmit interrupts are generated when the transmit buffer is empty.
Page 558 SERIAL I/O 12.2 Serial I/O Related Registers • Receive-finished DMA transfer request DMA transfer request is generated when the receive buffer is filled. RFIN (receive-completed bit) Receive DMA transfer request Note : When a receive error occurs, no receive-finished DMA transfer requests are generated. Figure 12.2.3 Receive-finished DMA Transfer Request 12-8 Ver.0.10...
Page 559: Sio Interrupt Control Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.2 SIO Interrupt Control Registers SIO23 Interrupt Status Register (SI23STAT) IRQT2 IRQR2 IRQT3 IRQR3 Bit Name Function 0 - 3 No functions assigned — IRQT2 (SIO2 transmit-finished 0 : Interrupt not requested interrupt request status bit) 1 : Interrupt requested IRQR2 (SIO2 receive interrupt...
Page 560 SERIAL I/O 12.2 Serial I/O Related Registers SIO45 Interrupt Status Register (SI45STAT) IRQT4 IRQR4 IRQT5 IRQR5 Bit Name Function IRQT4 (SIO4 transmit-finished 0 : Interrupt not requested interrupt request status bit) 1 : Interrupt requested IRQR4 (SIO4 receive interrupt 0 : Interrupt not requested request status bit)
Page 561 SERIAL I/O 12.2 Serial I/O Related Registers SIO03 Interrupt Mask Register (SI03MASK) T0MASK R0MASK T1MASK R1MASK T2MASK R2MASK T3MASK R3MASK Bit Name Function T0MASK (SIO0 transmit 0 : Masks (disables) interrupt request interrupt mask bit) 1 : Enables interrupt request R0MASK (SIO0 receive 0 : Masks (disables) interrupt request...
Page 562 SERIAL I/O 12.2 Serial I/O Related Registers SIO45 Interrupt Mask Register (SI45MASK) T4MASK R4MASK T5MASK R5MASK Bit Name Function T4MASK (SIO4 transmit 0 : Masks (disables) interrupt request interrupt mask bit) 1 : Enables interrupt request R4MASK (SIO4 receive 0 : Masks (disables) interrupt request interrupt mask bit)
Page 563 SERIAL I/O 12.2 Serial I/O Related Registers SIO03 Cause of Receive Interrupt Select Register (SI03SEL) ISR0 ISR1 ISR2 ISR3 Bit Name Function 0 - 3 No functions assigned — ISR0 (SIO0 receive interrupt 0 : Receive-finished interrupt cause select bit) 1 : Receive error interrupt...
Page 564 SERIAL I/O 12.2 Serial I/O Related Registers SIO45 Cause of Receive Interrupt Select Register (SI45SEL) ISR4 ISR5 Bit Name Function 0 - 3 No functions assigned — ISR4 (SIO4 receive interrupt 0 : Receive-finished interrupt cause select bit) 1 : Receive error interrupt ISR5 (SIO5 receive interrupt...
Page 565 SERIAL I/O 12.2 Serial I/O Related Registers TXD2 Data bus 4-source inputs IRQT2 SIO2,3 transmit/receive T2MASK (Level) interrupts RXD2 receive-finished RXD2 receive error IRQR2 ISR2 R2MASK TXD3 IRQT3 T2MASK RXD3 receive-finished RXD3 receive error IRQR3 ISR3 R2MASK...
Page 566: Sio Transmit Control Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.3 SIO Transmit Control Registers SIO0 Transmit Control Register (S0TCNT) SIO1 Transmit Control Register (S1TCNT) SIO2 Transmit Control Register (S2TCNT) SIO3 Transmit Control Register (S3TCNT) ...
Page 567 SERIAL I/O 12.2 Serial I/O Related Registers (1) CDIV (baud rate generator count source select) bits (D2, D3) These bits select the count source for the baud rate generator (BRG). Note : If f(BCLK) is selected as the count source for the BRG, make sure when you set BRG that the baud rate will not exceed the maximum transfer rate.
Page 568: Sio Transmit/Receive Mode Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.4 SIO Transmit/Receive Mode Registers SIO0 Mode Register (S0MOD) SIO1 Mode Register (S1MOD) SIO2 Mode Register (S2MOD) SIO3 Mode Register (S3MOD) SIO4 Mode Register (S4MOD) ...
Page 569 SERIAL I/O 12.2 Serial I/O Related Registers The SIO Mode Register consists of bits to set the serial I/O operation mode, data format, and the functions used during communication. The SIO Transmit/Receive Mode Register must always be set before serial I/O starts operating. If you want to change settings of this register after the serial I/O started transmitting or receiving data, be sure to confirm that transmit and receive operations have been completed and disable transmit/ receive operations (by clearing the SIO Transmit Control Register transmit enable bit and SIO...
Page 570 SERIAL I/O 12.2 Serial I/O Related Registers ST : Start bit PAR : Parity bit : One frame equivalent D : Data bit : Stop bit Direction of transfer Clock-synchronous mode Note 1 Note 2 7-bit UART mode D0 PAR SP Note 1 Note 2 D0 PAR 8-bit UART mode...
Page 571 SERIAL I/O 12.2 Serial I/O Related Registers 12.2.5 SIO Transmit Buffer Registers SIO0 Transmit Buffer Register (S0TXB) SIO1 Transmit Buffer Register (S1TXB) SIO2 Transmit Buffer Register (S2TXB) SIO3 Transmit Buffer Register (S3TXB) ...
Page 572: Sio Receive Buffer Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.6 SIO Receive Buffer Registers SIO0 Receive Buffer Register (S0RXB) SIO1 Receive Buffer Register (S1RXB) SIO2 Receive Buffer Register (S2RXB) SIO3 Receive Buffer Register (S3RXB) ...
Page 573: Sio Receive Control Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.7 SIO Receive Control Registers SIO0 Receive Control Register (S0RCNT) SIO1 Receive Control Register (S1RCNT) SIO2 Receive Control Register (S2RCNT) SIO3 Receive Control Register (S3RCNT) ...
Page 574 SERIAL I/O 12.2 Serial I/O Related Registers (1) RSTAT (receive status) bit (D1) [Set condition] This bit is set to 1 by a start of receive operation. When this bit = 1, it means that the serial I/O is receiving data. [Clear condition] This bit is cleared to 0 upon completion of receive operation or by clearing the REN (receive enable) bit.
Page 575 SERIAL I/O 12.2 Serial I/O Related Registers (5) PTY (parity error) bit (D5) This bit is effective in only UART mode. During CSIO mode, this bit is fixed to 0. [Set condition] The PTY (parity error) bit is set to 1 when the SIO Transmit/Receive Mode Register's PEN (parity enable/disable) bit is enabled and the parity (even/odd) of the receive data does not agree with the value that has been set by the said register's PSEL bit (parity select) bit.
Page 576: Sio Baud Rate Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.8 SIO Baud Rate Registers SIO0 Baud Rate Register (S0BAUR) SIO1 Baud Rate Register (S1BAUR) SIO2 Baud Rate Register (S2BAUR) SIO3 Baud Rate Register (S3BAUR) ...
Page 577 SERIAL I/O 12.2 Serial I/O Related Registers In UART mode, the serial I/O divides the internal BCLK using the clock divider. Next, it divides the resulting clock by (BRG set value + 1) according to the BRG set value and then by 16, which results in generating a transmit/receive shift clock.
Page 578: Transmit Operation In Csio Mode
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3 Transmit Operation in CSIO Mode 12.3.1 Setting the CSIO Baud Rate The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which to generate the transmit/receive shift clock is selected from the internal clock f(BCLK) or external clock.
Page 579: Initial Settings For Csio Transmission
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.2 Initial Settings for CSIO Transmission To transmit data in CSIO mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to CSIO mode •...
Page 580 SERIAL I/O 12.3 Transmit Operation in CSIO Mode Initial settings for CSIO transmission • Set register to CSIO mode Set SIO Transmit/Receive Mode Register • Select internal or external clock Set SIO Transmit Control Register • Select clock divider's divide-by ratio (Note 1) Serial I/O related...
Page 581: Starting Csio Transmission
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.3 Starting CSIO Transmission When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. (1) Transmit conditions when CSIO mode internal clock is selected •...
Page 582: Processing At End Of Csio Transmission
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.5 Processing at End of CSIO Transmission When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively • The transmit status bit is set to 0. (2) When transmitting successively •...
Page 583 SERIAL I/O 12.3 Transmit Operation in CSIO Mode The following processing is automatically executed in hardware CSIO transmit operation starts Transmit conditions met? (Note) Transmit interrupt request • Transfer content of transmit buffer to transmit shift register Transmit DMA • Set transmit buffer empty bit to 1 transfer request Transmit data Transmit...
Page 584: Typical Csio Transmit Operation
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.8 Typical CSIO Transmit Operation The following shows a typical transmit operation in CSIO mode. SCLKO SCLKI Internal clock selected External clock selected Transmit clock (SCLKO) Transmit enable bit...
Page 585 SERIAL I/O 12.3 Transmit Operation in CSIO Mode SCLKO SCLKI Internal clock selected External clock selected Transmit clock (SCLKO) Transmit enable bit Write to Write to Cleared transmit transmit buffer buffer...
Page 586: Receive Operation In Csio Mode
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4 Receive Operation in CSIO Mode 12.4.1 Initial Settings for CSIO Reception To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however, that because the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation even when you only want to receive data.
Page 587 SERIAL I/O 12.4 Receive Operation in CSIO Mode (8) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") Initial settings for CSIO reception •...
Page 588: Starting Csio Reception
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.2 Starting CSIO Reception When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. (1) Receive conditions when CSIO mode internal clock is selected •...
Page 589: About Successive Reception
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.4 About Successive Reception When the following conditions are met at completion of data reception, data may be received successively. • The receive enable bit is set to 1. • Transmit conditions are met. •...
Page 590: Flags Indicating The Status Of Csio Receive Operation
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.5 Flags Indicating the Status of CSIO Receive Operation Following flags are available that indicate the status of receive operation in CSIO mode. • SIO Receive Control Register receive status bit • SIO Receive Control Register receive-finished bit •...
Page 591: Typical Csio Receive Operation
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.6 Typical CSIO Receive Operation The following shows a typical receive operation in CSIO mode. SCLKO SCLKI Internal clock selected External clock selected Receive clock Clock stopped (SCLKI)
Page 592 SERIAL I/O 12.4 Receive Operation in CSIO Mode SCLKO SCLKI Internal clock selected External clock selected Transmit clock (SCLKO) Cleared First data reception Next data reception Receive enable bit completed completed Receive buffer not read...
Page 593: Precautions On Using Csio Mode
SERIAL I/O 12.5 Precautions on Using CSIO Mode 12.5 Precautions on Using CSIO Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating.
Page 594 SERIAL I/O 12.5 Precautions on Using CSIO Mode • About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data.
Page 595: Transmit Operation In Uart Mode
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6 Transmit Operation in UART Mode 12.6.1 Setting the UART Baud Rate The baud rate (data transfer rate) during UART mode is determined by a transmit/receive shift clock. In UART mode, the source for this transmit/receive shift clock is always the internal clock regardless of how the internal/external clock select bit (SIO Transmit/Receive Mode Register bit D11) is set.
Page 596: Uart Transmit/Receive Data Formats
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.2 UART Transmit/Receive Data Formats The transmit/receive data format during UART mode is determined by setting the SIO Transmit/ Receive Mode Register. Shown below is the transmit/receive data format that can be used in UART mode.
Page 597 SERIAL I/O 12.6 Transmit Operation in UART Mode 7-bit characters 8-bit characters 9-bit characters ST : Start bit D0 - D7 : Character (data) bits PAR : Parity bit SIO Transmit Buffer Register SP : Stop bit SIO Receive Buffer Register D7 D8 7-bit characters 8-bit characters...
Page 598: Initial Settings For Uart Transmission
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.3 Initial Settings for UART Transmission To transmit data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to UART mode •...
Page 599 SERIAL I/O 12.6 Transmit Operation in UART Mode Initial settings for UART transmission • Set register to UART mode • Set parity (when enabled, select odd/even) Set SIO Transmit/Receive Mode Register • Set stop bit length • Set character length Set SIO Transmit Control Register •...
Page 600: Starting Uart Transmission
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.4 Starting UART Transmission When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. • The SIO Transmit Control Register's TEN (transmit enable) bit is set to 1. (Note) •...
Page 601: Processing At End Of Uart Transmission
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.6 Processing at End of UART Transmission When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively • The transmit status bit is set to 0. (2) When transmitting successively •...
Page 602 SERIAL I/O 12.6 Transmit Operation in UART Mode The following processing is automatically executed in hardware UART transmit operation starts Transmit conditions met? (Note) Transmit interrupt request • Transfer content of transmit buffer to transmit shift register Transmit DMA • Set transmit buffer empty bit to 1 transfer request Transmit data Transmit...
Page 603: Transmit Interrupt
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.9 Typical UART Transmit Operation The following shows a typical transmit operation in CSIO mode. Transmit enable bit Write to transmit Cleared buffer register...
Page 604 SERIAL I/O 12.6 Transmit Operation in UART Mode Transmit enable bit Write to Write to Cleared transmit transmit buffer buffer register register (First data) (Next data) Transmit buffer empty bit Cleared when transmission Transferred from...
Page 605: Receive Operation In Uart Mode
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7 Receive Operation in UART Mode 12.7.1 Initial Settings for UART Reception To receive data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register •...
Page 606 SERIAL I/O 12.7 Receive Operation in UART Mode Initial settings for UART reception • Set register to UART mode • Set parity (when enabled, select odd/even) Set SIO Transmit/Receive Mode Register • Set stop bit length • Set character length Set SIO Transmit Control Register •...
Page 607: Starting Uart Reception
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.2 Starting UART Reception When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. • The SIO Receive Control Register's receive enable bit is set to 1 •...
Page 608 SERIAL I/O 12.7 Receive Operation in UART Mode The following processing is automatically executed in hardware UART receive operation starts Transmit conditions met? Start bit detected normally? Set receive status bit to 1 Receive data Overrun error? Transfer data from SIO Receive Shift Register to SIO Receive Buffer Register Set SIO Receive Control Register's overrun error bit...
Page 609: Typical Uart Receive Operation
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.4 Typical UART Receive Operation The following shows a typical receive operation in UART mode. Internal clock selected Receive enable bit (SIO Receive Control Register) Cleared...
Page 610 SERIAL I/O 12.7 Receive Operation in UART Mode Receive enable bit First data reception Next data reception (SIO Receive completed completed Control Register) Receive buffer not read during this interval Receive-finished bit (Note 5) Overrun error bit...
Page 611: Fixed Period Clock Output Function
SERIAL I/O 12.8 Fixed Period Clock Output Function 12.8 Fixed Period Clock Output Function When using SIO0, SIO1, SIO4 or SIO5 in UART mode, you can choose the relevant port (P84, P87, P65 or P66) to function as the SCLKO0, SCLKO1, SCLKO4 or SCLKO5 pin. In this way, a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin.
Page 612: Precautions On Using Uart Mode
SERIAL I/O 12.9 Precautions on Using UART Mode 12.9 Precautions on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating.
Page 613 SERIAL I/O 12.9 Precautions on Using UART Mode • Flags indicating the status of UART receive operation Following flags are available that indicate the status of receive operation during UART mode. • SIO Receive Control Register receive status bit • SIO Receive Control Register receive-finished bit •...
Page 614 SERIAL I/O 12.9 Precautions on Using UART Mode * This is a blank page.* 12-64 Ver.0.10...
Page 615: Chapter 13 Can Module
CHAPTER 13 CHAPTER 13 CAN MODULE 13.1 Outline of the CAN Module 13.2 CAN Module Related Registers 13.3 CAN Protocol 13.4 Initializing the CAN Module 13.5 Transmitting Data Frames 13.6 Receiving Data Frames 13.7 Transmitting Remote Frames 13.8 Receiving Remote Frames...
Page 616 CAN MODULE 13.1 Outline of the CAN Module 13.1 Outline of the CAN Module The M32R/E contains CAN (Controller Area Network) Specification 2.0B-compliant Full CAN module. This module has 16 message slots and three mask registers, effective use of which helps to reduce the CPU load for data processing.
Page 617 CAN MODULE 13.1 Outline of the CAN Module Table 13.1.2 CAN Module Interrupt Generation Function CAN module interrupt source ICU interrupt source CAN0 transmit complete interrupt CAN0 group interrupt CAN0 receive complete interrupt CAN0 group interrupt CAN0 bus error interrupt CAN0 group interrupt CAN0 error passive interrupt CAN0 group interrupt...
Page 618 CAN MODULE 13.2 CAN Module Related Registers 13.2 CAN Module Related Registers The diagram below shows a CAN module related register map. Address +0 Address +1 Address D7 D8 H'0080 1000 CAN0 Control Register (CAN0CNT) H'0080 1002 CAN0 Status Register (CAN0STAT) H'0080 1004 CAN0 Extended ID Register (CAN0EXTID) H'0080 1006...
Page 619 CAN MODULE 13.2 CAN Module Related Registers Address +0 Address +1 Address D7 D8 H'0080 1100 CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) H'0080 1102 CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) H'0080 1104 CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2)
Page 620 CAN MODULE 13.2 CAN Module Related Registers Address +0 Address +1 Address D7 D8 CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) H'0080 1154 H'0080 1156 CAN0 Message Slot 5 Data 0 (C0MSL5DT0) CAN0 Message Slot 5 Data 1 (C0MSL5DT1) CAN0 Message Slot 5 Data 2 (C0MSL5DT2) CAN0 Message Slot 5 Data 3 (C0MSL5DT3)
Page 621 CAN MODULE 13.2 CAN Module Related Registers Address +0 Address +1 Address D7 D8 H'0080 11A8 CAN0 Message Slot 10 Data 2 (C0MSL10DT2) CAN0 Message Slot 10 Data 3 (C0MSL10DT3) H'0080 11AA CAN0 Message Slot 10 Data 4 (C0MSL10DT4) CAN0 Message Slot 10 Data 5 (C0MSL10DT5) H'0080 11AC CAN0 Message Slot 10 Data 6 (C0MSL10DT6) CAN0 Message Slot 10 Data 7 (C0MSL10DT7)
Page 622: Can Control Register
CAN MODULE 13.2 CAN Module Related Registers 13.2.1 CAN Control Register CAN0 Control Register (CAN0CNT) RBO TSR FRST BCM LBM RST Bit Name Function No functions assigned – 0: Enables normal operation (Return bus off) 1: Requests clearing of error counter 0: Enables count operation (Time stamp Counter reset) 1: Initializes count (by setting H'0000)
Page 623 CAN MODULE 13.2 CAN Module Related Registers (1) RBO (Return Bus Off) bit (D4) Setting this bit to 1 clears the Receive Error Counter (CAN0REC) and Transmit Error Counter (CAN0TEC) and forcibly places the CAN module into an error active state. This bit is cleared when an error active state is entered.
Page 624 CAN MODULE 13.2 CAN Module Related Registers By using the same ID and setting the same value in mask registers for the two slots, the possibility of a message-lost trouble when, for example, receiving frames which have many IDs can be reduced. •...
Page 625: Can Status Register
CAN MODULE 13.2 CAN Module Related Registers 13.2.2 CAN Status Register CAN0 Status Register (CAN0STAT) BOS EPS CBS BCS LBS CRS RSB TSB RSC TSC Bit Name Function No functions assigned – 0: Not Bus off –...
Page 626 CAN MODULE 13.2 CAN Module Related Registers Bit Name Function 12-15 Number of message slot which has finished sending or receiving (Message slot number) 0000 : Slot0 – 0001 : Slot1 0010 : Slot2 0011 : Slot3 0100 : Slot4 0101 : Slot5 0110 : Slot6 0111 : Slot7...
Page 627 CAN MODULE 13.2 CAN Module Related Registers (3) CBS (CAN Bus Error) bit (D3) [Set condition] This bit is set to 1 when an error on the CAN bus is detected. [Clear condition] This bit is cleared when normally transmitted or received. (4) BCS (BasicCAN Status) bit (D4) When BCS bit = 1, it means that the CAN module is operating in BasicCAN mode.
Page 628 CAN MODULE 13.2 CAN Module Related Registers (7) RSB (Receive Status) bit (D8) [Set condition] This bit is set to 1 when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module started operating as a transmit node or entered a bus idle state.
Page 629: Can Extended Id Register
CAN MODULE 13.2 CAN Module Related Registers 13.2.3 CAN Extended ID Register CAN0 Extended ID Register (CAN0EXTID) IDE0 IDE1 IDE2 IDE3 IDE4 IDE5 IDE6 IDE7 IDE8 IDE9 IDE10 IDE11 IDE12 IDE13 IDE14 IDE15 Bit Name Function IDE0 (Extended ID0) 0: Standard ID format IDE1 (Extended ID1)
Page 630: Can Configuration Register
CAN MODULE 13.2 CAN Module Related Registers 13.2.4 CAN Configuration Register CAN0 Configuration Register (CAN0CONF) Bit Name Function Sets reSynchronization Jump Width (reSynchronization Jump Width) 00: SJW = 1Tq 01: SJW = 2Tq 10: SJW = 3Tq 11: SJW = 4Tq Sets Phase Segment2 (Phase Segment2)
Page 631 CAN MODULE 13.2 CAN Module Related Registers Bit Name Function 8-10 Sets Propagation Segment (Propagation Segment) 000: Propagation Seqment =1Tq 001: Propagation Seqment = 2Tq 010: Propagation Seqment = 3Tq 011: Propagation Seqment = 4Tq 100: Propagation Seqment = 5Tq 101: Propagation Seqment = 6Tq 110: Propagation Seqment = 7Tq 111: Propagation Seqment = 8Tq...
Page 632 CAN MODULE 13.2 CAN Module Related Registers (1) SJW bits (D0-D1) These bits set reSynchronization Jump Width. (2) PH2 bits (D2-D4) These bits set the width of Phase Segment2. Note: The internal CAN module of the M32R/E has IPT (Information Processing Time) = 2. Because PH2 bits = 0 after reset, be sure to change it to a value equal to or greater than 2 before you use the CAN module.
Page 633: Can Time Stamp Count Register
CAN MODULE 13.2 CAN Module Related Registers 13.2.5 CAN Time Stamp Count Register CAN0 Time Stamp Count Register (CAN0TSTMP) CANTSTMP Bit Name Function 0-15 CANSTMP 16-bit counter value – The CAN module contains a 16-bit counter. The count period can be chosen to be the CAN bus bit period divided by 1, 2, 3, or 4 by setting the CAN Control Register (CAN0CNT)'s TSP (Time Stamp Prescaler) bits.
Page 634: Can Error Count Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.6 CAN Error Count Registers CAN0 Receive Error Count Register (CAN0REC) Bit Name Function Receive error count value – (Receive error counter) In an error-active/error-passive state, a receive error count is stored in this register. When received normally, the counter counts down;...
Page 635: Can Baud Rate Prescaler
CAN MODULE 13.2 CAN Module Related Registers 13.2.7 CAN Baud Rate Prescaler CAN0 Baud Rate Prescaler (CAN0BRP) CANBRP Bit Name Function Selects baud rate prescaler value This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period x number of Tq's for 1 bit).
Page 636: Can Interrupt Related Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.8 CAN Interrupt Related Registers CAN0 Slot Interrupt Status Register (CAN0SLIST) SSB0 SSB1 SSB2 SSB3 SSB4 SSB5 SSB6 SSB7 SSB8 SSB9 SSB10 SSB11 SSB12 SSB13 SSB14 SSB15 Bit Name Function SSB0 (Slot 0 interrupt request status) 0: No interrupt request...
Page 637 CAN MODULE 13.2 CAN Module Related Registers When using CAN interrupts, this register lets you know which slot requested an interrupt. • Slots set for transmission The bit is set to 1 when the CAN module finished transmitting. The bit is cleared by writing a 0 in software.
Page 638 CAN MODULE 13.2 CAN Module Related Registers CAN0 Slot Interrupt Mask Register (CAN0SLIMK) IRB0 IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15 Bit Name Function IRB0 (Slot 0 interrupt request mask) 0: Masks (disables) interrupt request IRB1 (Slot 1 interrupt request mask) 1: Enables interrupt request...
Page 639 CAN MODULE 13.2 CAN Module Related Registers CAN0 Error Interrupt Status Register (CAN0ERIST) Bit Name Function No functions assigned – 0: No interrupt request (CAN bus error interrupt status) 1: Interrupt requested (Error passive interrupt status) (Bus off interrupt status) : Only writing a 0 is effective;...
Page 640 CAN MODULE 13.2 CAN Module Related Registers CAN0 Error Interrupt Mask Register (CAN0ERIMK) Bit Name Function 8-12 No functions assigned – 0: Masks (disables) interrupt request (CAN bus error interrupt mask) 1: Enables interrupt request (Error passive interrupt mask) (Bus off interrupt mask) (1) EIM (CAN Bus Error Interrupt Mask) bit (D5) This bit controls interrupt requests generated for occurrence of CAN bus errors by enabling or...
Page 641 CAN MODULE 13.2 CAN Module Related Registers CAN0SLIST CAN0SLIMK Slot 0 transmit/receive completed Data bus 19-source inputs SSB0 CAN0 transmit/receive & error IRB0 (Level) interrupts Slot 1 transmit/receive completed SSB1 IRB1 Slot 2 transmit/receive completed SSB2 IRB2 Slot 3 transmit/receive completed SSB3...
Page 642 CAN MODULE 13.2 CAN Module Related Registers CAN0SLIST CAN0SLIMK Slot 8 transmit/receive completed Data bus SSB8 19-source inputs To preceding page IRB8 (Level) Slot 9 transmit/receive completed SSB9 IRB9 Slot 10 transmit/receive completed SSB10 IRB10 Slot 11 transmit/receive completed SSB11 IRB11 Slot 12 transmit/receive completed...
Page 643 CAN MODULE 13.2 CAN Module Related Registers CAN0ERIST CAN0ERIMK CAN bus error occurs Data bus 19-source inputs To preceding page (Level) Go to error passive state Go to bus-off state Figure 13.2.7 Block Diagram of CAN0 Group Interrupts (3/3) 13-29 Ver.0.10...
Page 644: Can Mask Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.9 CAN Mask Registers CAN0 Global Mask Register Standard ID0 (C0GMSKS0) CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) SID0M SID1M SID2M...
Page 645 CAN MODULE 13.2 CAN Module Related Registers Three registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while Local Mask Registers A and B are used for message slots 14 and 15, respectively. •...
Page 646 CAN MODULE 13.2 CAN Module Related Registers CAN0 Global Mask Register Extended ID0 (C0GMSKE0) CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) EID0M EID1M EID2M EID3M ...
Page 647 CAN MODULE 13.2 CAN Module Related Registers CAN0 Global Mask Register Extended ID2 (C0GMSKE2) CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) EID12M EID13M EID14M EID15M EID16M EID17M ...
Page 648: Can Message Slot Control Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.10 CAN Message Slot Control Registers CAN0 Message Slot0 Control Registers (COMSL0CNT) CAN0 Message Slot1 Control Registers (COMSL1CNT) CAN0 Message Slot2 Control Registers (COMSL2CNT) CAN0 Message Slot3 Control Registers (COMSL3CNT) ...
Page 649 CAN MODULE 13.2 CAN Module Related Registers Bit Name Function 0: Message-lost not occurred (Message slot) 1: Message-lost occurred TRSTAT For transmit slots – (Transmit/receive status) 0: Transmission idle 1: Transmit request accepted For receive slots 0: Reception idle 1: Storing received data TRFIN For transmit slots (Transmit/receive complete)
Page 650 CAN MODULE 13.2 CAN Module Related Registers (3) RM (Remote) bit (D2) To handle remote frames in the message slot, set this bit to 1. The message slot may be set to handle remote frames in following two ways: • Set for remote frame transmission The data set in the message slot is transmitted as a remote frame.
Page 651 CAN MODULE 13.2 CAN Module Related Registers (6) ML (Message Lost) bit (D5) This bit is effective for receive slots. It is set to 1 when the message slot contains unread receive data which is overwritten by reception. This bit is cleared by writing a 0 in software. (7) TRSTAT (Transmit/Receive Status) bit (D6) This bit indicates that the CAN module is transmitting or receiving and is accessing the message slot.
Page 652: Can Message Slots
CAN MODULE 13.2 CAN Module Related Registers 13.2.11 CAN Message Slots CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) ...
Page 653 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) ...
Page 654 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) ...
Page 655 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) ...
Page 656 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) ...
Page 657 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) ...
Page 658 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 0 (C0MSL0DT0) CAN0 Message Slot 1 Data 0 (C0MSL1DT0) CAN0 Message Slot 2 Data 0 (C0MSL2DT0) CAN0 Message Slot 3 Data 0 (C0MSL3DT0) ...
Page 659 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 1 (C0MSL0DT1) CAN0 Message Slot 1 Data 1 (C0MSL1DT1) CAN0 Message Slot 2 Data 1 (C0MSL2DT1) CAN0 Message Slot 3 Data 1 (C0MSL3DT1) ...
Page 660 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 2 (C0MSL0DT2) CAN0 Message Slot 1 Data 2 (C0MSL1DT2) CAN0 Message Slot 2 Data 2 (C0MSL2DT2) CAN0 Message Slot 3 Data 2 (C0MSL3DT2) ...
Page 661 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 3 (C0MSL0DT3) CAN0 Message Slot 1 Data 3 (C0MSL1DT3) CAN0 Message Slot 2 Data 3 (C0MSL2DT3) CAN0 Message Slot 3 Data 3 (C0MSL3DT3) ...
Page 662 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 4 (C0MSL0DT4) CAN0 Message Slot 1 Data 4 (C0MSL1DT4) CAN0 Message Slot 2 Data 4 (C0MSL2DT4) CAN0 Message Slot 3 Data 4 (C0MSL3DT4) ...
Page 663 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 5 (C0MSL0DT5) CAN0 Message Slot 1 Data 5 (C0MSL1DT5) CAN0 Message Slot 2 Data 5 (C0MSL2DT5) CAN0 Message Slot 3 Data 5 (C0MSL3DT5) ...
Page 664 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 6 (C0MSL0DT6) CAN0 Message Slot 1 Data 6 (C0MSL1DT6) CAN0 Message Slot 2 Data 6 (C0MSL2DT6) CAN0 Message Slot 3 Data 6 (C0MSL3DT6) ...
Page 665 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 7 (C0MSL0DT7) CAN0 Message Slot 1 Data 7 (C0MSL1DT7) CAN0 Message Slot 2 Data 7 (C0MSL2DT7) CAN0 Message Slot 3 Data 7 (C0MSL3DT7) ...
Page 666 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) ...
Page 667: Can Protocol
CAN MODULE 13.3 CAN Protocol 13.3 CAN Protocol 13.3.1 CAN Protocol Frame There are four types of frames which are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Frames are separated from each another by an interframe space. Data frame Standard format 0-64...
Page 668 CAN MODULE 13.3 CAN Protocol Error frame 6-12 Interframe space or Error flag Error delimiter overload flag Overload frame 6-12 Interframe space or Overload flag overload flag Overload delimiter Interframe space In an error-active state SOF of next frame Bus idle Intermission In an error-passive state SOF of next frame...
Page 669 CAN MODULE 13.3 CAN Protocol Initial settings Error-active state Transmit error counter ≥ 128 11 consecutive recessive bits detected on CAN bus 128 times Receive error counter ≥ 128 reset by software Transmit error counter < 128 Receive error counter < 128 Bus-off Error-passive state...
Page 670: Initializing The Can Module
CAN MODULE 13.4 Initializing the CAN Module 13.4 Initializing the CAN Module 13.4.1 Initialization of the CAN Module Before you perform communication, set up the CAN module as described below. (1) Selecting pin functions The CAN transmit data output pin (CTX) and CAN data receive input pin (CRX) are shared with input/output ports, so be sure to select the functions of these pins.
Page 671 CAN MODULE 13.4 Initializing the CAN Module 1 Bit Rate Synchronization Propagation Segment Phase Segment1 Phase Segment2 Segment Sampling Point • Shown in this diagram is the bit timing for cases where one bit consists of 8 Tq's. • When one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the value of the bit.
Page 672 CAN MODULE 13.4 Initializing the CAN Module Initialize CAN module Set Input/output Port Operation Mode Register Set Interrupt Controller Set interrupt priority Set CAN Error Interrupt Set CAN Slot Interrupt Mask Register Mask Register • Enable/disable CAN • Enable/disable interrupt bus error interrupt to be generated at completion of transmission...
Page 673: Transmitting Data Frames
CAN MODULE 13.5 Transmitting Data Frames 13.5 Transmitting Data Frames 13.5.1 Data Frame Transmit Procedure The following describes the procedure for transmitting data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register.
Page 674 CAN MODULE 13.5 Transmitting Data Frames Data frame transmit procedure Initialize CAN Message Write H'00 Slot Control Register Read CAN Message Slot Control Register TRSTAT bit = 0 Verify that transmission is idle Set ID and data in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message...
Page 675: Data Frame Transmit Operation
CAN MODULE 13.5 Transmitting Data Frames 13.5.2 Data Frame Transmit Operation The following describes data frame transmit operation. The operations described below are automatically performed in hardware. (1) Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit.
Page 676: Transmit Abort Function
CAN MODULE 13.5 Transmitting Data Frames B'0000 0000 (Note) Write H'80 Transmit aborted Waiting for B'1000 0000 transmission Transmit request Lost bus arbitration accepted CAN bus error occurred Transmit aborted B'0000 0010 B'1000 0010 Transmit completed B'0000 0001 B'1000 0001 (Note) Note: When in this state, data can be written to the message slot.
Page 677: Receiving Data Frames
CAN MODULE 13.6 Receiving Data Frames 13.6 Receiving Data Frames 13.6.1 Data Frame Receive Procedure The following describes the procedure for receiving data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register.
Page 678 CAN MODULE 13.6 Receiving Data Frames Data frame receive procedure Initialize CAN Message Write H'00 Slot Control Register Read CAN Message Slot Control Register Verify that reception is idle TRSTAT bit = 0 Set ID in message slot Standard ID or extended ID Set Extended ID Register Set CAN Message Write H'40 (receive request)
Page 679: Data Frame Receive Operation
CAN MODULE 13.6 Receiving Data Frames 13.6.2 Data Frame Receive Operation The following describes data frame receive operation. The operations described below are automatically performed in hardware. (1) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15).
Page 680 CAN MODULE 13.6 Receiving Data Frames B'0000 0000 Receive request set Clear receive request Wait for receive data B'0100 0000 Store received data Clear receive request B'0000 0011 B'0100 0011 Finished storing Finished storing received data received data Clear receive request B'0100 0001 B'0000 0001...
Page 681: Reading Out Received Data Frames
CAN MODULE 13.6 Receiving Data Frames 13.6.3 Reading Out Received Data Frames The following describes the procedure for reading out received data frames from the slot. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'4E, H'40 or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0.
Page 682 CAN MODULE 13.6 Receiving Data Frames Reading out received data Clear TRFIN bit to 0 Read out from message slot Read CAN Message Slot Control Register TRFIN bit = 0 Finished reading out received data Figure 13.6.3 Procedure for Reading Out Received Data 13-68 Ver.0.10...
Page 683: Transmitting Remote Frames
CAN MODULE 13.7 Transmitting Remote Frames 13.7 Transmitting Remote Frames 13.7.1 Remote Frame Transmit Procedure The following describes the procedure for transmitting remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register.
Page 684 CAN MODULE 13.7 Transmitting Remote Frames Remote frame transmit procedure Initialize CAN Message Write H'00 Slot Control Register Read CAN Message Slot Control Register TRSTAT bit = 0 Verify that transmission is idle Set ID in message slot Set Extended ID Register Standard ID or extended ID Set CAN Message Write H'A0 (transmit request, remote)
Page 685: Remote Frame Transmit Operation
CAN MODULE 13.7 Transmitting Remote Frames 13.7.2 Remote Frame Transmit Operation The following describes remote frame transmit operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit At the same time H'A0 (Transmit Request, Remote) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames.
Page 686 CAN MODULE 13.7 Transmitting Remote Frames The following shows receive conditions for slots that have been set for data frame reception. [Conditions] • The receive frame is a data frame. • The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bit."...
Page 687 CAN MODULE 13.7 Transmitting Remote Frames B'0000 0000 Store received Clear transmit data request B'0000 1000 B'1010 1000 B'1010 1011 B'0000 1011 Finished storing Finished storing CAN bus error received data received data occurs Clear transmit request B'1010 1010 B'0000 1010 B'0000 0001 Finished Finished transmitting...
Page 688: Reading Out Received Data Frames When Set For Remote Frame Transmission
CAN MODULE 13.7 Transmitting Remote Frames 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission The following describes the procedure for reading out received data frames from the slot when it is set for remote frame transmission. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'AE or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0.
Page 689 CAN MODULE 13.7 Transmitting Remote Frames Reading out received data Clear TRFIN bit to 0 Read out from message slot Read CAN Message Slot Control Register TRFIN bit = 0 Finished reading out received data Figure 13.7.3 Procedure for Reading Out Received Data when Set for Remote Frame Transmission 13-75 Ver.0.10...
Page 690: Receiving Remote Frames
CAN MODULE 13.8 Receiving Remote Frames 13.8 Receiving Remote Frames 13.8.1 Remote Frame Receive Procedure The following describes the procedure for receiving remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register.
Page 691 CAN MODULE 13.8 Receiving Remote Frames Remote frame reception procedure Initialize CAN Message Write H'00 Slot Control Register Read CAN Message Slot Control Register TRSTAT bit = 0 Verify that reception is idle Set ID in message slot Set Extended ID Register Standard ID or extended ID Write H'60 (receive request, remote, Set CAN Message...
Page 692: Remote Frame Receive Operation
CAN MODULE 13.8 Receiving Remote Frames 13.8.2 Remote Frame Receive Operation The following describes remote frame receive operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit When H'60 (Transmit Request, Remote) or H'70 (Transmit Request, Remote, Automatic Response Disable) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames.
Page 693 CAN MODULE 13.8 Receiving Remote Frames (5) Operation after receiving a remote frame The operation performed after receiving a remote frame differs depending on how automatic response is set. When automatic response is disabled The slot which finished receiving goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software.
Page 694 CAN MODULE 13.8 Receiving Remote Frames B'0000 0000 Write H'70 Write H'60 (automatic response (automatic response enable) enable) Clear receive Wait for request receive data B'0110 1000 B'0111 1000 Store Store received data received data Store received data Store received data Clear receive Clear receive request...
Page 695: Chapter 14 Real-Time Debugger (Rtd)
CHAPTER 14 CHAPTER 14 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.2 Pin Function of the RTD 14.3 Functional Description of the RTD 14.4 Typical Connection with the Host...
Page 696 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.1 Outline of the Real-Time Debugger (RTD) The Real-Time Debugger (RTD) is a serial I/O through which to read or write to the internal RAM's entire area using commands from outside the microprocessor. Because data transfers between the RTD and internal RAM are performed using an internal dedicated bus independently of the M32R CPU, operation can be controlled without having the stop the M32R CPU.
Page 697 REAL-TIME DEBUGGER (RTD) 14.2 Pin Function of the RTD 14.2 Pin Function of the RTD Pin functions of the RTD are shown below. Table 14.2.1 Pin Function of the RTD Pin Name Type Function RTDTXD Output RTD serial data output RTDRXD Input RTD serial data input...
Page 698: Outline Of Rtd Operation
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3 Functional Description of the RTD 14.3.1 Outline of RTD Operation Operation of the RTD is specified by a command entered from devices external to the chip. A command is specified in bits 16-19(note 1) of the RTD receive data. Table 14.3.1 RTD Commands RTD Receive Data Command Mnemonic...
Page 699: Operation Of Rdr (Real-Time Ram Content Output)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.2 Operation of RDR (Real-time RAM Content Output) When the RDR (real-time RAM content output) command is issued, the RTD is made possible to transfer the contents of the internal RAM to external devices without causing the CPU's internal bus to stop.
Page 700 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD (LSB side) (MSB side) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • RTDTXD Read data (Note) Note : The read data is transferred LSB-first.
Page 701: Operation Of Wrr (Ram Content Forcible Rewrite)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.3 Operation of WRR (RAM Content Forcible Rewrite) When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU's internal bus to stop. Because the RTD writes data to the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU.
Page 702 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD The RTD reads out data from the specified address before writing to the internal RAM and again reads out from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM).
Page 703: Operation Of Ver (Continuous Monitor)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.4 Operation of VER (Continuous Monitor) When the VER (continuous monitor) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VER command.
Page 704: Operation Of Vei (Interrupt Request)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.5 Operation of VEI (Interrupt Request) When the VEI (interrupt request) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VEI command.
Page 705: Operation Of Rcv (Recover From Runaway)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.6 Operation of RCV (Recover from Runaway) When the RTD runs out of control, the RCV (recover from runway) command can be issued to forcibly recover from the runaway condition without having to reset the system. The RCV command must always be issued twice in succession.
Page 706: Method To Set A Specified Address When Using The Rtd
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.7 Method to Set a Specified Address when Using the RTD When using the Real-Time Debugger (RTD), you can set low-order 16-bit addresses of the internal RAM area. Because the internal RAM area is located in a 48 KB area ranging from H'0080 4000 to H'0080 FFFF, you can set low-order 16-bit addresses of that area.
Page 707: Resetting The Rtd
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.8 Resetting the RTD The RTD is reset by applying a system rest (i.e., by entering the RESET signal). The status of the RTD related output pins after a system reset are shown below. Table 14.3.2 RTD Pin State after System Reset Pin Name State...
Page 708: Typical Connection With The Host
REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host 14.4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data. The clock for synchronous is generated by the host. An example for connecting the RTD and host is shown below. Host M32R/E microprocessor...
Page 709 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host The RTD communication for a fixed length of 32 bits per frame generally is performed in four operations sending 8 bits at a time, because most serial interfaces transfer data in units of 8 bits. The RTDACK signal is used to verify that communication is performed normally.
Page 710 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host * This is a blank page.* 14-16 Ver.0.10...
Page 711: Chapter 15 External Bus Interface
CHAPTER 15 CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals 15.2 Read/Write Operations 15.3 Bus Arbitration 15.4 Typical Connection of External Extension Memory...
Page 712 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals 15.1 External Bus Interface Related Signals The 32170 comes with external bus interface related signals shown below. These signals can be used in external extension mode or processor mode. (1) Address The 32170 outputs a 20-bit address (A11-A30) for addressing any location in 2 Mbytes of space.
Page 713 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals (6) Data bus (DB0 - DB15) This is the 16-bit data bus used to access external devices. (7) System clock/write (BCLK / WR) The pin function changes depending on the Bus Mode Control Register (BUSMODC). When BUSMOD = 0 and this signal is System Clock (BCLK), it outputs the system clock necessary to synchronize operations in an external system.
Page 714 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals (10) Port P7 Operation Mode Register (P7MOD) ____ ____ ____ The WAIT, HREQ, and HACK pins are shared with P71, P72, and P73, respectively. The Port P7 Operation Mode Register is used to select the function of port P7. Configuration of this register is shown below.
Page 715 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals (11) Bus Mode Control Register (BUSMODC) The 32170 contains a function to switch between two external bus modes. Bus Mode Control Register (BUSMODC) BUSMOD Bit Name Function 8 - 15...
Page 716 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations 15.2 Read/Write Operations (1) When Bus Mode Control Register = 0 External read/write operations are performed using the address bus, data bus, and signals CS0, ___ __ ___ ____ ____ CS1, RD, BHW, BLW, WAIT, and BCLK. In external read cycle, the RD signal is low while BHW and BLW both are high, reading data from only the valid byte position of the bus.
Page 717 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read Read (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 "H"...
Page 718 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read Read (4 cycles) 1 external 2 internal wait cycles wait cycle BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) "L" Write Write (4 cycles) 1 external 2 internal wait cycles wait cycle BCLK...
Page 719 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations (2) When Bus Mode Control Register = 1 External read/write operations are performed using the address bus, data bus, and signals CS0, ___ ____ CS1, RD, BHE, BLE, WAIT, and WR. In external read cycle, the RD signal goes low and BHE or BLE output for the byte position from which to read is pulled low, reading data from only the byte position of the bus.
Page 720 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read Read (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 "H"...
Page 721 EXTERNAL BUS INTERFACE 15.2 Read/Write Operations Read Read (4 cycles) 1 external 2 internal wait cycles wait cycle BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) "L" Write Write (4 cycles) 1 external 2 internal wait cycles wait cycle BCLK...
Page 722 EXTERNAL BUS INTERFACE 15.3 Bus Arbitration 15.3 Bus Arbitration (1) When Bus Mode Control Register = 0 ____ When HREQ pin input is pulled low and the hold request is accepted, the 32170 goes to a hold state ____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the high- impedance state, allowing data to be transferred on the system bus.
Page 723 EXTERNAL BUS INTERFACE 15.3 Bus Arbitration (2) When Bus Mode Control Register = 1 ____ When HREQ pin input is pulled low and the hold request is accepted, the 32170 goes to a hold state ____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the high- impedance state, allowing data to be transferred on the system bus.
Page 724 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory 15.4 Typical Connection of External Extension Memory (1) When Bus Mode Control Register = 0 A typical connection when using external extension memory is shown in Figure 15.4.1. (External extension memory can only be used in external extension mode and processor mode.) Memory mapping Flash memory 32170F6...
Page 725 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory (2) When Bus Mode Control Register = 1 A typical connection when using external extension memory is shown in Figure 15.4.2. (External extension memory can only be used in external extension mode and processor mode.) Memory mapping Flash memory M32170F6...
Page 726 EXTERNAL BUS INTERFACE 15.4 Typical Connection of External Extension Memory (3) Using 8/16-bit data bus memories in combination when Bus Mode Control Register = 1 The diagram below shows a typical connection of external extension memory, with 8-bit data bus memory located in the CS0 area, and 16-bit data bus memory located in the CS1 area.
Page 727: Chapter 16 Wait Controller
CHAPTER 16 CHAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller 16.2 Wait Controller Related Registers 16.3 Typical Operation of the Wait Controller...
Page 728 WAIT CONTROLLER 16.1 Outline of the Wait Controller 16.1 Outline of the Wait Controller The wait controller controls the number of wait cycles inserted in bus cycles during access to an extended external area. The following outlines the wait controller. Table 16.1.1 Outline of the Wait Controller Item Specification...
Page 729 WAIT CONTROLLER 16.1 Outline of the Wait Controller When accessing an extended external area, the wait controller controls the number of wait cycles to be inserted in bus cycles based on the number of wait cycles set by software and those entered ____ from the WAIT pin.
Page 730 WAIT CONTROLLER 16.2 Wait Controller Related Registers 16.2 Wait Controller Related Registers The following shows a wait controller related register map. Address +0 Address +1 Address Wait Cycles Control Register H'0080 0180 (WTCCR) Blank addresses are a reserved area. Figure 16.2.1 Wait Controller Related Register Map 16-4 Ver.0.10...
Page 731: Wait Cycles Control Register
WAIT CONTROLLER 16.2 Wait Controller Related Registers 16.2.1 Wait Cycles Control Register Wait Cycles Control Register (WTCCR) CS0WTC CS1WTC Bit Name Function 0 , 1 No functions assigned — 2 , 3 CS0WTC 00 : 4 wait cycles (when reset) (CS0 wait cycles control) 01 : 3 wait cycles...
Page 732: Typical Operation Of The Wait Controller
WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller 16.3 Typical Operation of the Wait Controller The following shows a typical operation of the wait controller. The wait controller can control bus access in the range of 2 to 5 cycles. If more access cycles than that are needed, use the WAIT function in combination with the wait controller.
Page 733 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 "H"...
Page 734 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) Write Write (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1...
Page 735 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) Write Write (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1...
Page 736 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (5 cycles) 4 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) Write Write (5 cycles) 4 internal wait cycles BCLK A11 - A30 CS0, CS1...
Page 737 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (6 cycles) 1 external 4 internal wait cycles wait cycle BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) "L" Write Write (6 cycles) 1 external 4 internal wait cycles wait cycle...
Page 738 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (3+n cycles) 2 internal wait cycles n external wait cycles BCLK A11 - A30 CS0, CS1 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) "L" "L" "L" Write Write (3+n cycles) 2 internal wait cycles...
Page 739 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller (2) When Bus Mode Control Register = 1 External read/write operations are performed using the address bus, data bus, and signals CS0, ____ CS1, RD, BHE, BLE, WAIT, and WR. Bus-free state internal bus access BCLK A11 - A30...
Page 740 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (2 cycles) 1 internal wait cycle BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" Write Write (2 cycles) 1 internal wait cycle BCLK A11 - A30 CS0, CS1 "H"...
Page 741 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Write Write (3 cycles) 2 internal wait cycles BCLK A11 - A30 CS0, CS1...
Page 742 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read Read (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Write Write (4 cycles) 3 internal wait cycles BCLK A11 - A30 CS0, CS1...
Page 743 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (5 cycles) Read 4 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Write (5 cycles) Write 4 internal wait cycles BCLK A11 - A30 CS0, CS1...
Page 744 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (6 cycles) Read 1 external wait cycle 4 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) "L" Write (6 cycles) Write 1 external wait cycle...
Page 745 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Read (3+n cycles) Read n external wait cycles 2 internal wait cycles BCLK A11 - A30 CS0, CS1 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) "L" "L" "L" Write (3+n cycles) Write 2 internal wait cycles...
Page 746 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller * This is a blank page.* 16-20 Ver.0.10...
Page 747: Chapter 17 Ram Backup Mode
CHAPTER 17 CHAPTER 17 RAM BACKUP MODE 17.1 Outline 17.2 Example of RAM Backup when Power is Down 17.3 Example of RAM Backup for Saving Power Consumption 17.4 Exiting RAM Backup Mode (Wakeup)
Page 748 RAM BACKUP MODE 17.1 Outline 17.1 Outline In RAM backup mode, the contents of the internal RAM are retained while the power is turned off. RAM backup mode is used for the following two purposes: • Back up the internal RAM data when the power is down •...
Page 749: Normal Operating State
RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down 17.2.1 Normal Operating State Figure 17.2.2 shows the normal operating state of the M32R/E. During normal operation, input on _______ the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high. DC IN Input Output...
Page 750: Ram Backup State
RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down 17.2.2 RAM Backup State Shown in Figure 17.2.3 is the power outage RAM backup state of the M32R/E. When the power supply goes down, the power supply monitor IC starts feeding current from the backup battery to the M32R/E.
Page 751: Example Of Ram Backup For Saving Power Consumption
RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3 Example of RAM Backup for Saving Power Consumption Figure 17.3.1 shows a typical circuit for RAM backup to save on power consumption. The following explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example.
Page 752: Normal Operating State
RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3.1 Normal Operating State Figure 17.3.2 shows the normal operating state of the M32R/E. During normal operation, the RAM backup signal output by the external signal is high. Also, input on the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high.
Page 753: Ram Backup State
RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3.2 RAM Backup State Figure 17.3.3 shows the RAM backup state of the M32R/E. Figure 17.3.4 shows a RAM backup sequence. When the external circuit outputs a low, input on the SBI pin or ADnINi pin goes low. A low on these input pins generates a RAM backup signal (A and in Figure 17.3.3).
Page 754: Precautions To Be Observed At Power-On
RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption Power on RAM backup period 5.0V VCCE, VREFn, AVCCn 3.3V VCCI, OSC-VCC Port output setting Port output setting Port input (High level) (High level) mode Port X External input External input signal goes high signal goes low...
Page 755: Exiting Ram Backup Mode (Wakeup)
RAM BACKUP MODE 17.4 Exiting RAM Backup Mode (Wakeup) 17.4 Exiting RAM Backup Mode (Wakeup) Processing to exit RAM backup mode and return to normal operation is referred to as "wakeup processing." Figure 17.4.1 shows an example of wakeup processing. Wakeup processing is initiated by reset input.
Page 756 RAM BACKUP MODE 17.4 Exiting RAM Backup Mode (Wakeup) * This is a blank page.* 17-10 Ver.0.10...
Page 757: Chapter 18 Oscillation Circuit
CHAPTER 18 CHAPTER 18 OSCILLATION CIRCUIT 18.1 Oscillator Circuit 18.2 Clock Generator Circuit...
Page 758: Oscillator Circuit
OSCILLATION CIRCUIT 18.1 Oscillator Circuit 18.1 Oscillator Circuit The M32R/E contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/O, and internal memory. The frequency fed to the clock input pin (XIN) is multiplied by 4 by the internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory.
Page 759: System Clock Output Function
OSCILLATION CIRCUIT 18.1 Oscillator Circuit 18.1.2 System Clock Output Function A clock whose frequency is twice the input frequency can be output from the BCLK pin. The BCLK pin is shared with port P70. When you use this pin to output the system clock, set the P7 Operation Mode Register (P7MOD)'s D8 bit to 1.
Page 760: Oscillation Stabilization Time At Power-On
OSCILLATION CIRCUIT 18.1 Oscillator Circuit 18.1.3 Oscillation Stabilization Time at Power-on The oscillator circuit comprised of a ceramic (or crystal) resonator has a finite time after power-on at which its oscillation is instable. Therefore, create a certain amount of oscillation stabilization time that suits the oscillator circuit used.
Page 761: Clock Generator Circuit
OSCILLATION CIRCUIT 18.2 Clock Generator Circuit 18.2 Clock Generator Circuit The clock generator supplies independent clocks to the CPU and internal peripheral circuits. CPU clock (32MHz - 40MHz) (8MHz - 10MHz) BCLK (16MHz - 20MHz) 1/2 internal peripheral clock (8MHz - 10MHz) Figure 18.2.1 Configuration of the Clock Generator Circuit 18-5 Ver.0.10...
Page 762 OSCILLATION CIRCUIT 18.2 Clock Generator Circuit * This is a blank page.* 18-6 Ver.0.10...
Page 763: Chapter 19 Jtag
CHAPTER 19 CHAPTER 19 JTAG 19.1 Outline of JTAG 19.2 Configuration of the JTAG Circuit 19.3 JTAG Registers 19.4 Basic Operation of JTAG 19.5 Boundary Scan Description Language 19.6 Precautions about Board Design when Connecting JTAG...
Page 764 JTAG 19.1 Outline of JTAG 19.1 Outline of JTAG The 32170 contains a JTAG (Joint Test Action Group) interface based on IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports, refer to the IEEE Std.
Page 765 JTAG 19.2 Configuration of the JTAG Circuit 19.2 Configuration of the JTAG Circuit The 32170's JTAG circuit consists of the following blocks: • Instruction register to hold instruction codes which are fetched through the boundary-scan path • A set of data registers which are accessed through the boundary-scan path •...
Page 766: Instruction Register (Jtagir)
JTAG 19.3 JTAG Registers 19.3 JTAG Registers 19.3.1 Instruction Register (JTAGIR) The Instruction Register (JTAGIR) is a 6-bit register to hold instruction code. This register is set in IR path sequence. The instructions set in this register determine the data register to be selected in the subsequent DR path sequence.
Page 767: Data Registers
JTAG 19.3 JTAG Registers 19.3.2 Data Registers (1) Boundary Scan Register (JTAGBSR) The Boundary Scan Register is a 471-bit register used to perform boundary-scan test. Bits in this register are assigned to each pin on the 32170. Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or SAMPLE/PRELOAD instruction.
Page 768: Basic Operation Of Jtag
JTAG 19.4 Basic Operation of JTAG 19.4 Basic Operation of JTAG 19.4.1 Outline of JTAG Operation The instruction and data registers basically are accessed in the following three operations, which are performed based on state transitions of the TAP controller. The TAP controller changes state according to JTMS input, and generates control signals required for operation in each state.
Page 769 JTAG 19.4 Basic Operation of JTAG The state transitions of the TAP controller and the basic configuration of the 32170's JTAG related registers are shown below. Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Note : Values (0 and 1) in this diagram denote the state of JTMS input signal.
Page 770 JTAG 19.4 Basic Operation of JTAG 19.4.2 IR Path Sequence Instruction code is set in the Instruction Register (JTAGIR) to select the data register to be accessed in the subsequent DR path sequence. The IR path sequence is performed following the procedure described below.
Page 771 JTAG 19.4 Basic Operation of JTAG JTDI input is sampled at rise Instruction code is set in the parallel output of JTCK in "Shift-IR" state. stage at fall of JTCK in "Update-IR" state. JTCK JTMS state JTDI Don't Care Don't Care Instruction code (6 bits) LSB value MSB value...
Page 772 JTAG 19.4 Basic Operation of JTAG 19.4.3 DR Path Sequence The data register that was selected during the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it. The DR path sequence is performed following the procedure described below.
Page 773 JTAG 19.4 Basic Operation of JTAG JTDI input is sampled at rise Setup data is set in the parallel output stage of JTCK in "Shift-DR" state. at fall of JTCK in "Update-DR" state. JTCK JTMS state JTDI Don't Care Don't Care LSB value MSB value High impedance...
Page 774: Examining And Setting Data Registers
JTAG 19.4 Basic Operation of JTAG 19.4.4 Examining and Setting Data Registers To inspect or set the data register, follow the procedure described below. (1) To access the test access port (JTAG) for the first time, enter test reset (to initialize the test circuit).
Page 775 JTAG 19.4 Basic Operation of JTAG Test-Logic- Run-Test IR path DR path Run-Test IR path DR path Reset state /Idle state sequence sequence /Idle state sequence sequence states JTDI Instruction Setup data Instruction Setup data (Note 1) code code Fixed Fixed JTDO value...
Page 776: Boundary Scan Description Language
JTAG 19.5 Boundary Scan Description Language 19.5 Boundary Scan Description Language The Boundary Scan Description Language (abbreviated BSDL) is stipulated in supplements to "Standard Test Access Port and Boundary-Scan Architecture" of IEEE 1149.1-1990 and IEEE 1149.1a-1993. BSDL is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL).
Page 777 JTAG 19.5 Boundary Scan Description Language -- Boundary Scan Description Language (BSDL) for -- M32170F6VFP: M32R/E M32170 Group, Flash 768KB, 240P6Y_A -- Modification History -- Date Author Version -- Created '99/06/01 MITSUBISHI Ver. 0.0 -- Modified '--/--/-- entity M32170F6VFP is generic (PHYSICAL_PIN_MAP : string := "P6Y240_A");...
Page 778 JTAG 19.5 Boundary Scan Description Language :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; VCCE_51 :linkage bit; VSS_52 :linkage bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; VREF_61 :linkage bit;...
Page 779 JTAG 19.5 Boundary Scan Description Language P161 :inout bit; P162 :inout bit; P163 :inout bit; P164 :inout bit; P165 :inout bit; P166 :inout bit; P167 :inout bit; P172 :inout bit; P173 :inout bit; P174 :inout bit; P175 :inout bit; P176 :inout bit;...
Page 780 JTAG 19.5 Boundary Scan Description Language VCCE_157 :linkage bit; VSS_158 :linkage bit; P110 :inout bit; P111 :inout bit; P112 :inout bit; P113 :inout bit; P114 :inout bit; P115 :inout bit; P116 :inout bit; P117 :inout bit; P100 :inout bit; P101 :inout bit;...
Page 781 JTAG 19.5 Boundary Scan Description Language P146 :inout bit; P147 :inout bit; P150 :inout bit; P151 :inout bit; P152 :inout bit; P153 :inout bit; P154 :inout bit; P155 :inout bit; P156 :inout bit; P157 :inout bit; :inout bit; :inout bit; VCCI_225 :linkage bit;...
Page 782 JTAG 19.5 Boundary Scan Description Language "OSCVCC_21 :21," & "VSS_22 :22," & "VCNT_23 :23," & "VSS_24 :24," & "P30 :25," & "P31 :26," & "P32 :27," & "P33 :28," & "P34 :29," & "P35 :30," & "P36 :31," & "P37 :32,"...
Page 783 JTAG 19.5 Boundary Scan Description Language "AD0IN14 :77," & "AD0IN15 :78," & "AVSS_79 :79," & "VCCE_80 :80," & "VSS_81 :81," & "P180 :82," & "P181 :83," & "P182 :84," & "P183 :85," & "P184 :86," & "P185 :87," & "P186 :88,"...
Page 784 JTAG 19.5 Boundary Scan Description Language "P64 :133," & "P65 :134," & "P66 :135," & "P67 :136," & "VCCI_137 :137," & "VSS_138 :138," & "VCCE_139 :139," & "P70 :140," & "P71 :141," & "P72 :142," & "P73 :143," & "P74 :144,"...
Page 785 JTAG 19.5 Boundary Scan Description Language "P106 :189," & "P107 :190," & "P124 :191," & "P125 :192," & "P126 :193," & "P127 :194," & "VCCI_195 :195," & "VSS_196 :196," & "P130 :197," & "P131 :198," & "P132 :199," & "P133 :200,"...
Page 786 JTAG 19.5 Boundary Scan Description Language attribute TAP_SCAN_CLOCK of TCK : signal is (5.0e6, BOTH); attribute TAP_SCAN_RESET of TRST : signal is true; attribute INSTRUCTION_LENGTH of M32170F6VFP : entity is 6; attribute INSTRUCTION_OPCODE of M32170F6VFP : entity is "BYPASS (111111)," & "SAMPLE (000001),"...
Page 787 JTAG 19.5 Boundary Scan Description Language "USERCODE_REG[32] (USERCODE)," & "MDM_SYSTEM_REG[17] (MDM_SYSTEM)," & "MDM_CONTROL_REG[20] (MDM_CONTROL)," & "MDM_SETUP_REG[2] (MDM_SETUP)," & "MTM_CONTROL_REG[4] (MTM_CONTROL)," & "MON_CODE_REG[32] (MON_CODE)," & "MON_DATA_REG[32] (MON_DATA)," & "MON_PARAM_REG[32] (MON_PARAM)," & "MON_ACCESS_REG[4] (MON_ACCESS)," & "DMA_RADDR_REG[32] (DMA_RADDR)," & "DMA_RDATA_REG[32] (DMA_RDATA)," & "DMA_RTYPE_REG[3] (DMA_RTYPE),"...
Page 788 JTAG 19.5 Boundary Scan Description Language "434 (BC_4, P133, observe_only, X)," & "433 (BC_1, P133, output3, X, 432, 0, Z)," & "432 (BC_1, control, 0)," & "431 (BC_4, P134, observe_only, X)," & "430 (BC_1, P134, output3, X, 429, 0, Z)," & "429 (BC_1, control, 0),"...
Page 789 JTAG 19.5 Boundary Scan Description Language "378 (BC_1, control, 0)," & "377 (BC_4, P156, observe_only, X)," & "376 (BC_1, P156, output3, X, 375, 0, Z)," & "375 (BC_1, control, 0)," & "374 (BC_4, P157, observe_only, X)," & "373 (BC_1, P157, output3, X, 372, 0, Z),"...
Page 790 JTAG 19.5 Boundary Scan Description Language "322 (BC_4, P34, observe_only, X)," & "321 (BC_1, P34, output3, X, 320, 0, Z)," & "320 (BC_1, control, 0)," & "319 (BC_4, P35, observe_only, X)," & "318 (BC_1, P35, output3, X, 317, 0, Z)," & "317 (BC_1, control, 0),"...
Page 791 JTAG 19.5 Boundary Scan Description Language "266 (BC_1, control, 0)," & "265 (BC_4, P07, observe_only, X)," & "264 (BC_1, P07, output3, X, 263, 0, Z)," & "263 (BC_1, control, 0)," & "262 (BC_4, P10, observe_only, X)," & "261 (BC_1, P10, output3, X, 260, 0, Z),"...
Page 792 JTAG 19.5 Boundary Scan Description Language "210 (BC_1, P191, output3, X, 209, 0, Z)," & "209 (BC_1, control, 0)," & "208 (BC_4, P192, observe_only, X)," & "207 (BC_1, P192, output3, X, 206, 0, Z)," & "206 (BC_1, control, 0)," & "205 (BC_4, P193, observe_only, X),"...
Page 793 JTAG 19.5 Boundary Scan Description Language "154 (BC_4, P176, observe_only, X)," & "153 (BC_1, P176, output3, X, 152, 0, Z)," & "152 (BC_1, control, 0)," & "151 (BC_4, P177, observe_only, X)," & "150 (BC_1, P177, output3, X, 149, 0, Z)," & "149 (BC_1, control, 0),"...
Page 794 JTAG 19.5 Boundary Scan Description Language "98 (BC_1, P70, output3, X, 97, 0, Z)," & "97 (BC_1, control, 0)," & "96 (BC_4, P71, observe_only, X)," & "95 (BC_1, P71, output3, X, 94, 0, Z)," & "94 (BC_1, control, 0)," & "93 (BC_4, P72, observe_only, X),"...
Page 795 JTAG 19.5 Boundary Scan Description Language "42 (BC_1, control, 0)," & "41 (BC_4, P115, observe_only, X)," & "40 (BC_1, P115, output3, X, 39, 0, Z)," & "39 (BC_1, control, 0)," & "38 (BC_4, P116, observe_only, X)," & "37 (BC_1, P116, output3, X, 36, 0, Z),"...
Page 796: Precautions About Board Design When Connecting Jtag
JTAG 19.6 Precautions about Board Design when Connecting JTAG 19.6 Precautions about Board Design when Connecting JTAG To materialize fast and highly reliable communication with JTAG tools, the JTAG pins require that wiring lengths be matched during board design. JTAG tool SDI connector (JTAG connector) VCCE(5V) Power...
Page 797 JTAG 19.6 Precautions about Board Design when Connecting JTAG When connecting SDI connector (JTAG connector) VCCE(5V) JTAG tool Power M32R/E 10KΩ 33Ω JTDO 10KΩ 33Ω JTDI 10KΩ 33Ω JTMS 10KΩ 33Ω JTCK 33Ω TRST JTRST 2KΩ 10KΩ 33Ω 33Ω TRCLK TRCLK 33Ω...
Page 798 JTAG 19.6 Precautions about Board Design when Connecting JTAG * This is a blank page.* 19-36 Ver.0.10...
Page 799: Configuration Of The Power Supply Circuit
CHAPTER 20 CHAPTER 20 POWER-UP/POWER- SHUTDOWN SEQUENCE 20.1 Configuration of the Power Supply Circuit 20.2 Power-Up Sequence 20.3 Power-Shutdown Sequence...
Page 800 POWER-UP/POWER-SHUTDOWN SEQUENCE 20.1 Configuration of the Power Supply Circuit 20.1 Configuration of the Power Supply Circuit To materialize high-speed operation at low power, the M32R/E is designed in such a way that its external interface circuits operate at 5 V power supply and all other circuits operate at 3.3 V. This requires that control timing of both 5 V and 3.3 V power supplies be considered when designing your circuit.
Page 801: Power-On Sequence
POWER-UP/POWER-SHUTDOWN SEQUENCE 20.2 Power-Up Sequence 20.2 Power-On Sequence 20.2.1 Power-On Sequence When Not Using RAM Backup The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/E when not using RAM backup. VCCE AVCC0, AVCC1 VREF0, VREF1 RESET...
Page 802: Power-On Sequence When Using Ram Backup
20.2.2 Power-On Sequence When Using RAM Backup The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/E when using RAM backup. VCCE AVCC0, AVCC1 VREF0, VREF1 RESET 3.3V 2.0V 3.3V VCCI 3.3V FVCC 3.3V OSC-VCC : Turn on the 3.3 V power supply after turning on the 5 V power supply.
Page 803: Power-Shutdown Sequence
POWER-UP/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence 20.3 Power-Shutdown Sequence 20.3.1 Power-Shutdown Sequence When Not Using RAM Backup The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ E when not using RAM backup. VCCE AVCC0, AVCC1 VREF0, VREF1...
Page 804: Power-Shutdown Sequence When Using Ram Backup
20.3.2 Power-Shutdown Sequence When Using RAM Backup The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ E when using RAM backup. VCCE AVCC0, AVCC1 VREF0, VREF1 P72 / HREQ RESET 3.3V 2.0V 3.3V VCCI 3.3V FVCC...
Page 805 POWER-UP/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence M32R/E VCCE 5V power supply I/O control circuit AVCC A-D converter circuit VCCI 3.3V 3.3V power supply Peripheral circuits FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.3 Microcomputer Ready to Run State (VCCE = 5 V, VCCI system = 3.3 V, VDD = 3.3 V) M32R/E VCCE I/O control circuit...
Page 806 POWER-UP/POWER-SHUTDOWN SEQUENCE 20.3 Power-Shutdown Sequence M32R/E VCCE 5V power supply I/O control circuit AVCC A-D converter circuit VCCI 3.3V power supply Peripheral circuits FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 20.3.5 CPU Halt State M32R/E VCCE 5V power supply I/O control circuit AVCC A-D converter circuit...
Page 807: Absolute Maximum Ratings
CHAPTER 21 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings 21.2 Recommended Operating Conditions 21.3 DC Characteristics 21.4 A-D Conversion Characteristics 21.5 AC Characteristics...
Page 808 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.1 Absolute Maximum Ratings 21.1 Absolute Maximum Ratings Absolute Maximum Ratings (Guaranteed for Operation at -40 to 125°C) Symbol Condition Rated Value Unit Parameter Internal Logic Power Supply VCCI FVCC=OSC–VCC VCCI -0.3 to 4.2 Voltage VCCI FVCC=OSC–VCC RAM Power Supply Voltage -0.3 to 4.2...
Page 809 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.2 Recommended Operating Conditions 21.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter Rated Value Unit...
Page 810 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Rated Value Unit External I/O Buffer Power Supply Voltage (Note 1) VCCE Internal Logic Power Supply Voltage (Note 2)
Page 811 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.3 DC Characteristics 21.3 DC Characteristics 21.3.1 Electrical Characteristics (1) Electrical characteristics when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter...
Page 812 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.3 DC Characteristics (2) Electrical characteristics of each power supply pin when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Symbol Parameter...
Page 813 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.3 DC Characteristics (3) Electrical characteristics when f(XIN) = 8 MHz (Referenced to VCCE = 5 V ± 10%, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter Condition Rated Value Unit...
Page 814 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.3 DC Characteristics (4) Electrical characteristics of each power supply pin when f(XIN) = 8 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Symbol Parameter...
Page 815 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.3 DC Characteristics RAM retention power supply current in a standard sample (reference value) 1000 Ta=125°C Ta=85°C Ta=25°C VDD [V] 21-9 Ver.0.10...
Page 816: Flash Related Electrical Characteristics
ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.3 DC Characteristics 21.3.2 Flash Related Electrical Characteristics Flash Related Electrical Characteristics (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V Unless Otherwise Noted) Symbol Parameter Condition Unit Rated Value FVCC Power Supply Current Ifvcc1 (when Programming)
Page 817: A-D Conversion Characteristics
ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.4 A-D Conversion Characteristics 21.4 A-D Conversion Characteristics A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = 25°C, f(XIN) = 10.0 MHz Unless Otherwise Noted) Rated Value Symbol Parameter Condition Unit –...
Page 818: Ac Characteristics
ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics 21.5 AC Characteristics 21.5.1 Timing Requirements • Unless otherwise noted, timing conditions are VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C • The characteristic values apply to the case of concentrated capacitance with an output load capacitance of 15 to 50 pF (however, 80 pF for JTAG-related).
Page 819 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics (4) TINi (i=0-25) Symbol Parameter Condition Unit Rated Value Figure 21.5.5 TINi Input Pulse Width tc(BCLK) w(TINi) (5) Read and write timing Rated Value Symbol Parameter Condition Unit Figure 21.5.6 21.5.7 21.5.8 su(D-BCLKH) Data Input Setup Time before BCLK h(BCLKH-D) Data Input Hold Time after BCLK...
Page 820 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics (6) Bus arbitration timing Symbol Parameter Condition Unit Rated Value Figure 21.5.9 HREQ Input Setup Time before BCLK su(HREQL-BCLKH) HREQ Input Hold Time after BCLK h(BCLKH-HREQL) (7) Input transition time on JTAG pin Rated Value Figure Symbol...
Page 821: Switching Characteristics
ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics 21.5.2 Switching Characteristics (1) Input/output ports Rated Value Symbol Parameter Condition Unit Figure 21.5.1 d(E-P) Port Data Output Delay Time (2) Serial I/O a) CSIO mode, with internal clock selected Rated Value Symbol Parameter Condition Unit...
Page 822 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics (4) Read and write timing Rated Value Figure Symbol Parameter Condition Unit 21.5.6 21.5.7 21.5.8 tc(Xin) BCLK Output Cycle Time c(BCLK) tc(BCLK) BCLK Output High Pulse Width w(BCLKH) tc(BCLK) BCLK Output Low Pulse Width w(BCLKL) Address Delay Time after BCLK d(BCLKH-A)
Page 823 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics Read and write timing (continued from the preceding page) Symbol Parameter Condition Unit Rated Value Figure 21.5.6 21.5.7 21.5.8 Data Output Delay Time after Write d(BLWL-D) (Byte write mode) d(BHWL-D) Valid Data Output Time after Write tc(BCLK) v(BLWH-D) (Byte write mode)
Page 824 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics 21.5.3 AC Characteristics 0.8VCCE BCLK 0.2VCCE tsu(P-E) th(E-P) 0.8VCCE 0.8VCCE Port input 0.2VCCE 0.2VCCE td(E-P) 0.8VCCE Port output 0.2VCCE Figure 21.5.1 Input/Output Port Timing a) CSIO mode, with internal clock selected 0.8VCCE 0.2VCCE td(CLK-D) 0.8VCCE 0.2VCCE...
Page 825 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics 0.2VCCE 0.2VCCE tw(SBIL) Figure 21.5.3 SBI Timing BCLK 0.2VCCE td(BCLK-TOi) 0.8VCCE 0.2VCCE Figure 21.5.4 TOi Timing tw(TINi) 0.8VCCE 0.8VCCE TINi 0.2VCCE 0.2VCCE Figure 21.5.5 TINi Timing 21-19 Ver.0.10...
Page 826 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics tc(BCLK) tw(BCLKH) tw(BCLKL) BCLK 0.43VCCE 0.16VCCE td(BCLKH-CS) tv(BCLKH-CS) td(BCLKL-RDL) td(BCLKH-A) tv(BCLKH-A) Address 0.43VCCE (A11-A30) 0.16VCCE CS0, CS1 tv(RDH-A) td(CS-RDL) td(A-RDL) tv(RDH-CS) tw(RDL) tv(BCLKH-RDL) 0.43VCCE 0.16VCCE tw(RDH) td(BLWH-RDL) tsu(D-RDH) th(RDH-D) td(BHWH-RDL) 0.43VCCE Data input 0.16VCCE (D0-D15) th(BCLKH-D)
Page 827 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics tw(BCLKL) tc(BCLK) tw(BCLKH) BCLK 0.43VCCE 0.16VCCE 0.16VCCE tv(BCLKH-CS) td(BCLKH-CS) td(BCLKH-A) tv(BCLKH-A) Address 0.43VCCE (A12-A30) 0.16VCCE CS0, CS1 td(RDH-BLWL) td(BCLKL-RDL) td(RDH-BHWL) 0.43VCCE 0.16VCCE td(CS-BLWL) td(CS-BHWL) td(BLWH-RDL) td(A-BLWL) tw(BLWL) td(BHWH-RDL) td(A-BHWL) tw(BHWL) 0.43VCCE 0.16VCCE 0.16VCCE tv(BLWH-CS) tv(BCLKL-BLWL) tv(BHWH-CS)
Page 828 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics Address (A11-A30) 0.43VCCE 0.43VCCE 0.16VCCE 0.16VCCE CS0, CS1 td(RDH-BLEL) td(BLEH-RDL) td(RDH-BHEL) td(BHEH-RDL) 0.43VCCE 0.16VCCE td(CS-WRL) tv(WRH-CS) td(A-WRL) tv(WRH-A) tw(WRL) 0.43VCCE 0.16VCCE 0.16VCCE tv(WRH-BLEL) td(BLEL-WRL) tv(WRH-BHEL) td(BHEL-WRL) 0.43VCCE 0.16VCCE 0.16VCCE BLE , BHE tpxz(WRH-DZ) td(WRL-D) tv(WRH-D) Data output...
Page 829 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics JTCK,JTDI 0.8VCCE 0.8VCCE JTMS,JRST 0.2VCCE 0.2VCCE Note: Stipulated values are guaranteed values when the test pin load capacitance CL = 80 pF. Figure 21.5.10 Input Transition Time on JTAG pins tc(JTCK) tw(JTCKL) tw(JTCKH) 0.5VCCE JTCK th(JTCK-JTDI)
Page 830 ELECTRICAL CHARACTERISTICS PRELIMINARY PRELIMINARY 21.5 AC Characteristics This is a blank page. 21-24 Ver.0.10...
Page 831: Chapter 22 Typical Characteristics
CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22.1 A-D Conversion Characteristics...
Page 832 INTERNAL MEMORY 22.1 A-D Conversion Characteristics 22.1 A-D Conversion Characteristics (1) Test conditions • Ta = -40°C, 27°C, 125°C • Test voltage (VCC) = 5.12 V • Double-speed mode (2) Measured value (Reference value) Ta = -40°C Ta = 27°C Ta = 125°C Vertical axis : Conversion error Horizontal axis : Analog input voltage ( 5.12 ×...
Page 833: Appendix 1 Mechanical Specifications
APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing...
Page 834 MECHANICAL SPECIFICATIONS Appendix 1 Appendix 1.1 Dimensional Outline Drawing Appendix 1.1 Dimensional Outline Drawing (1) 240-pin QFP 240P6Y-A Plastic 240pin 32×32mm body QFP Weight(g) Lead Material EIAJ Package Code JEDEC Code QFP240-P-3232-0.50 — Cu Alloy Recommended Mount Pad Dimension in Millimeters Symbol —...
Page 835 MECHANICAL SPECIFICATIONS Appendix 1 Appendix 1.1 Dimensional Outline Drawing (2) 255-pin FBGA 255F7F 255pin 17×17mm body FBGA EIAJ Package Code JEDEC Code Weight(g) — — Under Development × 17TYP 19=15.2 0.20 C A (16.6) 0.35 – 0.05 0.8TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 255- φ...
Page 836 MECHANICAL SPECIFICATIONS Appendix 1 Appendix 1.1 Dimensional Outline Drawing This is a blank page. Appendix 1-4 Ver.0.10...
Page 837 APPENDIX 2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32170 Instruction Processing Time...
Page 838 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 32170 Instruction Processing Time Appendix 2.1 32170 Instruction Processing Time For the M32R, the number of instruction execution cycles in E stage normally represents its instruction processing time. However, depending on pipeline operation, other stages may affect the instruction processing time.
Page 839 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 32170 Instruction Processing Time The following shows the number of memory access cycles in IF and MEM stages. Shown here are the minimum number of cycles required for memory access. Therefore, these values do not always reflect the number of cycles required for actual memory or bus access.
Page 840 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 32170 Instruction Processing Time This is a blank page. Appendix 2-4 Ver.0.10...
Page 841 APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise...
Page 842 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1 Precautions about Noise The following describes precautions to be taken about noise and corrective measures against noise. The corrective measures described here are theoretically effective for noise, but require that the application system with these measures incorporated be fully evaluated before it can actually be put to use.
Page 843 INSTRUCTION PROCESSING TIME Appendix 3 Appendix 3.1 Precautions about Noise (2) Wiring of clock input/output pins Reduce the length of wiring connecting to the clock input/output pins. When connecting a capacitor to the oscillator, make sure its ground lead wire and the VSS pin on the microcomputer are connected with the shortest possible wiring (within 20 mm).
Page 844 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0.1 µF between VSS and VCC lines in such a way as to meet the requirements described below.
Page 845 INSTRUCTION PROCESSING TIME Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.3 Processing Analog Input Pin Wiring Connect a resistor of about 100 to 500 Ω ( in series to the analog signal wire connecting to the analog input pin at a position as close to the microcomputer as possible. Also, insert a capacitor of about 100 pF between the analog input pin and AVSS pin at a position as close to the AVSS pin as possible.
Page 846 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.4 Consideration about the Oscillator The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it less susceptible to influences from other signals. (1) Avoidance from large-current signal lines Signal lines in which a large current flows exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer (especially the oscillator) as possible.
Page 847 INSTRUCTION PROCESSING TIME Appendix 3 Appendix 3.1 Precautions about Noise (2) Avoiding effects of rapidly level-changing signal lines Locate signal lines whose levels change rapidly as far away from the oscillator as possible. Also, make sure rapidly level-changing signal lines will not intersect clock-related signal lines and other noise-sensitive signal lines.
Page 848 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.5 Processing Input/Output Ports For input/output ports, take the appropriate measures in both hardware and software following the procedure described below. Hardware measures _ Insert resistors of 100 Ω (or more) in series to input/output ports. Software measures •...
Page 849 Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/E Series 32170 Group User’s Manual Ver 0.10 March 17, 2000 Copyright © 2000 MITSUBISHI ELECTRIC CORPORATION Copyright © 2000 MITSUBISHI ELECTRIC SEMICONDUCTOR SYSTEMS CORPORATION All Rights Reversed. No part of this manual may be reproduced or distributed in any form or by any means...
Page 850 M32R Family M32R/E Series 32170 Group User’s Manual Mitsubishi Electric Corporation Mitsubishi Electric Semiconductor Systems Corporation MSD-M32170-U-0003...

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Mitsubishi Electric M32R Series User Manual

Chapter 1 Overview

Chapter 3 Address Space

Chapter 4 Eit

Chapter 5 Interrupt Controller (Icu)

Chapter 6 Internal Memory

Chapter 9 Dmac

Chapter 10 Multijunction Timers

Chapter 11 A-D Converters

Chapter 12 Serial I/O

Chapter 13 Can Module

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Summary of Contents for Mitsubishi Electric M32R Series