Asus AAEON FWS-2272 User Manual
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Asus AAEON FWS-2272 User Manual

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FWS-2272
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Summary of Contents for Asus AAEON FWS-2272

  • Page 1 FWS-2272 Network Appliance User’s Manual 1...
  • Page 2 Copyright Notice This document is copyrighted, 2018. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel  Corporation Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity FWS-2272  Power adapter  If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. Caution: There is a danger of explosion if the battery is incorrectly replaced.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Embedded Box PC/ Industrial System 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○ 连接器及线材...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Embedded Box PC/ Industrial System Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................5 Dimensions ....................... 6 Jumpers and Connectors ..................9 List of Jumpers ......................11 2.3.1 CMOS Setting Selection (CN2) ..............12 List of Connectors ....................13 2.4.1 Digital I/O (CN9) ..................14 Installing the SATA DOM ..................
  • Page 12 3.4.6.1.4 Serial Port for Out-of-Band Management/Windows Emergency Management Services (EMS) ..........37 3.4.7 Advanced: Power Management ............39 3.4.8 Advanced: Digital I/O Port Configuration ...........41 3.4.9 Status LED Configuration ..................42 Setup submenu: Chipset ..................43 3.5.1 Chipset: North Bridge ................44 3.5.1.1 North Bridge: AMI Graphic Output Protocol Policy ....

  • Page 13: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 14: Specifications

    Specifications System Intel® Celeron N3350 Processor SoC Processor  LPDDR4 1GB RAM System Memory  Chipset  Intel® i211 Ethernet  Gigabit Ethernet x 4 Bypass  8GB eMMC Storage  SATA 6.0 Gb/s port x 1, for SATA DOM Mini-Card socket (full-size) with SIM socket x Expansion Interface ...
  • Page 15 1~255 steps by software programming Watchdog Timer  GPIO Programmable push button x 1 Software Button  TPM2.0 9665  Reserve internal pin header 8-bit Digital I/O GPIO  interface (4-in /4-out) Fanless  Silver Color  12V DC Power in connector Power Requirement ...
  • Page 16 10 ~ 80% @ 40°C, non-condensing Storage Humidity  0.5 Grms/ 5 ~ 500Hz / operation (SATA DOM) Anti-Vibration  1.5 Grms/ 5 ~ 500Hz / non operation 10 G peak acceleration (11 m sec. duration), Anti-Shock  operation 20 G peak acceleration (11 m sec. duration), non operation Chapter 1 –...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions System Chapter 2 – Hardware Information...
  • Page 19 Board Component Side 85.8 81.75 78.09 80.27 74.08 67.03 71.88 54.36 42.32 32.22 27.28 14.11 10.9 10.23 5.77 5.39 Chapter 2 – Hardware Information...
  • Page 20 Solder Side 54.36 50.4 Chapter 2 – Hardware Information...

  • Page 21: Jumpers And Connectors

    Jumpers and Connectors Component Side LPC1 CN11 CN12 Chapter 2 – Hardware Information...
  • Page 22 Solder Side Chapter 2 – Hardware Information...

  • Page 23: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function CMOS Setting Selection Chapter 2 – Hardware Information...

  • Page 24: Cmos Setting Selection (Cn2)

    2.3.1 CMOS Setting Selection (CN2) 1 2 3 Normal (Default) Clear CMOS Chapter 2 – Hardware Information...

  • Page 25: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function DIMM1 DDR3L SODIMM SOCKET (Option) CON1 RS-232 SATA6G INTERFACE SATA POWER Mini PCIe socket CN7/CN8 SIM CARD SOCKET CN14 RESET Pin Head (Option) CN13...

  • Page 26: Digital I/O (Cn9)

    2.4.1 Digital I/O (CN9) This connector offers 4-pair of digital I/O functions and address is 801H. The pin definitions are illustrated below: Signal Signal Digital- IN/OUT(Port1 Bit 1) Digital- IN/OUT (Port1 Bit 2) Digital- IN/OUT (Port1 Bit 4) Digital- IN/OUT (Port1 Bit 5) Digital- IN/OUT (Port3 Bit 4) Digital- IN/OUT (Port3 Bit 5) Digital- IN/OUT (Port6 Bit 3)

  • Page 27: Installing The Sata Dom

    Installing the SATA DOM 1. Loosen and remove the screws from the top panel. Chapter 2 – Hardware Information...
  • Page 28 2. Remove the top panel. Chapter 2 – Hardware Information...
  • Page 29 Step 3: Connect the SATA and power cables to the PCBA. Chapter 2 – Hardware Information...

  • Page 30: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 31: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.

  • Page 32: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press ...

  • Page 33: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 34: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 35: Advanced: Trusted Computing

    3.4.1 Advanced: Trusted Computing Options summary: Security Device Support Disabled Enabled Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Enabled Enable or Disable SHA-1 PCR Bank SHA256 PCR Bank Disabled...
  • Page 36 TPM Clear Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device. Platform Hierarchy Disabled Enabled Enable or Disable Platform Hierarchy Storage Hierarchy Disabled Enabled Enable or Disable Storage Hierarchy Endorsement Hierarchy Disabled Enabled...

  • Page 37: Advanced: Cpu Configuration

    3.4.2 Advanced: CPU Configuration Options summary: Intel Virtualization Technology Disabled Enabled When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology VT-d Disabled Enabled Enable/Disable CPU VT-d EIST Disabled Enabled Enable/Disable Intel SpeedStep Power Limit 1 Enable Disabled Chapter 3 –...
  • Page 38 Enabled Enable/Disable Power Limit 1 Chapter 3 – AMI BIOS Setup...

  • Page 39: Advanced: Sata Drives

    3.4.3 Advanced: SATA Drives Options summary: Chipset SATA Disabled Enabled Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). Chapter 3 – AMI BIOS Setup...

  • Page 40: Advanced: Usb Configuration

    3.4.4 Advanced: USB Configuration Options summary: Legacy USB Support Disabled Enabled Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. Chapter 3 – AMI BIOS Setup...

  • Page 41: Advanced: Hardware Monitor

    3.4.5 Advanced: Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 42: Advanced: Sio Configuration

    3.4.6 Advanced: SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 43: Sio Configuration: Serial Port Configuration

    3.4.6.1 SIO Configuration: Serial Port Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 44: Serial Port Console Redirection

    3.4.6.1.1 Serial Port Console Redirection Options summary: Console Redirection Disabled Enabled Console Redirection Enabled or Disabled. Chapter 3 – AMI BIOS Setup...

  • Page 45: Console Redirection Settings

    3.4.6.1.2 Console Redirection Settings Options summary: Terminal Type VT100 VT100+ VT-UTF8 ANSI Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. Bits per second 9600 19200...
  • Page 46 115200 Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds. Data Bits Data Bits Parity None Even Mark Space A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1’s in the data bits is even.
  • Page 47 Enabled Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals Recorder Mode Disabled Enabled On this mode enabled only text will be send. This is to capture Terminal data. Resolution 100x31 Disabled Enabled Enables or disables extended terminal resolution Legacy OS Redirection Resolution 80x24 80x25 On Legacy OS, the Number of Rows and Columns supported redirection...

  • Page 48: Legacy Console Redirection Settings

    3.4.6.1.3 Legacy Console Redirection Settings Legacy Serial Redirection Port COM0 Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages. (Default only support first COM Port) Chapter 3 – AMI BIOS Setup...

  • Page 49: Serial Port For Out-Of-Band Management/Windows

    3.4.6.1.4 Serial Port for Out-of-Band Management/Windows Emergency Management Services (EMS) Options summary: Terminal Type VT100 VT100+ VT-UTF8 ANSI VT-UTF8 is the preferred terminal type for out-of-band management. The next best choice is VT100+ and then VT100. See above, in Console Redirection Settings page, for more Help with Terminal Type/Emulation.
  • Page 50 115200 Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds. Flow Control None Hardware RTS/CTS Software Xon/Xoff Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a ‘stop’...

  • Page 51: Advanced: Power Management

    3.4.7 Advanced: Power Management Options summary: Power Mode ATX Type AT Type Select Power Supply Mode. Restore AC Power Loss Power Off Power On Last State Select AC power state when power is re-applied after a power failure. RTC Wake system from S5 Disabled Fixed time Dynamic time...
  • Page 52 Fixed Time: System will wake on the hr::min::sec specified. Dynamic Time: System will wake on the current time + Increase minute(s) Wake up day (Fixed time option) Select 0 for daily system wake up, 1-31 for which day of month that you would like the system to wake up.

  • Page 53: Advanced: Digital I/O Port Configuration

    3.4.8 Advanced: Digital I/O Port Configuration DIO_P#1~4 Input Output Set DIO as Input or Output DIO_P#5~8 Input Output Set DIO as Input or Output DIO_P#1~4 Direction High Set output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 54: Status Led Configuration

    3.4.9 Status LED Configuration Status LED LED OFF RED LED ON RED LED BLINK RED LED FAST BLINK GREEN LED ON GREEN LED BLINK GREEN LED FAST BLINK Configure Status LED Chapter 3 – AMI BIOS Setup...

  • Page 55: Setup Submenu: Chipset

    Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 56: Chipset: North Bridge

    3.5.1 Chipset: North Bridge Options summary: Primary Display PCIe Select which of IGD/PCI Graphics device should be Primary Display Chapter 3 – AMI BIOS Setup...

  • Page 57: North Bridge: Ami Graphic Output Protocol Policy

    3.5.1.1 North Bridge: AMI Graphic Output Protocol Policy Options summary: Output Select HDMI1 Output Interface Chapter 3 – AMI BIOS Setup...

  • Page 58: Scc Configuration

    3.5.2 SCC Configuration Options summary: SCC eMMC Support (D28:F0) Enable Disable Enable/Disable SCC eMMC Support eMMC Max Speed HS400 HS200 DDR50 Select the eMMC max Speed allowed. Chapter 3 – AMI BIOS Setup...

  • Page 59: Setup Submenu: Security

    Setup submenu: Security Change User/Administrator Password You can set passwords to limit BIOS access - After installing an Administrator password, you will then be able to install a User password. A user password does not provide access to many of the features in the Setup utility.
  • Page 60 Removing the Password Highlight this item and type in the current password. When the next dialog box appears, press Enter to disable password protection. Chapter 3 – AMI BIOS Setup...

  • Page 61: Setup Submenu: Boot

    Setup submenu: Boot Options summary: Quite Boot Disabled Enabled Enables or disables Quiet Boot option. CSM Support Disabled Enabled Enable/Disable Support Launch PXE ROM Disabled Enabled Controls the execution of Legacy PXE OpROM Network Stack Disabled Enabled Chapter 3 – AMI BIOS Setup...
  • Page 62 Enable/Disable UEFI Network Stack Chapter 3 – AMI BIOS Setup...

  • Page 63: Setup Submenu: Exit

    Setup submenu: Exit Chapter 3 – AMI BIOS Setup...

  • Page 64: Chapter 4 - Driver Installation

    Chapter 4 Chapter 4 – Driver Installation...

  • Page 65: Driver Installation

    Driver Installation Please download the driver from AAEON website. It contains all the drivers and utilities you need to set up your product. Follow the steps below to install the driver. http://www.aaeon.com/en/p/desktop-network-appliance-fws-2272 Step 1 – Install LAN Driver Open the Step 1 – LAN file Unzip the igb-5.3.5.12.tar.gz file Follow the “readme”...

  • Page 66: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 67: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 68 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 69 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 70 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 71 ************************************************************************************ VOID SIOEnterMBPnPMode(){ Switch(SIOIndex){ Case 0x2E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0x55); Break; Case 0x4E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0xAA); Break; VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0x02); IOWriteByte(SIOData, 0x02); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN);...
  • Page 72 ************************************************************************************ VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 << BitNum); TmpValue |= (Value << BitNum); IOWriteByte(SIOData, TmpValue); SIOExitMBPnPMode(); VOID SIOByteSet(byte LDN, byte Register, byte Value){ SIOEnterMBPnPMode();...

  • Page 73: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 74: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 75 Appendix B – I/O Information...

  • Page 76: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 77: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 78 Appendix B – I/O Information...
  • Page 79 Appendix B – I/O Information...
  • Page 80 Appendix B – I/O Information...
  • Page 81 Appendix B – I/O Information...
  • Page 82 Appendix B – I/O Information...
  • Page 83 Appendix B – I/O Information...
  • Page 84 Appendix B – I/O Information...
  • Page 85 Appendix B – I/O Information...

  • Page 86: Appendix C - Standard Lan Bypass Platform Setting

    Appendix C Appendix C - Standard LAN Bypass Platform Setting...

  • Page 87: Status Led

    Status LED The LED status indicator of FWS-2272 is programmable with AAEON SDK for your application. Table1: LED Status STA_LED2 STA_LED1 STA_LED0 LED Off Red LED On Red LED Blink Red LED Fast Blink Reserved Green LED Blink Green LED Fast Blink Green LED On Table2: Status LED and register mapping table CPLD Slave Address 0x90 (Note1)
  • Page 88 Sample Code: ***************************************************************************************** #define Byte CPLD_SLAVE_ADDRESS //This parameter is represented from Note1 #define Byte OFFSET //This parameter is represented from Note2 ***************************************************************************************** bData = aaeonSmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); switch( LED_FLAG) case 0: //LED Off //BIT2=0, BIT1=0, BIT0=0 bData = bData & 0xF8; break;...
  • Page 89 bData = (bData & 0xF8) | 0x07; break; case 5: //Green LED Blink //BIT2=1, BIT1=0, BIT0=1 bData = (bData & 0xF8) | 0x05; break; case 6: //Green LED Fast Blink //BIT2=1, BIT1=1, BIT0=0 bData = (bData & 0xF8) | 0x06; break;...

  • Page 90: Lan Bypass

    LAN Bypass Table1: LAN Kit ID Select LAN_ID2 LAN_ID1 LAN_ID0 LAN kit selected LAN Kit 1 Selected LAN Kit 2 Selected Table2: LAN Bypass register table Function Description LAN_ID3 Use for selecting which LAN kit will be LAN_ID2 configured, refert to Table 1 of ID Select table of LAN kit.
  • Page 91 Table3: LAN Bypass register mapping table CPLD Slave Address 0x90 (Note1) Attribute Offset(SMBUS) BitNum Value LAN_ID3 0x01(Note2) (Table 1) LAN_ID2 0x01(Note2) (Table 1) LAN_ID1 0x01(Note2) (Table 1) LAN_ID0 0x01(Note2) (Table 1) PWR_ON 0x01(Note2) (Table 2) PWR_OFF 0x01(Note2) (Table 2) WDT_EN 0x01(Note2) (Table 2) ACT_EN...
  • Page 92 // Set Reg01h bit0 if(bLanSel & 0x01) bData = bData | 0x01; else bData = bData & 0xFE; // Power On Action (Reg01h bit6) if(SET_PASS_THROUGH) // Pass Through bData = bData & 0xBF; else // Bypass bData = bData | 0x40; // Power Off Action (Reg01h bit5) if(SET_PASS_THROUGH) // Pass Through bData = bData &...

  • Page 93: Software Reset Button Configuration

    Software Reset Button Configuration Table 1: Soft Reset Button register mapping table Attribute Register(I/O) BitNum Value BTN_STS 0xA05(Note1) 4(Note2) (Note3) Table 2: LAN Bypass register table Function Description Reading this register returns the pin level status which is normal high active low. BTN_STS 0: Pin Level States Low.

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