Page 1 Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products...
Page 2 A signal is asserted when it is in its active or true state, regardless of whether that state is represented by a high or low voltage. A signal is negated when it is in its inac- tive or false state. MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 3 Freescale Semiconductor, Inc. MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 4: Table Of Contents
Internal ROM Disable (MOD) ................ 4-4 Exception Control Signals ................4-4 4.4.1 Reset (RSTIN)....................4-4 4.4.2 Low Voltage Reset (LVRSTIN) ..............4-5 4.4.3 Reset Out (RSTOUT) ..................4-5 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 5 4.12.3 Standby Battery Power (V )..............4-9 BATT 4.12.4 Standby Power Filter (V )................ 4-9 STBY SECTION 5 ROM MODULE Overview ......................5-1 Functional Description..................5-1 Applications...................... 5-2 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 6 8.2.3 General Low-Power Features ............... 8-7 SECTION 9 TIMER/RESET MODULE Overview ......................9-1 Timer/Reset Programming Model ..............9-1 Reset Operation ....................9-2 9.3.1 Reset Pins ..................... 9-2 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 7 10.2.3 Fast Interrupt Enable Register (FIER)............10-3 10.2.4 Normal Interrupt Pending Register (NIPND) ..........10-4 10.2.5 Fast Interrupt Pending Register (FIPND) ............ 10-5 10.2.6 Interrupt Request Input Assignments ............10-5 MOTOROLA MMC2001 viii REFERENCE MANUAL For More Information On This Product,...
Page 8 Signal Descriptions ..................12-3 12.3.1 SPI_MISO (Master In, Slave Out) ............... 12-3 12.3.2 SPI_MOSI (Master Out, Slave In) ............... 12-4 12.3.3 SPI_EN......................12-4 12.3.4 SPI_CLK...................... 12-4 12.3.5 SPI_GP ....................... 12-4 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 9 14.4.4 Keypad Standby ..................14-7 14.4.5 Glitch Suppression on Keypad Inputs ............14-7 14.4.6 Multiple Key Closures.................. 14-8 14.4.7 Typical Keypad Configuration and Scanning Sequence ......14-9 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 10 16.8.3 Breakpoint Address Mask Registers (BAMA, BAMB) ....... 16-14 16.8.4 Breakpoint Address Comparators ............. 16-14 16.8.5 Memory Breakpoint Counters (MBCA, MBCB) ......... 16-14 16.9 OnCE Trace Logic..................16-14 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 11 Overview ......................B-1 APPENDIX C PROGRAMMING REFERENCE Peripheral Module Address Assignment ............C-1 Interrupt Controller Programming Model............C-2 C.2.1 Interrupt Source Register (INTSRC)............C-2 C.2.2 Normal Interrupt Enable Register (NIER) ............C-2 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 12 UART Programming Model ................C-34 C.9.1 UART Receive Register (URX)..............C-36 C.9.2 UART Transmit Register (UTX) ..............C-37 C.9.3 UART Control Register 1 (UCR1)..............C-38 C.9.4 UART Control Register 2 (UCR2)..............C-40 MMC2001 MOTOROLA REFERENCE MANUAL xiii For More Information On This Product, Go to: www.freescale.com...
Page 13 C.10.11 Control State Register (CTL) ..............C-52 C.10.12 Write-Back Bus Register (WBBR) .............C-53 C.10.13 Processor Status Register (PSR) ..............C-53 C.10.14 Reserved Test Control Registers (Reserved, MEM_BIST, FTCR, LSRL) .C-53 INDEX RECORD OF CHANGES MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 14 9-16 PIT Control and Status Register ..............9-14 9-17 PIT Data Register................... 9-15 9-18 PIT Alternate Data Register ................9-16 10-1 Interrupt Source Register ................10-2 10-2 Normal Interrupt Enable Register..............10-3 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 15 15-2 PWM Generating Audio ................. 15-1 15-3 PWM Prescaler ....................15-2 15-4 PWM Control Registers.................. 15-4 15-5 PWM Period Registers................... 15-6 15-6 PWM Width Registers ..................15-7 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 16 C-13 Watchdog Service Register................C-11 C-14 PIT Control and Status Register ..............C-11 C-15 PIT Data Register...................C-13 C-16 PIT Alternate Data Register ................C-13 C-17 Keypad Control Register ................C-14 MMC2001 MOTOROLA REFERENCE MANUAL xvii For More Information On This Product, Go to: www.freescale.com...
Page 17 C-44 UART Data Direction Register ...............C-45 C-45 UART Port Data Register................C-45 C-46 OnCE Command Register ................C-46 C-47 OnCE Control Register ..................C-47 C-48 OnCE Status Register..................C-50 C-49 Control State Register..................C-52 MOTOROLA MMC2001 xviii REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 18 16-2 Sequential Control Field Settings..............16-9 16-3 Memory Breakpoint Control Field Settings........... 16-10 16-4 Processor Mode Field Settings ..............16-12 Maximum Ratings ....................A-1 DC Electrical Specifications ................A-1 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 19 C-18 TxFL Field Settings ..................C-38 C-19 RxFL Field Settings..................C-39 C-20 OnCE Register Addressing ................C-47 C-21 Sequential Control Field Definition..............C-48 C-22 Memory Breakpoint Control Field Definition...........C-49 C-23 Processor Mode Field Definition ..............C-51 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 20 — Periodic interrupt capability — Pins can be configured as general-purpose I/O • Interval Mode Serial Peripheral Interface (ISPI) — Efficient communication with slower serial peripherals MMC2001 INTRODUCTION MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 21: Mmc2001 Block Diagram
20-Bit Address Bus 32-Kbyte SRAM Periodic Interval Timer 16-Bit Data Bus Peripheral Interrupt Interface Gasket Control PWM x 6 UART x 2 ISPI Figure 1-1 MMC2001 Block Diagram MOTOROLA INTRODUCTION MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 22: Integer Cpu
This section gives a short description of the M•CORE CPU features and some basic bus interface information. 2.1 M•CORE Overview The 32-bit M•CORE microRISC engine represents a new family of Motorola micropro- cessor core products. The processor architecture has been designed for high-perfor- mance and cost-sensitive embedded control applications, with particular emphasis on reduced system power consumption.
Page 23: Features
Load and store multiple register instructions allow low overhead context save and restore operations. These instructions can execute in (N+1) clock cycles, where N is the numbers of registers to transfer. MOTOROLA INTEGER CPU MMC2001...
Page 24: Programming Model
By convention, register R15 serves as the link register for subrou- tine calls, and register R0 is typically used as the current stack pointer. MMC2001 INTEGER CPU MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 25: Programming Model
Five scratch registers are provided for supervisor software use in handling exception events. A single register is provided to alter the base address of the exception vector table. Two registers are provided for global control and status. MOTOROLA INTEGER CPU MMC2001...
Page 26: Data Format Summary
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Halfword Halfword Byte 0 Byte 1 Byte 2 Byte 3 Word Figure 2-3 Data Organization in Registers MMC2001 INTEGER CPU MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 27: Operand Addressing Capabilities
BKPT Breakpoint BMASKI Bit Mask Immediate Branch BREV Bit Reverse BSETI Bit Set Immediate Branch to Subroutine Branch on Condition True BTSTI Bit Test Immediate MOTOROLA INTEGER CPU MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 28 Move Inverted C Bit to Register Logical Complement Logical Inclusive-OR ROTLI Rotate Left by Immediate RSUB Reverse Subtract RSUBI Reverse Subtract Immediate Return from Exception Return from Interrupt MMC2001 INTEGER CPU MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 29: M•Core Bus Interface
The M•CORE uses the address bus to specify the address for the transfer and the data bus to transfer the data. Control and attribute signals indicate the beginning and type MOTOROLA INTEGER CPU MMC2001...
Page 30: Bus Signals
= time set up th = time hold Figure 2-4 Signal Relationships to Clocks 2.8.2 Bus Signals Figure 2-5 shows the M•CORE bus signals arranged by functional group. MMC2001 INTEGER CPU MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 31: Signal Descriptions
Figure 2-5 M•CORE Bus Signals 2.8.3 Signal Descriptions Table 2-2 lists and describes the bus interface signals. More detailed descriptions can be found in subsequent sections. Signal direction is relative to the M•CORE. MOTOROLA INTEGER CPU MMC2001 2-10 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 32: Bus Operation
The following sections provide a functional description of the system bus, the signals that control it, and the bus cycles provided for data transfer operations. They also describe the error conditions and reset operation. MMC2001 INTEGER CPU MOTOROLA REFERENCE MANUAL 2-11 For More Information On This Product, Go to: www.freescale.com...
Page 33: Interface Requirements For Read And Write Cycles
TSIZ1 TSIZ0 ADDR1 ADDR0 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] — — — — — — Byte — — — — — — — — Halfword — — Word MOTOROLA INTEGER CPU MMC2001 2-12 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 34: Processor Instruction/Data Transfers
Once an access has been accepted, the processor is free to change the current request. Access information must therefore be latched by a slave device. MMC2001 INTEGER CPU MOTOROLA REFERENCE MANUAL 2-13 For More Information On This Product, Go to: www.freescale.com...
Page 35: Bus Exception Cycles
A bus error termination for any write or read access that references data specifically requested by the execution unit causes the processor to begin exception processing immediately. MOTOROLA INTEGER CPU MMC2001 2-14...
Page 36: System Memory Map
The description of the peripherals in this document provide information regarding the result of accesses to unimplemented registers. MMC2001 SYSTEM MEMORY MAP MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 37: Peripheral Module Interface Operation
On-Chip RAM Array Supervisor, Selective User 30008000 – 3000FFFF RAM Echoes Supervisor, Selective User Not Used 30100000 – 40000000 — (Access causes transfer error) MOTOROLA SYSTEM MEMORY MAP MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 38: Signal Descriptions
UART1 RxD1/TSIZ1 RTS0/PSTAT2 SRAM ROW[7:0] CTS0/PSTAT3 COL[7:0] UART0 TxD0/PSTAT0 RxD0/PSTAT1 Peripheral ADDR[19:0] Interface Gasket DATA[15:0] PWM[5:0] CS[2:0],CS3 Timer/Reset ISPI Module Figure 4-1 Functional Signal Groups MMC2001 SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 39: Signal Index
Keypad and Edge Port COL[7:0] GPIO — Column 7 – 0 ROW[7:0] GPIO 47-K pull-up Row 7 – 0 INT[7:0] GPIO — External interrupts 7 – 0 MOTOROLA SIGNAL DESCRIPTIONS MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 40 1. All pull-ups and pulldowns are disconnected when the pin is programmed as an output. 2. GPIO = “General-Purpose Input/Output”, GPO = “General-Purpose Output”, GPI = “General-Purpose Input”. MMC2001 SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 41: Bus Signals
This active-low input signal is used to initiate a system reset. An external reset signal resets the MMC2001 and most internal peripherals. The debug module is unaffected by RSTIN; this function is provided through the TRST pin. MOTOROLA SIGNAL DESCRIPTIONS MMC2001...
Page 42: Low Voltage Reset (Lvrstin)
The test data input (TDI) pin is the serial input for test instructions and data. TDI is sampled on the rising edge of TCK and it has an internal 47-Kbyte pull-up resistor. MMC2001 SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 43: Test Data Output (Tdo)
See SECTION 13 EXTERNAL INTERRUPTS/GPIO (EDGE PORT) for more informa- tion on these signals. 4.7.1 External Interrupts 7 – 0 (INT[7:0]) These bidirectional pins comprise the external interface to the GPIO module. MOTOROLA SIGNAL DESCRIPTIONS MMC2001 REFERENCE MANUAL For More Information On This Product,...
Page 44: Keypad Signals
TxD1 is used to provide the TSIZ0 internal status signal when the SZEN bit in the EIM configuration register is set. In this case it operates as an active-high TSIZ0 out- put. MMC2001 SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 45: Clear To Send (Cts0)
This output signal is used as a general-purpose control signal for external logic or devices. 4.11 Pulse Width Modulator Signals See SECTION 15 PULSE WIDTH MODULATOR for more information on these sig- nals. MOTOROLA SIGNAL DESCRIPTIONS MMC2001 REFERENCE MANUAL For More Information On This Product,...
Page 46: Pwm[5:0]
This pin supplies positive battery standby power to the chip. 4.12.4 Standby Power Filter (V STBY This pin is used to provide an external filter capacitor connection for the standby volt- age switching logic. MMC2001 SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 47 Freescale Semiconductor, Inc. MOTOROLA SIGNAL DESCRIPTIONS MMC2001 4-10 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 48: Rom Module
CS0 output for an external boot ROM. Refer to SECTION 4 SIGNAL DESCRIPTIONS and SECTION 7 EXTERNAL INTERFACE MODULE for details of the interaction of the MOD input signal with the CS0 signal. MMC2001 ROM MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 49: Applications
• Reset boot code • Frequently accessed code • Table of constants • Revision and identification registers for all MMC2001 peripherals • Self-test diagnostic code MOTOROLA ROM MODULE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 50: Static Ram Module
An external standby power pin is provided to power both sections of the SRAM for data retention. The SRAM contents are undefined immediately following a power-on reset. MMC2001 STATIC RAM MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 51 Freescale Semiconductor, Inc. MOTOROLA STATIC RAM MODULE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 52: External Interface Module
TA, TEA Figure 7-1 EIM Block Diagram 7.2 Signals 7.2.1 Address Bus The ADDR[19:0] signals are address bus outputs used to address external devices. MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 53: Data Bus
7.2.6.1 Chip Select 0 (CS0) This active-low output signal is asserted based on a decode of bits ADDR[31:24] of the access address, and at reset based on the value of the MOD input. MOTOROLA EXTERNAL INTERFACE MODULE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 54: Chip-Select Address Range
00101101 Flash 00101111 SRAM 00101110 Spare 00101100 7.4 EIM Interface Example Figure 7-2 shows an example of an EIM interface to memory and peripherals. MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 55: Eim Functionality
7.5 EIM Functionality 7.5.1 Configurable Bus Sizing The EIM supports byte, halfword, and word operands, allowing access to 8- and 16- bit ports. It does not support misaligned transfers. MOTOROLA EXTERNAL INTERFACE MODULE MMC2001 REFERENCE MANUAL For More Information On This Product,...
Page 56: Interface Requirements For Read And Write Cycles
— DATA[15:8] DATA[15:8] — — DATA[7:0] DATA[7:0] — — DATA[15:8] DATA[7:0] DATA[15:8] DATA[15:8] DATA[15:8] DATA[15:8] Word DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] DATA[15:8] DATA[7:0] DATA[15:8] DATA[7:0] MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 57: External Boot Rom Control
• A user access to a supervisor-protected internal ROM or RAM (i.e., the corre- sponding SP bit in the EIM configuration register is set), or user access to peripheral space. MOTOROLA EXTERNAL INTERFACE MODULE MMC2001 REFERENCE MANUAL For More Information On This Product,...
Page 58: Show Cycles
15 (i.e., bits other than the PA and CSEN bits) are undefined at reset. Access these registers with 32-bit loads and stores only. CS0CR — CS0 Control Register 10004000 RESET: CSEN RESET: Figure 7-3 CS0 Control Register MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 59: Cs1, Cs2, Cs3 Control Registers
CSA=0, WSC=0001 and WWS=1 for access to Flash memory (two-clock read access and three-clock write access), EDC, CSA and WSC to the appropriate number for access to an LCD controller. MOTOROLA EXTERNAL INTERFACE MODULE MMC2001...
Page 60: Wait State Control Field Settings
1 = Chip select is asserted a clock later during both read and write cycles. In addition, an idle cycle is inserted between back-to-back external transfers. MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 61: Data Port Size Field Settings
1 = User mode accesses are prohibited. An attempted access to an address mapped by this chip select in user mode will result in a TEA to the CPU and no assertion of the chip select output. MOTOROLA EXTERNAL INTERFACE MODULE MMC2001...
Page 62: Eim Configuration Register
Access this register with 32-bit loads and stores only. EIMCR — EIM Configuration Register 10004018 RESET: SZEN PSTEN SHEN RESET: Figure 7-5 EIM Configuration Register MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL 7-11 For More Information On This Product, Go to: www.freescale.com...
Page 63 These two bits are used to determine what the EIM does with the external bus during internal transfers (i.e., an access to the internal ROM, RAM or peripherals). When show cycles are enabled, the internal address and data bus are driven externally. On reset, show cycles are disabled. MOTOROLA EXTERNAL INTERFACE MODULE MMC2001 7-12...
Page 64: External Bus Timing Diagrams
Reserved 7.8 External Bus Timing Diagrams The following timing diagrams show the timing of accesses to memory or peripherals. MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL 7-13 For More Information On This Product, Go to: www.freescale.com...
Page 65 S3(S1) MCU ADDR addr V1 addr V2 addr Vx MCU R/W MCU TREQ ADDR[19:0] addr V1 DATA[15:0] OE, EB[0:1] OEA = 1 MCU DATA MCU TA...
Page 66: Write Memory Access (Csa = 0, Wsc = 1, Wws = 0)
Freescale Semiconductor, Inc. Figure 7-7 Write Memory Access (CSA = 0, WSC = 1, WWS = 0) MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL 7-15 For More Information On This Product, Go to: www.freescale.com...
Page 67 S5(S1) addr V1 addr V2 addr V2 addr Vx addr Vy addr V2 MCU ADDR MCU R/W MCU TREQ addr V1 addr V1+2 addr Vy ADDR[19:0] READ READ DATA[15:0] Halfword Halfword OE, EB[0:1] MCU DATA Word MCU TA READ...
Page 68 S5(S1) MCU ADDR addr V1 addr V2 addr V2 addr Vx addr Vy addr Vz MCU R/W MCU TREQ ADDR[19:0] addr V1+2 addr Vy addr V1 Write Write DATA[15:0] Halfword Halfword EB[0:1] Write MCU DATA Word MCU TA WRITE...
Page 69 S3(S1) S3(S1) MCU ADDR addr V1 addr Vx addr Vy addr V2 addr Vz addr Vw MCU R/W MCU TREQ ADDR[19:0] addr V1 addr V2 DATA[15:0] READ WRITE OE,EB[0:1] OE, EB MCU DATA MCU TA READ (WSC=2, EDC=0) WRITE (WSC=1, WWS=0)
Page 70 S3(S1) addr V1 addr Vx addr Vy addr V2 addr Vz addr Vw MCU ADDR MCU R/W MCU TREQ ADDR[19:0] addr V1 addr Vy DATA[15:0] OE, EB[0:1] OE, EB MCU DATA MCU TA READ (WSC=1, EDC=1) IDLE WRITE (WSC=1, WWS=0)
Page 71 MCU ADDR Addr x Addr y MCU R/W MCU TREQ Addr y Addr x READ DATA[7:0] XXXXXXXXXXX OE, EB[0:1] MCU DATA MCU TA IDLE...
Page 72 Freescale Semiconductor, Inc. Figure 7-13 Peripheral Write Access (CSA = 1, WSC = 5) MMC2001 EXTERNAL INTERFACE MODULE MOTOROLA REFERENCE MANUAL 7-21 For More Information On This Product, Go to: www.freescale.com...
Page 73 MCU ADDR addr V1 addr V2 addr Vy MCU R/W MCU TREQ ADDR[19:0] addr V1 addr V2 DATA[15:0] Read Write OE, EB[0:1] OE, EB Write Read MCU DATA MCU TA READ WRITE...
Page 74: Clock Module And Low-Power Modes
Interval Timer (PIT) LOW_REFCLK/4 (8.192 kHz) LOW_REFCLK/128 (256 Hz) GPIO/Keypad for interrupt debouncer JTAG/OnCE HI_REFCLK, TCK NOTES: 1. When enabled and not low-power disabled MMC2001 CLOCK MODULE AND LOW-POWER MODES MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 75 • Control circuitry for generation and gating of high frequency clocks to the CPU and peripherals • Divider circuits for generation of low frequency clocks for peripherals. A diagram of the clock module is shown in Figure 8-1. MOTOROLA CLOCK MODULE AND LOW-POWER MODES MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 76: Mmc2001 Clock Module
*CLKIN input buffer (to CPU, EIM, is a special low signal !STBY &!STOP &!DOZE &!WAIT Interrupt Controller) swing receiver Figure 8-1 MMC2001 Clock Module MMC2001 CLOCK MODULE AND LOW-POWER MODES MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 77: Low-Power Modes
Stop mode must be entered in a controlled manner, by shutting down each peripheral that is going to be stopped after it is ensured that its current operation is properly terminated. MOTOROLA CLOCK MODULE AND LOW-POWER MODES MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 78: Peripheral Behavior In Low-Power Modes
The module registers will not be accessed by the CPU during the low-power mode states. Once a pending MMC2001 CLOCK MODULE AND LOW-POWER MODES MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 79 Table 8-2. Standby mode is selected when the LVRSTIN pin is asserted. All modules except for the low-power oscillator (OSC) and the time-of-day timer (TOD) are held in reset in this mode. The TOD continues to run. MOTOROLA CLOCK MODULE AND LOW-POWER MODES MMC2001...
Page 80: General Low-Power Features
This output pin may be disabled in the low state to lower power consumption via the CLKOUT enable (CKOE) bit in the reset/timer block. MMC2001 CLOCK MODULE AND LOW-POWER MODES MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 81 Freescale Semiconductor, Inc. MOTOROLA CLOCK MODULE AND LOW-POWER MODES MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 82: Timer/Reset Module
Supervisor Only 1000102C PIT Alternate Data Register (ITADR) Supervisor Only 1000102E Reserved Supervisor Only 10001FFF 10002000 Not Used (Access causes transfer error) Not Applicable 10002FFF MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 83: Reset Operation
To internal resets Watchdog Timer Signal to latch MOD pin Reset Status Register Power-up bypass Internal MOD signal to EIM Figure 9-1 Reset Functional Block Diagram MOTOROLA TIMER/RESET MODULE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 84: Reset Sequence
This bit is cleared by POR, a qualified assertion of the RSTIN pin, or a qualified assertion of the LVRSTIN pin. 0 = CLKOUT source is HI_REFCLK 1 = CLKOUT source is LOW_REFCLK MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 85: Time-Of-Day Timer
TOD Fraction Alarm 32-Bit TOD Seconds Alarm Interrupt TOD Fraction 32-Bit TOD Seconds 256 Hz TOD Fraction Latch MMC2001 Internal Bus Figure 9-3 TOD Block Diagram MOTOROLA TIMER/RESET MODULE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 86: Tod Operation
This bit controls the function of the TOD alarm 0 = Alarm function is off to save power 1 = Alarm function is on AIE — Alarm Interrupt Enable MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 87: Tod Seconds Register (Todsr)
TODSR is written but are not affected by either reset pin or the watchdog reset conditions. The fraction counter is undefined after a POR. Writes to this register cause all eight bits to be set. Access this register with 32-bit accesses only. MOTOROLA TIMER/RESET MODULE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 88: Tod Seconds Alarm Register (Todsar)
1/256 of a second if the alarm function is enabled by the AE bit in the TODCSR. This register is not affected by any of the reset conditions. Access this register with 32-bit loads and stores only. MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 89: Watchdog Timer
(From Clock Block) * NOTE: DOZE and STOP are generated from the CPU signals LPMD1 and LPMD0 DBUG is an active high signal from the CPU indicating debug mode Figure 9-9 Watchdog Timer Block Diagram MOTOROLA TIMER/RESET MODULE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 90: Watchdog Timing Specifications
(watchdog stop enable) bit is set in the watchdog control register (WCR), the watch- dog is halted. When stop mode is exited, the watchdog operation reverts to what it was prior to entering stop mode. MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 91: Watchdog Timer In Debug Mode
After reset, write WT before enabling the watchdog. The value in WT is loaded into the watchdog counter after running the ser- vice routine as well as on enabling the watchdog timer. MOTOROLA TIMER/RESET MODULE MMC2001...
Page 92: Interval Timer (Pit)
The timer can either count down from the value written in the modulus latch, or it can be a free-running down-counter. MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL 9-11 For More Information On This Product, Go to: www.freescale.com...
Page 93: Pit Operation
This mode of operation is selected when the RLD bit in the PIT control/status register (ITCSR) is set to a value of one. The counter is not directly writable from the module data bus; instead, it gets its data from the modulus latch. MOTOROLA TIMER/RESET MODULE MMC2001...
Page 94: Pit As A "Free-Running" Timer
9.6.4 Interval Timer Registers The interval timer has three registers: the control/status register (ITCSR), the data register (ITDR), and the alternate data register (ITADR). MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL 9-13 For More Information On This Product, Go to: www.freescale.com...
Page 95: Pit Control/Status Register (Itcsr)
This bit is the PIT interrupt flag. It is cleared by writing a one to this bit or by writing to the PIT data register. 0 = No PIT interrupt is present 1 = PIT interrupt is present MOTOROLA TIMER/RESET MODULE MMC2001 9-14...
Page 96: Pit Data Register (Itdr)
Access this register with 32-bit loads and stores only. ITDR — PIT Data Register 10001028 RESET: PIT DATA RESET: Figure 9-17 PIT Data Register MMC2001 TIMER/RESET MODULE MOTOROLA REFERENCE MANUAL 9-15 For More Information On This Product, Go to: www.freescale.com...
Page 97: Pit Alternate Data Register (Itadr)
In debug mode, the module may either continue to run or be halted. If the DBG bit is set in the PIT control/status register, the timer is halted. When debug mode is exited, the timer operation reverts to what it was prior to entering debug mode. MOTOROLA TIMER/RESET MODULE MMC2001...
Page 98: Interrupt Controller
These registers are readable by software. In addition, the NIER and FIER registers are writable. Attempted writes to read-only registers are ignored. Access these regis- ters with 32-bit loads and stores only. MMC2001 INTERRUPT CONTROLLER MOTOROLA REFERENCE MANUAL 10-1 For More Information On This Product, Go to: www.freescale.com...
Page 99: Interrupt Controller Programming Model
IN26 IN25 IN24 IN23 IN22 IN21 IN20 IN19 IN18 IN17 IN16 RESET: IN15 IN14 IN13 IN12 IN11 IN10 RESET: Figure 10-1 Interrupt Source Register MOTOROLA INTERRUPT CONTROLLER MMC2001 10-2 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 100: Normal Interrupt Enable Register (Nier)
EF25 EF24 EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16 RESET: EF15 EF14 EF13 EF12 EF11 EF10 RESET: Figure 10-3 Fast Interrupt Enable Register MMC2001 INTERRUPT CONTROLLER MOTOROLA REFERENCE MANUAL 10-3 For More Information On This Product, Go to: www.freescale.com...
Page 101: Normal Interrupt Pending Register (Nipnd)
When a normal interrupt enable flag is set and the corresponding interrupt line is asserted, the interrupt controller asserts a normal interrupt request. The normal inter- rupt pending flags reflect the interrupt input lines which are asserted and are currently enabled to generate a normal interrupt. MOTOROLA INTERRUPT CONTROLLER MMC2001 10-4...
Page 102: Fast Interrupt Pending Register (Fipnd)
10.2.6 Interrupt Request Input Assignments The assignment of bits within the interrupt registers to interrupt sources is shown in Table 10-2. MMC2001 INTERRUPT CONTROLLER MOTOROLA REFERENCE MANUAL 10-5 For More Information On This Product, Go to: www.freescale.com...
Page 103: Interrupt Source Assignment
PWM2 PWM3 PWM4 PWM5 UART0 transmit UART1 transmit UART0 receive UART1 receive ISPI INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Unused Unused Unused MOTOROLA INTERRUPT CONTROLLER MMC2001 10-6 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 104: Universal Asynchronous Receiver/Transmitter Module Overview
The UART performs all normal operations associated with “start-stop” asynchronous communication. Serial data is transmitted and received at standard bit rates using the internal 16x bit clock generator. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-1 For More Information On This Product, Go to: www.freescale.com...
Page 105: Uart Signals
CTS output. If the receiver detects a pending overrun, it negates the CTS output. This pin can also be used as a general purpose output controlled by the CTS bit in UART control register 2. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001...
Page 106: Txd - Uart Transmit
Jitter tolerance and noise immunity are provided by sampling at a 16x rate and using voting techniques to clean up the samples. Once the MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-3 For More Information On This Product,...
Page 107: Infrared Interface
Start Bit — One bit time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition. Stop Bit — One bit time of logic one that indicates the end of a data frame. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001...
Page 108: Uart Programming Model
All registers may be accessed either as a halfword or as a byte. The RX and TX data registers may also be accessed as 32-bit words. For these registers the upper 16 bits are forced to zeros. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-5 For More Information On This Product, Go to: www.freescale.com...
Page 109: Uart Module Address Map
UART1 Port Data Register (U1PDR) Supervisor Only 1000A088 Reserved Supervisor Only 1000AFFF 1000B000 Not Used (Access causes transfer error) Not Applicable 1FFFFFFF MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001 11-6 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 110: Uart Receive Register (Urx)
0 = No FIFO overrun 1 = A FIFO overrun was detected At reset, this bit is cleared to zero. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-7 For More Information On This Product, Go to: www.freescale.com...
Page 111: Uart Transmitter Register (Utx)
The low byte is write-only. When this register is read, bits TX[15:8] always return zero, and TX[7:0] is not driving the bus. The TX register is echoed to 16-word addresses in order to support filling the transmit FIFO with the store register quadrant (stq) instruc- tion. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001 11-8...
Page 112: Uart Control Register 1 (Ucr1)
Interrupt if TX FIFO has a slot for eight or more characters Interrupt if TX FIFO has a slot for fourteen or more characters At reset, these bits are cleared to zero. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-9 For More Information On This Product, Go to: www.freescale.com...
Page 113: Rxfl Field Settings
0 = Receiver disabled 1 = Receiver enabled At reset, this bit is cleared to zero. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001 11-10 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 114: Uart Control Register 2 (Ucr2)
UART. It controls the clock source, number of bits per character, parity generation and checking, and behavior of the RTS, CTS, and DTR pins. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-11 For More Information On This Product,...
Page 115 This bit enables or disables the parity generator in the transmitter and parity checker in the receiver. 0 = Parity disabled 1 = Parity enabled At reset, this bit is cleared to zero. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001 11-12 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 116: Uart Brg Register (Ubrgr)
(equal to the system clock). The value 0xFFF pro- duces the minimum clock rate (divide by 4096). MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-13 For More Information On This Product, Go to: www.freescale.com...
Page 117: Uart Status Register (Usr)
RX FIFO is empty. This bit is automatically cleared when the data level in the RX FIFO goes below the set threshold level. 0 = No character ready (no interrupt posted) 1 = Character(s) ready (interrupt posted) At reset, this bit is cleared to zero. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001 11-14 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 118: Uart Test Register (Uts)
This bit controls a loopback from transmitter to receiver in the infrared interface. 0 = No IR loop 1 = Connect IR transmit to IR receiver At reset, this bit is cleared to zero. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-15 For More Information On This Product, Go to: www.freescale.com...
Page 119: Gpio Pins And Registers
U0DDR — UART0 Data Direction Register 1000908C U1DDR — UART1 Data Direction Register 1000A08C PDC3 PDC2 PDC1 PDC0 RESET: Figure 11-10 UART Data Direction Register MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001 11-16 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 120: Uart Port Data Register (Updr)
In the following figures, the RT clock cycles are numbered from one (start of a bit time) to sixteen (end of a bit time). MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-17 For More Information On This Product,...
Page 121 At the end of a character reception, data is transferred from the shift register to the parallel receiver register, with the corresponding flags updated in the receiver register and the status register. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001...
Page 122: Start Bit - Ideal Case
RT clock leads to an uncertainty about the exact placement of the leading edge of the start bit. The uncertainty in the placement of the edge will be one-sixteenth of a bit-time. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-19 For More Information On This Product, Go to: www.freescale.com...
Page 123: Start Bit - Noise Case One
RT7 [3] now verify that the start bit has been found. If the noise bit [1] is further away from the beginning of the actual start bit, the perceived start bit will still be correct. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE...
Page 124: Start Bit - Noise Case Two
This causes incorrect data reception. MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-21 For More Information On This Product, Go to: www.freescale.com...
Page 125: Start Bit - Noise Case Three
The noise [3] causes two out of the three data samples to be erroneously detected as logic ones. This is rejected, therefore, as a start bit, because the majority of samples RT8, RT9, and RT10 [3] suggest it should be a logic one. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001...
Page 126: Uart Operation In Low-Power System Modes
Table 11-5 UART Low-Power Mode Operation Doze Mode Normal Mode Wait Mode Stop Mode DOZE = 0 DOZE = 1 System Clock UART Serial Interface Module Interface MMC2001 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MOTOROLA REFERENCE MANUAL 11-23 For More Information On This Product, Go to: www.freescale.com...
Page 127: Uart Operation In System Debug Mode
“bump.” That is, the value at the read side of the RX FIFO does not change as a result of reading this register in debug mode. Repeated reads of the UART receiver register, therefore, do not cause its value to change once it contains a valid character. MOTOROLA UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE MMC2001...
Page 128: Interval Mode Serial Peripheral Interface
Interval mode is similar to manual mode, except that it includes a programmable timer to support timed transfers. Interval mode is suitable for control- ling an external sound DAC, for example. MMC2001 INTERVAL MODE SERIAL PERIPHERAL INTERFACE MOTOROLA REFERENCE MANUAL 12-1 For More Information On This Product, Go to: www.freescale.com...
Page 129 The user then negates the SPI_EN register bit to complete the operation. For systems that need more than 16 clocks to transfer data, the SPI_EN bit can remain set between exchanges. MOTOROLA INTERVAL MODE SERIAL PERIPHERAL INTERFACE MMC2001 12-2...
Page 130: Interval (Master) Mode
A new data bit is presented on each trailing edge of the SPI_CLK in normal clock mode (PHA=0). As a slave mode output, SPI_MISO is three-stated when the SPI_EN input is negated. MMC2001 INTERVAL MODE SERIAL PERIPHERAL INTERFACE MOTOROLA REFERENCE MANUAL 12-3 For More Information On This Product, Go to: www.freescale.com...
Page 131: Spi_Mosi (Master Out, Slave In)
Supervisor Only 10008004 ISPI Interval Control Register (SPICR) Supervisor Only 10008006 ISPI Status Register (SPSR) Supervisor Only 10008008 Reserved Supervisor Only 10008FFF MOTOROLA INTERVAL MODE SERIAL PERIPHERAL INTERFACE MMC2001 12-4 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 132: Ispi Data Register
SPCR — ISPI Control Register 10008002 DOZE SPI_EN SNS MSTR IRQ_EN PHA SPIGP BAUD RATE CLOCK COUNT RESET: Figure 12-4 ISPI Control Register MMC2001 INTERVAL MODE SERIAL PERIPHERAL INTERFACE MOTOROLA REFERENCE MANUAL 12-5 For More Information On This Product, Go to: www.freescale.com...
Page 133 IRQ_EN — Interrupt Request Enable This bit enables/disables the ISPI interrupt request output signal. This bit is cleared to zero on reset. 0 = Interrupts disabled 1 = Interrupts enabled MOTOROLA INTERVAL MODE SERIAL PERIPHERAL INTERFACE MMC2001 12-6 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 134: Clock Count Field Settings
16 bits can be transferred. A count of all zeros causes the ISPI to be disabled. Table 12-3 CLOCK COUNT Field Settings Value Meaning 0000 Disable ISPI 0001 2-bit transfer 0111 8-bit transfer 1111 16-bit transfer MMC2001 INTERVAL MODE SERIAL PERIPHERAL INTERFACE MOTOROLA REFERENCE MANUAL 12-7 For More Information On This Product, Go to: www.freescale.com...
Page 135: Ispi Interval Control Register
SPSR — ISPI Status Register 10008006 RESET: Figure 12-6 ISPI Status Register MOTOROLA INTERVAL MODE SERIAL PERIPHERAL INTERFACE MMC2001 12-8 REFERENCE MANUAL For More Information On This Product,...
Page 136: Ispi Programming Examples
To program the ISPI to perform such a transfer: 1. Write ISPI register SPCR to 0x4E4B. 2. Write ISPI register SPDR to 0x0013. MMC2001 INTERVAL MODE SERIAL PERIPHERAL INTERFACE MOTOROLA REFERENCE MANUAL 12-9 For More Information On This Product, Go to: www.freescale.com...
Page 137: Slave Mode Example
61 * 2 * (671 + 2) + (61 * 64 * 11) = 125.05 µs. The ISPI interval timer begins as soon as written, following the transfer period. This leaves approximately 1406 HI_REFCLK cycles before the Tx data register must be re-written. MOTOROLA INTERVAL MODE SERIAL PERIPHERAL INTERFACE MMC2001 12-10...
Page 138: Ispi Operation In Low-Power System Modes
IRQ bit in the SPI status register is disabled. Normally the IRQ bit is cleared on a read or write access to the SPDR. MMC2001 INTERVAL MODE SERIAL PERIPHERAL INTERFACE MOTOROLA REFERENCE MANUAL 12-11 For More Information On This Product,...
Page 139 Freescale Semiconductor, Inc. MOTOROLA INTERVAL MODE SERIAL PERIPHERAL INTERFACE MMC2001 12-12 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 140: External Interrupts/Gpio (Edge Port)
The interrupt request function on these pins is masked in the interrupt controller fast interrupt enable register (FIER) and nor- mal interrupt enable register (NIER). MMC2001 EXTERNAL INTERRUPTS/GPIO (EDGE PORT) MOTOROLA REFERENCE MANUAL 13-1 For More Information On This Product, Go to: www.freescale.com...
Page 141: Edge Port Programming Model
Pins configured as edge-sensitive interrupts are latched and need not remain asserted for interrupt generation. When the pin is programmed to use the edge detecting circuit, its state is monitored regardless of its configuration as input or out- put. MOTOROLA EXTERNAL INTERRUPTS/GPIO (EDGE PORT) MMC2001 13-2...
Page 142: Edge Port Data Direction Register (Epddr)
EPDR — Edge Port Data Register 10007004 EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPD0 RESET: X = Unaffected by reset Figure 13-4 Edge Port Data Register MMC2001 EXTERNAL INTERRUPTS/GPIO (EDGE PORT) MOTOROLA REFERENCE MANUAL 13-3 For More Information On This Product, Go to: www.freescale.com...
Page 143: Edge Port Flag Register (Epfr)
EPFR. The outputs of this register drive the cor- responding input of the interrupt controller for those bits configured as edge detecting. These bits are cleared by hardware reset. MOTOROLA EXTERNAL INTERRUPTS/GPIO (EDGE PORT) MMC2001...
Page 144: Keypad Port
256 Hz Keypad Matrix Up to 8 x 8 Row Enable Controls (KPCR) Pad Drivers KDDR[7:0] Pull-up/Data Direction Controls (KDDR) Figure 14-1 KPP Block Diagram MMC2001 KEYPAD PORT MOTOROLA REFERENCE MANUAL 14-1 For More Information On This Product, Go to: www.freescale.com...
Page 145: Kpp Pin Description
The keypad control register (KPCR) determines which of the eight possible column strobes are to be open drain when configured as outputs and which of the eight row sense lines are considered in generating an interrupt to the CPU. MOTOROLA KEYPAD PORT MMC2001...
Page 146: Keypad Status Register (Kpsr)
The KPKR bit may be used to generate a maskable key release interrupt. The key release synchronizer may be set high by software after scanning the keypad to ensure a known state. MMC2001 KEYPAD PORT MOTOROLA REFERENCE MANUAL 14-3 For More Information On This Product, Go to: www.freescale.com...
Page 147: Keypad Status Register
KPKR is cleared by writing a logic one into this bit. KPKD — Keypad Key Depress 0 = No key presses detected 1 = A key has been depressed KPKD is cleared by writing a logic one into this bit. MOTOROLA KEYPAD PORT MMC2001 14-4 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 148: Keypad Data Direction Register (Kddr)
* Since pins default to inputs, reset value is determined by the logic level present on the pins at reset. Figure 14-5 Keypad Data Register MMC2001 KEYPAD PORT MOTOROLA REFERENCE MANUAL 14-5 For More Information On This Product, Go to: www.freescale.com...
Page 149: Keypad Operation
The basic period is the period between the scan of two consec- utive columns, so the debounce time between two consecutive scans of the whole matrix equals the number of columns multiplied by the basic period. MOTOROLA KEYPAD PORT MMC2001...
Page 150: Keypad Standby
S-R latch and remains asserted until cleared by soft- ware. The set input of the latch is clocked on the rising edge. MMC2001 KEYPAD PORT MOTOROLA REFERENCE MANUAL 14-7 For More Information On This Product,...
Page 151: Multiple Key Closures
As can be seen in Figure 14-7, three keys pressed simultaneously can short between the column currently “scanned” by software and another column. Depending on the location of the third key pressed, a “ghost” key press may be detected. MOTOROLA KEYPAD PORT MMC2001 14-8...
Page 152: Typical Keypad Configuration And Scanning Sequence
Sample row inputs and save data. Multiple key presses can be detected on a single column. g. Repeat steps b to f for remaining columns. h. Return all columns to zero in preparation for standby mode. MMC2001 KEYPAD PORT MOTOROLA REFERENCE MANUAL 14-9 For More Information On This Product, Go to: www.freescale.com...
Page 153 KPKR synchronizer chain, clear the KPKD synchronizer chain. j. Re-enable the appropriate keypad interrupt(s); KDIE to detect a key hold condition, or KRIE to detect a key release event. MOTOROLA KEYPAD PORT MMC2001 14-10 REFERENCE MANUAL For More Information On This Product,...
Page 154: Pulse Width Modulator
6 kHz and 8 kHz. Figure 15-2 relates the pulse stream to the filtered audio output. Pulse Stream Filtered Audio Figure 15-2 PWM Generating Audio MMC2001 PULSE WIDTH MODULATOR MOTOROLA REFERENCE MANUAL 15-1 For More Information On This Product, Go to: www.freescale.com...
Page 155: Pwm Programming Model
This section describes the registers and control bits in the PWM module. All registers reset to 0x0000 after reset. These registers must be accessed with halfword accesses. Accesses other than half- word in size result in undefined activity. MOTOROLA PULSE WIDTH MODULATOR MMC2001 15-2...
Page 156: Pwm Address Map
Supervisor Only 1000502E PWM5 Counter Register (PWMCTR5) Supervisor Only 10005030 Reserved Supervisor Only 10005FFF 10006000 Not Used (Access causes transfer error) Not Applicable 10006FFF MMC2001 PULSE WIDTH MODULATOR MOTOROLA REFERENCE MANUAL 15-3 For More Information On This Product, Go to: www.freescale.com...
Page 157: Pwm Control Register
Setting this bit forces a new period. The period and width registers are loaded into the comparator latches and the counter is reset. This bit is cleared automatically after the load has been performed. The actual load occurs some time after the CPU writes this MOTOROLA PULSE WIDTH MODULATOR MMC2001...
Page 158 To prevent this, write the interrupt enable control bit (IRQ_EN) to zero when disabling the counter. MMC2001 PULSE WIDTH MODULATOR MOTOROLA REFERENCE MANUAL 15-5 For More Information On This Product, Go to: www.freescale.com...
Page 159: Pwm Period Register
PERIOD = 0, the output is never set high (0% duty cycle). In this case, the compara- tor is loaded and the counter reset on every PCLK. In addition, if enabled, an interrupt request is generated on every PCLK. MOTOROLA PULSE WIDTH MODULATOR MMC2001...
Page 160: Pwm Width Register
PWMCTR5 — PWM5 Counter Register 1000502E COUNT RESET: Figure 15-7 PWM Count Registers COUNT — Count Value This is the current count value. MMC2001 PULSE WIDTH MODULATOR MOTOROLA REFERENCE MANUAL 15-7 For More Information On This Product, Go to: www.freescale.com...
Page 161: Pwm Operating Range
In stop mode, the PWM halts immediately (due to halting of system clocks) and forgets the state of any period (the state machine is reset, and the shift register is cleared). It is assumed that when stop is initiated, the channels have been disabled. MOTOROLA PULSE WIDTH MODULATOR MMC2001...
Page 162: Once™ Debug Module
Data may then be scanned in and used to update a register or resource on a write to the resource, or data associated with a resource may be scanned out for a read of the resource. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-1 For More Information On This Product, Go to: www.freescale.com...
Page 163: Once Controller
Exit1 - IR Pause - DR Pause - IR Exit2 - DR Exit2 - IR Update - DR Update - IR Figure 16-2 OnCE Controller MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-2 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 164: Once Pins
The debug mode select input is used to cycle through states in the OnCE debug con- troller. Toggling the TMS pin while clocking with TCK controls the transitions through the TAP state controller. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-3 For More Information On This Product, Go to: www.freescale.com...
Page 165: Test Reset (Trst)
OnCE Decoder Controller ISTRACE ISDR Status and Control Registers Register Write Register Read Mode Select CPU Control/Status Figure 16-3 OnCE Controller and Serial Interface MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-4 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 166: Once Interface Signals
16.5.6 CPU Status (PSTAT) The trace logic uses the CPU PSTAT signals to qualify trace count decrements with specific CPU activity. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-5 For More Information On This Product, Go to: www.freescale.com...
Page 167: Once Debug Output (Debug)
In addition, the update-DR state must also be transitioned through in order for the single-step and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it. The command register is shown in Figure 16-4. MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-6...
Page 168: Once Command Register
The register select bits define the source or destination register for the read or write operation, respectively. Table 16-1 shows OnCE register addresses. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-7 For More Information On This Product, Go to: www.freescale.com...
Page 169: Once Control Register
OnCE logic. The control bits are read/write. OCR — OnCE Control Register RESET: IDRE FRZC RESET: Figure 16-5 OnCE Control Register MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-8 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 170: Sequential Control Field Settings
Logic). This bit is cleared on test logic reset. Trace operation is also affected by the SQC field described above. 0 = Disable trace operation 1 = Enable trace operation MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-9 For More Information On This Product, Go to: www.freescale.com...
Page 171: Memory Breakpoint Control Field Settings
Qualify match with any supervisor data access Qualify match with any supervisor change of flow access Qualify match with any supervisor data write Qualify match with any supervisor data read Reserved MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-10 REFERENCE MANUAL For More Information On This Product,...
Page 172: Once Status Register
B event has occurred to enable trace counter operation. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-11 For More Information On This Product,...
Page 173: Once Decoder (Odec)
Using address comparators to set breakpoints enables the user to set breakpoints in RAM or ROM in any operating mode. Memory accesses are monitored according to the contents of the OCR. MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-12...
Page 174: Memory Address Latch (Mal)
(ISBKPTx asserted). 16.8.1 Memory Address Latch (MAL) The memory address latch (MAL) is a 32-bit register that latches the address bus on every access. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-13 For More Information On This Product, Go to: www.freescale.com...
Page 175: Breakpoint Address Base Registers (Baba, Babb)
(The OnCE trace logic is independent of the M•CORE trace facility, which is controlled through the trace mode bits in the M•CORE processor status reg- ister). The OnCE trace logic block diagram is shown in Figure 16-8. MOTOROLA OnCE™ DEBUG MODULE MMC2001...
Page 176: Trace Counter (Otc)
When debug mode is exited, the counter is decremented after each execution of an instruction. Interrupts can be serviced, and all instructions executed (including inter- rupt services) will decrement the trace counter. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-15 For More Information On This Product, Go to: www.freescale.com...
Page 177: Methods Of Entering Debug Mode
When the OnCE trace mode mechanism is enabled and the trace count is greater than zero, the trace counter is decremented for each instruction executed. Complet- ing execution of an instruction when the trace counter is zero causes the CPU to enter debug mode. MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-16...
Page 178: Enabling Once Memory Breakpoints
Figure 16-9 shows the block diagram of the pipeline information registers contained in the CPUSCR. WBBR Figure 16-9 CPU Scan Chain Register (CPUSCR) MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-17 For More Information On This Product, Go to: www.freescale.com...
Page 179: Program Counter Register (Pc)
GO and EX bits set and not ignored. Set these bits to ones while instructions are executed during a debug session. CTL — Control State Register Reserved Reserved RESET: Figure 16-10 Control State Register MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-18 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 180: Write-Back Bus Register (Wbbr)
This register is affected by the operations performed in debug mode and must be restored by the external command controller when returning to normal mode. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-19 For More Information On This Product, Go to: www.freescale.com...
Page 181: Instruction Address Fifo Buffer (Pc Fifo)
PC FIFO Register 4 PC FIFO Register 5 PC FIFO Register 6 PC FIFO Register 7 PC FIFO Shift Register Figure 16-11 OnCE PC FIFO MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-20 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 182: Reserved Test Control Registers (Reserved, Mem_Bist, Ftcr, Lsrl)
16.14 Target Site Debug System Requirements A typical debug environment consists of a target system in which the MMC2001 resides in the user-defined hardware. MMC2001 OnCE™ DEBUG MODULE MOTOROLA REFERENCE MANUAL 16-21 For More Information On This Product, Go to: www.freescale.com...
Page 183: Interface Connector For Jtag/Once Serial Port
Note: GPIO/SI and GPIO/SO are not required for OnCE operation at this time. These pins can be used for high speed downloads with a recommended interface. Figure 16-12 Recommended Connector Interface to JTAG/OnCE Port MOTOROLA OnCE™ DEBUG MODULE MMC2001 16-22...
Page 184: Appendix Aelectrical Characteristics
Supply Current at 2.0 V @ 34 MHz µA STOP — CC_stop DOZE — CC_doze WAIT — CC_wait — CC_run Pin Capacitance — Load Capacitance — MMC2001 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 185: Clock Input Specifications
Value (periodically sampled and not 100% tested) max: 5.5 * T µs MOD Setup Time to RSTOUT Negation + 0.05 122.12 — MOD Hold Time — — MOTOROLA ELECTRICAL CHARACTERISTICS MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 186: External Interrupt Timing Specifications
Table A-5 External Interrupt Timing Specifications Characteristic Symbol Unit Minimum Edge-Triggered INTn Width High 2 * T 60.8 — Minimum Edge-Triggered INTn Width Low 2 * T 60.8 — MMC2001 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 187: Eim Timing Specifications
1. Output timing is measured at the pin. The specifications assume a capacitive load of 50 pF. 2. EB outputs are asserted for reads if the EBC bit in the corresponding CS control register is cleared MOTOROLA ELECTRICAL CHARACTERISTICS MMC2001...
Page 188: Eim Read/Write Timing
(Read) (WEN=0) (Write) EB (WEN=1) (Write) OE, EB (WSC=0) Data In (Read) Data Out (WSC>0) (Write) (WSC=0) Data Out (Write) Figure A-5 EIM Read/Write Timing MMC2001 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 189: Ispi Timing Specifications
Fall Time (20% V to 70% V = 20pF) Manual/Interval Mode Slave Mode Sequential Transfer Delay — SCLK NOTES: 1. Signal depends on software in interval mode. MOTOROLA ELECTRICAL CHARACTERISTICS MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 190: Spi Slave Timing (Pha = 0
NOTE: PD — Port data is not defined, but normally LSB of character previously transmitted (likely not to be LSB in slave mode). Figure A-7 SPI Slave Timing (PHA = 1) MMC2001 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 191: Spi Manual/Interval Mode Timing (Pha = 0
MSB IN DATA (Input) NOTE: The sequential transfer delay is determined by the settings in the SPI interval control register. Figure A-9 SPI Manual/Interval Mode Timing (PHA = 1) MOTOROLA ELECTRICAL CHARACTERISTICS MMC2001 REFERENCE MANUAL For More Information On This Product,...
Page 192: Once Timing Specifications
TCK Low to TDO High Z Assert Time TRST — Setup Time to TCK Low TRST — Figure A-10 Test Clock Input Timing TRST Figure A-11 TRST Timing MMC2001 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 193 Freescale Semiconductor, Inc. V IL Input Data Valid Output Data Valid Output Data Valid Figure A-12 Test Access Port Timing MOTOROLA ELECTRICAL CHARACTERISTICS MMC2001 A-10 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 194: Overview
*Pin 12 must be grounded for proper operation but is NOT a system ground. Figure B-1 144-Lead Plastic Thin Quad Flat Pack Pin Assignment MMC2001 PACKAGING AND PIN ASSIGNMENTS MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 195 Freescale Semiconductor, Inc. MOTOROLA PACKAGING AND PIN ASSIGNMENTS MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 196: Appendix Cprogramming Reference
30000000 – 30007FFF On-Chip RAM Array Supervisor, Selective User 30008000 – 3000FFFF RAM Echoes Supervisor, Selective User Not Used 30100000 – 40000000 — (Access causes transfer error) MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 197: Interrupt Controller Programming Model
“sources” in the appropriate interrupt enable register(s) (NIER, FIER). C.2.2 Normal Interrupt Enable Register (NIER) Access the 32-bit normal interrupt enable register with 32-bit loads and stores only. MOTOROLA PROGRAMMING REFERENCE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 198: Fast Interrupt Enable Register (Fier
EFx — Enable Fast Interrupt Flag x This bit enables the corresponding interrupt source to request a fast interrupt. 0 = Disable 1 = Enable A reset operation clears this bit. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 199: Normal Interrupt Pending Register (Nipnd
FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 RESET: FP15 FP14 FP13 FP12 FP11 FP10 RESET: Figure C-5 Fast Interrupt Pending Register MOTOROLA PROGRAMMING REFERENCE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 200: Timer/Reset Programming Model
This status and control register gives the state of the reset sources and serves to control the CLKOUT pin. Writes to this register clear any previously set status bits. Access this register with 32-bit loads and stores only. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 201: Reset Source Register
WDR — Watchdog Reset This bit is set when the watchdog timer expires. It is cleared by POR, a qualified assertion of the RSTIN pin, a qualified assertion of the LVRSTIN pin, or by writing to RSCR. MOTOROLA PROGRAMMING REFERENCE MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 202: Time-Of-Day Control/Status Register (Todcsr
TODFR is cleared to all zeros. TODSR is not affected by the watchdog reset or by a reset initiated by the external reset signal, but is undefined after a POR. Access this register with 32-bit loads and stores only. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 203: Tod Fraction Register (Todfr
For proper alarm operation, the fraction alarm register must be (re)written after a write to this register. This register is not affected by any of the reset conditions. Access this register with 32-bit loads and stores only. MOTOROLA PROGRAMMING REFERENCE MMC2001...
Page 204: Tod Fraction Alarm Register (Todfar
The write-once bits can only be written once after a reset condi- tion. Subsequent attempts to write to them will not affect the data previously written. Access this register with 32-bit loads and stores only. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 205: Watchdog Service Register (Wsr
WDR bit in the reset source register and asserts a system reset. Both writes must occur in the order listed prior to the time-out, but any number of instructions can be executed between the two writes. Access this register with 32-bit loads and stores only. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-10...
Page 206: Pit Control/Status Register (Itcsr
This bit controls the function of the PIT in debug mode 0 = PIT function is not affected while in debug mode 1 = PIT function is frozen while in debug mode MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-11 For More Information On This Product, Go to: www.freescale.com...
Page 207: Pit Data Register (Itdr
OVW bit set to one. The counter value can be read from the PIT alternate data register. Access this register with 32-bit loads and stores only. MOTOROLA PROGRAMMING REFERENCE MMC2001...
Page 208: Pit Alternate Data Register (Itadr
Keypad Status Register (KPSR) Supervisor Only 10003004 Keypad Data Direction Register (KDDR) Supervisor Only 10003006 Keypad Data Register (KPDR) Supervisor Only 10003008 Reserved Supervisor Only 10003FFF MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-13 For More Information On This Product, Go to: www.freescale.com...
Page 209: Keypad Control Register (Kpcr
1 = An interrupt request is generated when KPKD is set KRSS — Key Release Synchronizer Set The key release synchronizer is set by writing a logic one into this bit. Reads return a value of zero. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-14...
Page 210: Keypad Data Direction Register (Kddr
Otherwise, the value read is the value stored in the register. The KPDR register is byte or halfword addressable. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-15 For More Information On This Product, Go to: www.freescale.com...
Page 211: Eim Programming Model
For CS1–CS3 control registers, bits two to 15 (i.e., bits other than the PA and CSEN bits) are undefined at reset. Access these registers with 32-bit loads and stores only. MOTOROLA PROGRAMMING REFERENCE MMC2001...
Page 212: Cs0 Control Register
CSA=0, WSC=0001 and WWS=1 for access to Flash memory (two-clock read access and three-clock write access), EDC, CSA and WSC to the appropriate number for access to an LCD controller. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-17 For More Information On This Product, Go to: www.freescale.com...
Page 213: Wait State Control Field Settings
0 = Chip select is asserted normally, i.e., as early as possible. No idle cycle is inserted between back-to-back external transfers. 1 = Chip select is asserted a clock later during both read and write cycles. In addition, an idle cycle is inserted between back-to-back external transfers. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-18...
Page 214: Data Port Size Field Settings
TEA to the CPU and no assertion of the chip select output. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-19 For More Information On This Product, Go to: www.freescale.com...
Page 215: Eim Configuration Register
When the chip select is enabled, the PA control bit is ignored. C.5.2 EIM Configuration Register The EIM configuration register contains control bits that configure the EIM and other internal blocks for certain operation modes. Access this register with 32-bit loads and stores only. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-20 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 216: Eim Configuration Register
This bit is ignored if SHEN is cleared. 0 = Lower internal data bus bits DATA[15:0] are driven externally. 1 = Upper internal data bus bits DATA[31:16] are driven externally. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-21 For More Information On This Product, Go to: www.freescale.com...
Page 217: Pwm Module
PWM3 Width Register (PWMWR3) Supervisor Only 1000501E PWM3 Counter Register (PWMCTR3) Supervisor Only 10005020 PWM4 Control Register (PWMCR4) Supervisor Only 10005022 PWM4 Period Register (PWMPR4) Supervisor Only MOTOROLA PROGRAMMING REFERENCE MMC2001 C-22 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 218: Pwm Control Register
0 = PWM channel is unaffected in doze mode 1 = PWM channel is disabled in doze mode At reset, this bit is cleared to zero. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-23 For More Information On This Product, Go to: www.freescale.com...
Page 219 1 = Inverted PWM polarity MODE — PWM Mode This bit selects whether the PWM pin is used for GPIO or for the PWM function. 0 = General-purpose I/O mode 1 = PWM mode MOTOROLA PROGRAMMING REFERENCE MMC2001 C-24 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 220: Pwm Period Register
PCLKs in the period. When the counter value matches the value in this register, an interrupt is posted and the counter is reset to start another period. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-25 For More Information On This Product,...
Page 221: Pwm Width Register
1000502C WIDTH RESET: Figure C-26 PWM Width Registers WIDTH — Pulse Width When the counter reaches the value in this register, the output is reset. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-26 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 222: Pwm Counter Register
Requests are always generated out of this block but may be masked within the interrupt controller module. The functionality of this register is independent of the programmed pin direction. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-27 For More Information On This Product, Go to: www.freescale.com...
Page 223: Edge Port Data Direction Register (Epddr
Pin direction is independent of the level/edge mode programmed. EPDDR — Edge Port Data Direction Register 10007002 EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0 RESET: Figure C-29 Edge Port Data Direction Register MOTOROLA PROGRAMMING REFERENCE MMC2001 C-28 REFERENCE MANUAL For More Information On This Product,...
Page 224: Edge Port Data Register (Epdr
When a pin is configured as a general-purpose output, writes to EPDR which cause the selected level or edge MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-29 For More Information On This Product,...
Page 225: Ispi Programming Model
COUNT field in the ISPI control register. For example, if the exchange length is ten bits (CLOCK COUNT = 0x9), the MSB of the outgoing data is bit nine. The first bit presented to the external device is bit nine, followed by the remaining nine less signif- icant bits. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-30...
Page 226: Ispi Control Register
SPI_EN pin is an output. If the SPI_EN pin is an input, then it is active low, and the SNS bit has no effect. 0 = SPI_EN pin is active low 1 = SPI_EN pin is active high MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-31 For More Information On This Product, Go to: www.freescale.com...
Page 227 These bits select the baud rate of the ISPI bit clock based on divisions of the system clock. The master clock for the ISPI is HI_REFCLK. Table C-15 BAUD RATE Values Value Divide By 1024 MOTOROLA PROGRAMMING REFERENCE MMC2001 C-32 REFERENCE MANUAL For More Information On This Product,...
Page 228: Ispi Interval Control Register
Each bit-clock period, the value in this counter is decremented by one. When the value in the register reaches zero, then XCH is set, and a new transfer is begun. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-33 For More Information On This Product, Go to: www.freescale.com...
Page 229: Ispi Status Register
All UART registers may be accessed either as a halfword or as a byte. The RX and TX data registers may also be accessed as 32-bit words. For these registers the upper 16 bits are forced to zeros. MOTOROLA PROGRAMMING REFERENCE MMC2001...
Page 230: Uart Module Address Map
Supervisor Only 1000A08E UART1 Port Data Register (U1PDR) Supervisor Only 1000A088 Reserved Supervisor Only 1000AFFF 1000B000 Not Used (Access causes transfer error) Not Applicable 1FFFFFFF MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-35 For More Information On This Product, Go to: www.freescale.com...
Page 231: Uart Receive Register (Urx
FRMERR — Frame Error When set, this read-only bit indicates that the current character had a framing error (missing stop bit). The data is possibly corrupted. This bit is updated for each charac- ter read from the FIFO. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-36...
Page 232: Uart Transmit Register (Utx
U1TX — UART1 Transmit Register 1000A040* TX DATA RESET: *Echoes begin at 10009044 and 1000A044 respectively. X = Undefined Figure C-37 UART Transmit Register MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-37 For More Information On This Product, Go to: www.freescale.com...
Page 233: Uart Control Register 1 (Ucr1
This bit enables or disables the transmitter. While UARTEN and TXEN bits are set, and DOZE bit is cleared, the transmitter is enabled. If this bit is cleared in the middle of a transmission, the UART disables the transmitter immediately and starts marking ones. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-38...
Page 234: Rxfl Field Settings
UART status register. 0 = RTS interrupt disabled 1 = RTS interrupt enabled At reset, this bit is cleared to zero. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-39 For More Information On This Product, Go to: www.freescale.com...
Page 235: Uart Control Register 2 (Ucr2
U0CR2 — UART0 Control Register 2 10009082 U1CR2 — UART1 Control Register 2 1000A082 IRTS CTSC PREN PROE STPB RESET: Figure C-39 UART Control Register 2 MOTOROLA PROGRAMMING REFERENCE MMC2001 C-40 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 236 0 = One stop bit transmitted 1 = Two stop bits transmitted At reset, this bit is cleared to zero. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-41 For More Information On This Product, Go to: www.freescale.com...
Page 237: Uart Brg Register (Ubrgr
FIFOs. U0SR — UART0 Status Register 10009086 U1SR — UART1 Status Register 1000A086 RTSS TRDY RRDY MPTY RTSD RESET: Figure C-41 UART Status Register MOTOROLA PROGRAMMING REFERENCE MMC2001 C-42 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 238: Uart Test Register (Utsr
The UART test register is a read/write register. Unimplemented bits always return zero when read. This register contains miscellaneous bits to control test features of the UART block. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-43 For More Information On This Product, Go to: www.freescale.com...
Page 239: Uart Port Control Register (Upcr
The read/write UART port control register controls the functionality of UART GPIO pins. U0PCR — UART0 Port Control Register 1000908A U1PCR — UART1 Port Control Register 1000A08A RESET: Figure C-43 UART Port Control Register MOTOROLA PROGRAMMING REFERENCE MMC2001 C-44 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 240: Uart Data Direction Register (Uddr
One method for doing this is to configure the missing pins as general-purpose outputs. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-45 For More Information On This Product, Go to: www.freescale.com...
Page 241: Once Registers
1 = Leave debug mode RS — Register Select The register select bits define the source or destination register for the read or write operation, respectively. Table C-20 indicates the OnCE register addresses. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-46 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 242: Once Control Register (Ocr
OnCE logic. The con- trol bits are read/write. OCR — OnCE Control Register RESET: IDRE FRZC RESET: Figure C-47 OnCE Control Register MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-47 For More Information On This Product, Go to: www.freescale.com...
Page 243: Sequential Control Field Definition
B occurs, or freezing the PC FIFO from further updates when memory breakpoint B occurs while allowing the CPU to continue execution. The PC FIFO remains frozen until the FRZO bit in the OSR is cleared. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-48...
Page 244: Memory Breakpoint Control Field Definition
Qualify match with any supervisor change of flow access Qualify match with any supervisor data write Qualify match with any supervisor data read Reserved MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-49 For More Information On This Product, Go to: www.freescale.com...
Page 245: Once Status Register (Osr
This read-only status bit is set when sequential operation is enabled and a memory breakpoint B event has occurred to enable trace counter operation. This bit is cleared on test logic reset or when debug mode is exited with the GO and EX bits set. MOTOROLA PROGRAMMING REFERENCE MMC2001...
Page 246: Memory Address Latch (Mal
The program counter register (PC) is a 32-bit latch that stores the value of the pro- gram counter that was present when the chip entered debug mode. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-51 For More Information On This Product,...
Page 247: Instruction Register (Ir
16-bit size, i.e., 0b10. This field should be restored to its original value after a debug session is completed, i.e., when a OnCE command is issued with the GO and EX bits set and not ignored. MOTOROLA PROGRAMMING REFERENCE MMC2001...
Page 248: Write-Back Bus Register (Wbbr
These registers are reserved for factory testing. WARNING To prevent damage to the device or system, do not access these registers during normal operation. MMC2001 PROGRAMMING REFERENCE MOTOROLA REFERENCE MANUAL C-53 For More Information On This Product, Go to: www.freescale.com...
Page 249 Freescale Semiconductor, Inc. MOTOROLA PROGRAMMING REFERENCE MMC2001 C-54 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 250 CD bit 11-13, C-42 CHARRDY bit 11-7, C-36 –D– Chip Select 4-4, 7-2 Assert bit 7-9, C-18 Control Registers 7-7, C-16 DATA (data bus) signals 4-4, 7-2 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 251 7-4 Freeze Control bit 16-10, C-48 Configuration Register 7-11, C-20 FRMERR bit 11-8, C-36 programming model 7-7 FRZC bit 16-10, C-48 signals 7-1 FRZO bit 16-11, C-50 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 252 IR 16-18, C-52 KPDR 14-5, C-15 IREN bit 11-11, C-39 KPKD bit 14-3, 14-4, C-15 IRQ bit 12-9, C-34 KPKR bit 14-3, 14-4, C-15 IRQ EN bit 15-4, C-24 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 253 16-6 Maximum ratings A-1 decoder 16-12 MBCA 16-14, C-51 interface signals 16-5 MBCB 16-14, C-51 operation 16-1 MBO bit 16-11, C-50 serial interface 16-5 Memory signals 16-3 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 254 Receive Data Register 12-5, C-30 PREN bit 11-12, C-41 Received Data bits 11-8, C-37 PRERR bit 11-8, C-37 Receiver 11-3 Prescaler, PWM 15-2 Enable bit 11-10, C-39 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 255 Show Cycle Enable bits 7-7, 7-12, C-22 TC field 16-19, C-53 Signals 4-1 TCK 4-5 edge port 13-1 TCK signal 16-3 EIM 7-1 TDI signal 4-5, 16-3 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 256 BRG Register 11-13, C-42 WDZE bit 9-11, C-10 Control Register 1 11-9, C-38 WEN bit 7-10, C-19 Control Register 2 11-11, C-40 WIDTH field 15-7, C-26 Data Direction Register 11-16 MMC2001 MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 257 WS bit 11-13, C-42 WSC bit 7-8, C-17 WSR 9-11, C-10 WSTP bit 9-11, C-10 WT field 9-10, C-10 WWS bit 7-9, C-18 –X– XCH bit 12-9, C-34 XOSCpin 4-5 MOTOROLA MMC2001 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 258 Section 1.1 Changed number of address lines in features list from 20 to 22 15 OCT 98 Section 11.2.1 Rewrote to clarify function of RTS pin Section 11.2.2 Rewrote to clarify function of CTS pin MMC2001 RECORD OF CHANGES MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 259 Freescale Semiconductor, Inc. This manual is a product of the Motorola M•Core Technology Center Design Documentation team. Technical writing, illustration, and production editing performed with Adobe® FrameMaker® running on multiple platforms. Cover graphic design by Bazzirk, Inc. of Austin, Texas. Printed by Imperial Lithographics, Phoenix, Arizona.

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