Page 1 CMOS 32-BIT SINGLE CHIP MICROCONTROLLER S1C31D50/D51 Technical Manual Rev. 2.00...
Page 2 2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed by the use of it.
Page 3 PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C31D50/D51. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. Notational conventions and symbols in this manual Register address Peripheral circuit chapters do not provide control register addresses.
Page 4: Table Of Contents
3.3.1 List of Debugger Input/Output Pins ............... 3-1 3.3.2 External Connection ....................3-1 4 Memory and Bus ......................4-1 4.1 Overview ......................... 4-1 4.2 Bus Access Cycle ......................4-2 4.3 Flash Memory ......................... 4-2 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 5 DMAC Primary-Alternate Clear Register ................6-13 DMAC Priority Set Register ....................6-13 DMAC Priority Clear Register ....................6-13 DMAC Error Interrupt Flag Register ..................6-13 DMAC Transfer Completion Interrupt Flag Register ............. 6-14 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 6 8.2 Peripheral Circuit I/O Function Assignment ..............8-1 8.3 Control Registers ......................8-2 Pxy–xz Universal Port Multiplexer Setting Register ............... 8-2 9 Watchdog Timer (WDT2) ....................9-1 9.1 Overview ......................... 9-1 9.2 Clock Settings ......................... 9-1 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 7 11.5.1 SVD3 Interrupt ..................... 11-4 11.5.2 SVD3 Reset ......................11-5 11.6 Control Registers ......................11-5 SVD3 Clock Control Register ....................11-5 SVD3 Control Register......................11-6 SVD3 Status and Interrupt Flag Register ................11-7 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 8 13.6.2 Parity Error ......................13-9 13.6.3 Overrun Error ....................... 13-9 13.7 Interrupts ........................13-10 13.8 DMA Transfer Requests ....................13-10 13.9 Control Registers ......................13-11 UART3 Ch.n Clock Control Register ................... 13-11 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 9 15.3 Clock Settings ......................15-6 15.3.1 QSPI Operating Clock ..................15-6 15.3.2 Clock Supply During Debugging ................. 15-7 15.3.3 QSPI Clock (QSPICLKn) Phase and Polarity ............15-7 15.4 Data Format ......................... 15-8 15.5 Operations ........................15-9 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 10 I2C Ch.n Mode Register ...................... 16-19 I2C Ch.n Baud-Rate Register ....................16-19 I2C Ch.n Own Address Register..................16-20 I2C Ch.n Control Register ....................16-20 I2C Ch.n Transmit Data Register ..................16-21 Seiko Epson Corporation viii S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 11 18.7 Control Registers ......................18-7 REMC3 Clock Control Register .................... 18-7 REMC3 Data Bit Counter Control Register ................18-8 REMC3 Data Bit Counter Register ..................18-9 REMC3 Data Bit Active Pulse Length Register ..............18-10 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 12 RFC Ch.n Measurement Counter Low and High Registers ..........20-10 RFC Ch.n Time Base Counter Low and High Registers ............20-10 RFC Ch.n Interrupt Flag Register ..................20-11 RFC Ch.n Interrupt Enable Register ..................20-11 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 13 SDAC Data Register ......................21-28 SDAC Interrupt Flag Register ....................21-28 SDAC Interrupt Enable Register ..................21-29 22 Electrical Characteristics ..................22-1 22.1 Absolute Maximum Ratings ..................22-1 22.2 Recommended Operating Conditions ................. 22-1 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 14 0x0020 0840–0x0020 0850 R/F Converter (RFC) Ch.0 ........AP-A-51 0x0020 0860–0x0020 086a Sound DAC (SDAC) ..........AP-A-52 0x0020 08a0–0x0020 08a8 HW Processor (HWP) ..........AP-A-53 0x0020 1000–0x0020 2014 DMA Controller (DMAC) .......... AP-A-53 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 15 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Revision History Seiko Epson Corporation xiii S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 16: Overview
The S1C31D50/D51 is suitable for home electronics, white goods, and battery-based products, which require a voice and audio playback function. Furthermore, the S1C31D51 can realize a voice and audio playback function with a buzzer and a small number of external components without using an external audio amplifier.
Page 17 2.7 to 5.5 V (when V is generated internally) QSPI-Flash interface power voltage 3.0 to 3.6 V (voltage different from V can be supplied.) Operating temperature Operating temperature range -40 to 85 °C Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 18: Block Diagram
Sound DAC 2 Ch. SDACOUT_P (SDAC) EXCL00–03 SDACOUT_N EXCL10–13 1 Ch. * The pin configuration depends on the package. For detailed information, refer to Section 1.3, “Pins.” Figure 1.2.1 S1C31D50/D51 Block Diagram Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 19: Pins
P46/RTC1S P45/#ADTRG0 P40/VREFA0 OSC1 OSC1 OSC2 OSC2 P17/UPMUX/ADIN00 P83/EXOSC P16/UPMUX/ADIN01 P84/EXCL00 P15/UPMUX/ADIN02 P85/EXCL01 P14/UPMUX/ADIN03 P13/UPMUX/ADIN04 P72/EXCL10 P06/UPMUX P73/EXCL11 SWCLK/PD0 P05/UPMUX SWD/PD1 P04/UPMUX TEST TEST P03/UPMUX Figure 1.3.1.1 S1C31D50/D51 Pin Configuration Diagram (TQFP12-48PIN) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 20 OSC1 OSC1 OSC2 OSC2 P40/VREFA0 P17/UPMUX/ADIN00 P16/UPMUX/ADIN01 P83/EXOSC P84/EXCL00 P15/UPMUX/ADIN02 P85/EXCL01 P14/UPMUX/ADIN03 P13/UPMUX/ADIN04 P12/UPMUX/ADIN05 P11/UPMUX/ADIN06 P72/EXCL10 P06/UPMUX P73/EXCL11 SWCLK/PD0 P05/UPMUX SWD/PD1 P04/UPMUX TEST TEST P03/UPMUX Figure 1.3.1.2 S1C31D50/D51 Pin Configuration Diagram (QFP13-64PIN) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 21 OSC2 OSC2 P40/VREFA0 P83/EXOSC P17/UPMUX/ADIN00 P84/EXCL00 P16/UPMUX/ADIN01 P15/UPMUX/ADIN02 P85/EXCL01 P14/UPMUX/ADIN03 P13/UPMUX/ADIN04 P12/UPMUX/ADIN05 P11/UPMUX/ADIN06 P72/EXCL10 P10/UPMUX/ADIN07 P07/UPMUX P73/EXCL11 P06/UPMUX P05/UPMUX SWCLK/PD0 SWD/PD1 P04/UPMUX TEST TEST P03/UPMUX Figure 1.3.1.3 S1C31D50/D51 Pin Configuration Diagram (TQFP14-80PIN) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 22 P83/EXOSC P17/UPMUX/ADIN00 P84/EXCL00 P16/UPMUX/ADIN01 P85/EXCL01 P15/UPMUX/ADIN02 P14/UPMUX/ADIN03 P13/UPMUX/ADIN04 P12/UPMUX/ADIN05 P11/UPMUX/ADIN06 P72/EXCL10 P10/UPMUX/ADIN07 P73/EXCL11 P07/UPMUX P06/UPMUX P05/UPMUX SWCLK/PD0 P04/UPMUX SWD/PD1 P03/UPMUX TEST TEST P02/UPMUX P01/UPMUX P00/UPMUX Figure 1.3.1.4 S1C31D50/D51 Pin Configuration Diagram (QFP15-100PIN) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 23: Pin Descriptions
ADIN04 12-bit A/D converter Ch.0 analog signal input 4 Hi-Z – I/O port ✓ ✓ ✓ ✓ UPMUX User-selected I/O (universal port multiplexer) ADIN03 12-bit A/D converter Ch.0 analog signal input 3 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 24 ✓ ✓ ✓ ✓ RTC1S Real-time clock 1-second cycle pulse output Hi-Z I/O port – – – ✓ ✓ SDACOUT_P O (L) Sound DAC positive output ✓ ✓ ✓ ✓ ✓ I/O port Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 25 ✓ Hi-Z I/O port – – – ✓ ✓ Hi-Z I/O port – – – ✓ ✓ SWCLK I (Pull-up) Serial-wire debugger clock input ✓ ✓ ✓ ✓ ✓ I/O port Seiko Epson Corporation 1-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 26 T16B Ch.n PWM output/capture input 1 TOUTn2/CAPn2 T16B Ch.n PWM output/capture input 2 TOUTn3/CAPn3 T16B Ch.n PWM output/capture input 3 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation 1-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 27: Power Supply, Reset, And Clocks
Connection Diagram” chapter, respectively. DDQSPI is the power supply dedicated for the quad synchronous serial interface (QSPI-Flash). It is also used as DDQSPI the power supply for the I/O ports P90 to P95. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 28: D1 Regulator Operation Mode
(Set to automatic mode) 5. Switch the system clock to a high-speed clock. 6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 29: System Reset Controller (Src)
Reset request from CPU Watchdog timer reset Supply voltage detector reset SYSRST_S0_0 Software reset 0 To peripheral circuit 0 Reset decoder SYSRST_S0_n Software reset n To peripheral circuit n Figure 2.2.1.1 SRC Configuration Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 30: Input Pin
Note, however, that the software reset operations depend on the periph- eral circuit. For more information, refer to “Control Registers” in each peripheral circuit chapter. Note: The MODEN bit of some peripheral circuits does not issue software reset. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 31: Initialization Conditions (Reset Groups)
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation. • Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state. Figure 2.3.1.1 shows the CLG configuration. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 32: Input/Output Pins
2.3.3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 33 OSC3 pin open. For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 34 EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 35: Operations
Figure 2.3.4.2 shows an operation example when the oscillation start- up control circuit is used. (1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1N[1:0] setting gain Oscillation waveform Normal operation Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 36 In addition to the above, configure the following bits when using the crystal/ceramic oscillator: - CLGOSC3.OSC3INV[1:0] bits (Set oscillation inverter gain) Configure the following bits when using the internal oscillator: - CLGOSC3.OSC3FQ[1:0] bits (Select oscillation frequency) Seiko Epson Corporation 2-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 37 This allows flexible clock control according to the wake-up process. Configure the clock using the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit to enable this function. Seiko Epson Corporation 2-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 38 After the trimming operation has completed, the CLGOSC3.OSC3STM bit automatically reverts to 0. Although the trimming time depends on the temperature, an average of several 10 ms is required. Seiko Epson Corporation 2-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 39: Operating Mode
RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source. Seiko Epson Corporation 2-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 40 The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Reset request Seiko Epson Corporation 2-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 41: Interrupts
Bits 3–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the V regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGACTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode Seiko Epson Corporation 2-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 42: Clg System Clock Control Register
These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation 2-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 43: Clg Oscillation Control Register
Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation 2-17 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 44: Clg Iosc Control Register
This bit selects an oscillator type of the OSC1 oscillator circuit. 1 (R/WP): Internal oscillator 0 (R/WP): Crystal oscillator Bits 10–8 CGI1[2:0] These bits set the internal gate capacitance in the OSC1 oscillator circuit. Seiko Epson Corporation 2-18 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 45: Clg Osc3 Control Register
Bit name Initial Reset Remarks CLGOSC3 15–12 – – – 11–10 OSC3FQ[1:0] R/WP OSC3MD R/WP – – 7–6 – – 5–4 OSC3INV[1:0] R/WP OSC3STM R/WP 2–0 OSC3WT[2:0] R/WP Bits 15–12 Reserved Seiko Epson Corporation 2-19 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 46 These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit. Table 2.6.11 OSC3 Oscillation Stabilization Waiting Time Setting CLGOSC3.OSC3WT[2:0] bits Oscillation stabilization waiting time 65,536 clocks 16,384 clocks 4,096 clocks 1,024 clocks 256 clocks 64 clocks 16 clocks 4 clocks Seiko Epson Corporation 2-20 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 47: Clg Interrupt Flag Register
CLG Interrupt Enable Register Register name Bit name Initial Reset Remarks CLGINTE 15–9 – 0x00 – – OSC3TERIE – – (reserved) OSC1STPIE OSC3TEDIE – – OSC3STAIE OSC1STAIE IOSCSTAIE Bits 15–9, 7, 6, 3 Reserved Seiko Epson Corporation 2-21 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 48: Clg Fout Control Register
0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation 2-22 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 49: Cpu And Debugger
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up re- sistors R ” in the “Electrical Characteristics” chapter. R and R are not required when using the debug DBG1–2 DBG1 DBG2 pins as general-purpose I/O port pins. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 50: Memory And Bus
0x0003 0000 0x0003 0000 0x0002 ffff 0x0002 ffff Flash area (192K bytes) Flash area (192K bytes) (Device size: 32 bits) (Device size: 32 bits) 0x0000 0000 0x0000 0000 Figure 4.1.1 Memory Map Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 51: Bus Access Cycle
Flash memory. However, it is not necessary to discon- nect the wire when using Bridge Board (S5U1C31001L) to supply the V voltage, as Bridge Board controls the power supply so that it will be supplied during Flash programming only. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 52: Ram
0x0020 0204 PPORTP0RCTL P0 Port Pull-up/down Control Register 0x0020 0206 PPORTP0INTF P0 Port Interrupt Flag Register 0x0020 0208 PPORTP0INTCTL P0 Port Interrupt Control Register 0x0020 020a PPORTP0CHATEN P0 Port Chattering Filter Enable Register Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 53 0x0020 0284 PPORTP8RCTL P8 Port Pull-up/down Control Register 0x0020 0286 PPORTP8INTF P8 Port Interrupt Flag Register 0x0020 0288 PPORTP8INTCTL P8 Port Interrupt Control Register 0x0020 028a PPORTP8CHATEN P8 Port Chattering Filter Enable Register Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 54 0x0020 03b0 SPIA_0MOD SPIA Ch.0 Mode Register (SPIA) Ch.0 0x0020 03b2 SPIA_0CTL SPIA Ch.0 Control Register 0x0020 03b4 SPIA_0TXD SPIA Ch.0 Transmit Data Register 0x0020 03b6 SPIA_0RXD SPIA Ch.0 Receive Data Register Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 55 T16 Ch.3 Interrupt Flag Register 0x0020 048c T16_3INTE T16 Ch.3 Interrupt Enable Register 16-bit timer (T16) Ch.4 0x0020 04a0 T16_4CLK T16 Ch.4 Clock Control Register 0x0020 04a2 T16_4MOD T16 Ch.4 Mode Register Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 56 16-bit timer (T16) Ch.2 0x0020 0680 T16_2CLK T16 Ch.2 Clock Control Register 0x0020 0682 T16_2MOD T16 Ch.2 Mode Register 0x0020 0684 T16_2CTL T16 Ch.2 Control Register 0x0020 0686 T16_2TR T16 Ch.2 Reload Data Register Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 57 0x0020 07ae ADC12A_0DMAEN1 ADC12A Ch.0 DMA Request Enable Register 1 0x0020 07b0 ADC12A_0DMAEN2 ADC12A Ch.0 DMA Request Enable Register 2 0x0020 07b2 ADC12A_0DMAEN3 ADC12A Ch.0 DMA Request Enable Register 3 0x0020 07b4 ADC12A_0DMAEN4 ADC12A Ch.0 DMA Request Enable Register 4 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 58: System-Protect Function
This IC includes an instruction cache. Enabling the cache function translates into reduced current consumption, as the Flash memory access frequency is decreased. This function is enabled by setting the CASHECTL.CACHEEN bit to 1. Setting this bit to 0 clears the instruction codes stored in the cache. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 59: Memory Mapped Access Area For External Flash Memory
REGSEL bit = 0 REGSEL bit = 1 2.1 MHz (max.) 16.6 MHz (max.) 1.05 MHz (max.) 8.4 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation 4-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 60: Interrupt
• IOSC oscillation stabilization waiting completion • OSC1 oscillation stabilization waiting completion • OSC3 oscillation stabilization waiting completion • OSC1 oscillation stop • OSC3 oscillation auto-trimming completion • OSC3 oscillation auto-trimming error Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 61 • Overrun error • Receive buﬀer two bytes full • Receive buﬀer one byte full • Transmit buﬀer empty 16-bit timer Ch.0 interrupt Underﬂow VTOR + 0x90 16-bit timer Ch.3 interrupt Underﬂow Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 62: Vector Table Offset Address (Vtor)
CPU core even if the interrupt flag is set to 1. An interrupt request is also sent to the CPU core if the status is changed to interrupt enabled when the interrupt flag is 1. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 63: Nmi
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece- dence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 64: Dma Controller (Dmac)
• Priority level for each channel is selectable from two levels. • DMA transfers are allowed even if the CPU is placed into HALT mode. Figure 6.1.1 shows the configuration of the DMAC. Table 6.1.1 DMAC Channel Configuration of S1C31D50/D51 Item 48-pin package...
Page 65: Operations
256 bytes DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00) DMACCPTR.CPTR[31:0] + 0x080 9 to 16 512 bytes DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x100 16 to 32 1,024 bytes DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x200 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 66: Transfer Source End Pointer
6.4.2 Transfer Destination End Pointer Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if the transfer destination address is not incremented. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 67 When the DMAC is performing a successive transfer, it suspends the data transfer at the cycle set with R_pow- er. If DMA requests have been issued at that point, the DMAC re-arbitrates them according to their priorities and then performs a DMA transfer for the channel with the highest priority. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 68: Dma Transfer Mode
DMA transfer 1 DMA transfer 2 DMA transfer 3 DMA transfer 4 DMA transfer 7 DMA transfer 8 operation DMACENDIF.ENDIFn DMA transfer request Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2 = 2) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 69: Ping-Pong Transfer
5. Set cycle_ctrl to 0x0 after a DMA transfer completion interrupt has occurred by the next to last task. 6. The DMA transfer is completed when a DMA transfer completion interrupt occurs by the last task. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 70: Memory Scatter-Gather Transfer
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 71: Peripheral Scatter-Gather Transfer
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 72: Dma Transfer Cycle
The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 73: Control Registers
– 15–8 – 0x00 – – 7–1 – 0x00 – MSTEN – – Bits 31–1 Reserved Bit 0 MSTEN This bit enables the DMA controller. 1 (W): Enable 0 (W): Disable Seiko Epson Corporation 6-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 74: Dmac Control Data Base Pointer Register
DMA transfer requests from peripheral circuits have been disabled. 0 (R): DMA transfer requests from peripheral circuits have been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 75: Dmac Request Mask Clear Register
The alternate data structure has been enabled. 0 (R): The primary data structure has been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 76: Dmac Primary-Alternate Clear Register
ERRIF This bit indicates the DMAC error interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 6-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 77: Dmac Transfer Completion Interrupt Flag Register
DMAC Error Interrupt Enable Set Register Register name Bit name Initial Reset Remarks DMACERRIESET 31–24 – 0x00 – – 23–16 – 0x00 – 15–8 – 0x00 – 7–1 – 0x00 – ERRIESET Bits 31–1 Reserved Seiko Epson Corporation 6-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 78: Dmac Error Interrupt Enable Clear Register
0x00 – ERRIECLR – – Bits 31–1 Reserved Bit 0 ERRIECLR This bit disables DMA error interrupts. 1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.) 0 (W): Ineffective Seiko Epson Corporation 6-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 79: O Ports (Pport)
Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 7.1.1 shows the configuration of PPORT. Table 7.1.1 Port Configuration of S1C31D50/D51 Item 48-pin package...
Page 80: I/O Cell Structure And Functions
The input functions are all configured with the Schmitt interface level. When a port is set to input disable status (PPORTPxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is placed into floating status. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 81: Over Voltage Tolerant Fail-Safe Type I/O Cell
When using the chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be configured so that it will keep suppling by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 82: Clock Supply During Debugging
When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings: 1. Set the PPORTPxIOEN.PxOENy bit to 1. (Enable output) 2. Set the PPORTPxMODSEL.PxSELy bit to 0. (Enable GPIO function) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 83: Port Input/Output Control
7.4.2 Port Input/Output Control Peripheral I/O function control The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor- mation, refer to the respective peripheral circuit chapter. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 84: Interrupts
CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 85: Control Registers
When both data output and data input are enabled, the pin output status controlled by this IC can be read. These bits do not affect the input control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 86: Px Port Pull-Up/Down Control Register
These bits select the input signal edge to generate a port input interrupt. 1 (R/W): An interrupt will occur at a falling edge. 0 (R/W): An interrupt will occur at a rising edge. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 87: Px Port Chattering Filter Enable Register
These bits select the peripheral I/O function to be assigned to each port pin. Table 7.6.1 Selecting Peripheral I/O Function PPORTPxFNCSEL.PxyMUX[1:0] bits Peripheral I/O function Function 3 Function 2 Function 1 Function 0 This selection takes effect when the PPORTPxMODSEL.PxSELy bit = 1. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 88: P Port Clock Control Register
1/32,768 1/16,384 1/8,192 1/4,096 1/2,048 1/1,024 1/512 1/256 1/128 1/64 1/32 1/16 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation 7-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 89: P Port Interrupt Flag Group Register
A port generated an interrupt 0 (R): No port generated an interrupt The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 7-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 90: Control Register And Port Function Configuration Of This Ic
✓ P0OEN5 ✓ ✓ ✓ ✓ P0OEN4 ✓ ✓ ✓ ✓ P0OEN3 ✓ ✓ ✓ ✓ P0OEN2 – – – ✓ P0OEN1 – – – ✓ P0OEN0 – – – ✓ Seiko Epson Corporation 7-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 91 ✓ P0CHATEN5 ✓ ✓ ✓ ✓ P0CHATEN4 ✓ ✓ ✓ ✓ P0CHATEN3 ✓ ✓ ✓ ✓ P0CHATEN2 – – – ✓ P0CHATEN1 – – – ✓ P0CHATEN0 – – – ✓ Seiko Epson Corporation 7-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 92: P1 Port Group
✓ P1IN5 ✓ ✓ ✓ ✓ P1IN4 ✓ ✓ ✓ ✓ P1IN3 ✓ ✓ ✓ ✓ P1IN2 – ✓ ✓ ✓ P1IN1 – ✓ ✓ ✓ P1IN0 – – ✓ ✓ Seiko Epson Corporation 7-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 93 ✓ P1IE5 ✓ ✓ ✓ ✓ P1IE4 ✓ ✓ ✓ ✓ P1IE3 ✓ ✓ ✓ ✓ P1IE2 – ✓ ✓ ✓ P1IE1 – ✓ ✓ ✓ P1IE0 – – ✓ ✓ Seiko Epson Corporation 7-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 94 ✓ – – UPMUX ADC12A ADIN01 – – ✓ ✓ ✓ ✓ – – UPMUX ADC12A ADIN00 – – ✓ ✓ ✓ ✓ *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 95: P2 Port Group
✓ P2REN5 – ✓ ✓ ✓ P2REN4 – ✓ ✓ ✓ P2REN3 ✓ ✓ ✓ ✓ P2REN2 ✓ ✓ ✓ ✓ P2REN1 ✓ ✓ ✓ ✓ P2REN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-17 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 96 ✓ 9–8 P24MUX[1:0] – ✓ ✓ ✓ 7–6 P23MUX[1:0] ✓ ✓ ✓ ✓ 5–4 P22MUX[1:0] ✓ ✓ ✓ ✓ 3–2 P21MUX[1:0] ✓ ✓ ✓ ✓ 1–0 P20MUX[1:0] ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-18 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 97: P3 Port Group
✓ P3OEN5 – – ✓ ✓ P3OEN4 – ✓ ✓ ✓ P3OEN3 – ✓ ✓ ✓ P3OEN2 ✓ ✓ ✓ ✓ P3OEN1 ✓ ✓ ✓ ✓ P3OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-19 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 98 ✓ P3CHATEN5 – – ✓ ✓ P3CHATEN4 – ✓ ✓ ✓ P3CHATEN3 – ✓ ✓ ✓ P3CHATEN2 ✓ ✓ ✓ ✓ P3CHATEN1 ✓ ✓ ✓ ✓ P3CHATEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-20 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 99: P4 Port Group
✓ P4IN5 ✓ ✓ ✓ ✓ P4IN4 – ✓ ✓ ✓ P4IN3 – ✓ ✓ ✓ P4IN2 – – ✓ ✓ P4IN1 – – ✓ ✓ P4IN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-21 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 100 ✓ P4IE5 ✓ ✓ ✓ ✓ P4IE4 – ✓ ✓ ✓ P4IE3 – ✓ ✓ ✓ P4IE2 – – ✓ ✓ P4IE1 – – ✓ ✓ P4IE0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-22 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 101 – – – ✓ ✓ ✓ ✓ RTCA RTC1S – – – – – – ✓ ✓ ✓ ✓ – – – – – – – – – – – ✓ Seiko Epson Corporation 7-23 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 102: P5 Port Group
✓ P5REN5 – – – ✓ P5REN4 – – – ✓ P5REN3 – – ✓ ✓ P5REN2 – – ✓ ✓ P5REN1 ✓ ✓ ✓ ✓ P5REN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-24 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 103 ✓ 9–8 P54MUX[1:0] – – – ✓ 7–6 P53MUX[1:0] – – ✓ ✓ 5–4 P52MUX[1:0] – – ✓ ✓ 3–2 P51MUX[1:0] ✓ ✓ ✓ ✓ 1–0 P50MUX[1:0] ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-25 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 104: P6 Port Group
✓ P6OEN5 – – – ✓ P6OEN4 – – ✓ ✓ P6OEN3 – – ✓ ✓ P6OEN2 ✓ ✓ ✓ ✓ P6OEN1 ✓ ✓ ✓ ✓ P6OEN0 – – – ✓ Seiko Epson Corporation 7-26 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 105 ✓ P6CHATEN5 – – – ✓ P6CHATEN4 – – ✓ ✓ P6CHATEN3 – – ✓ ✓ P6CHATEN2 ✓ ✓ ✓ ✓ P6CHATEN1 ✓ ✓ ✓ ✓ P6CHATEN0 – – – ✓ Seiko Epson Corporation 7-27 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 106: P7 Port Group
✓ P7IN5 – – – ✓ P7IN4 – – ✓ ✓ P7IN3 ✓ ✓ ✓ ✓ P7IN2 ✓ ✓ ✓ ✓ P7IN1 – ✓ ✓ ✓ P7IN0 – ✓ ✓ ✓ Seiko Epson Corporation 7-28 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 107 ✓ P7IE5 – – – ✓ P7IE4 – – ✓ ✓ P7IE3 ✓ ✓ ✓ ✓ P7IE2 ✓ ✓ ✓ ✓ P7IE1 – ✓ ✓ ✓ P7IE0 – ✓ ✓ ✓ Seiko Epson Corporation 7-29 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 108 – – – – – – ✓ – – – – – – – – – – – ✓ – – – – – – – – – – – ✓ Seiko Epson Corporation 7-30 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 109: P8 Port Group
✓ P8REN5 ✓ ✓ ✓ ✓ P8REN4 ✓ ✓ ✓ ✓ P8REN3 ✓ ✓ ✓ ✓ P8REN2 – ✓ ✓ ✓ P8REN1 – ✓ ✓ ✓ P8REN0 – – ✓ ✓ Seiko Epson Corporation 7-31 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 110 ✓ 9–8 P84MUX[1:0] ✓ ✓ ✓ ✓ 7–6 P83MUX[1:0] ✓ ✓ ✓ ✓ 5–4 P82MUX[1:0] – ✓ ✓ ✓ 3–2 P81MUX[1:0] – ✓ ✓ ✓ 1–0 P80MUX[1:0] – – ✓ ✓ Seiko Epson Corporation 7-32 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 111: P9 Port Group
P9OEN5 – ✓ ✓ ✓ ✓ P9OEN4 ✓ ✓ ✓ ✓ P9OEN3 ✓ ✓ ✓ ✓ P9OEN2 ✓ ✓ ✓ ✓ P9OEN1 ✓ ✓ ✓ ✓ P9OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-33 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 112 P9SEL5 – ✓ ✓ ✓ ✓ P9SEL4 ✓ ✓ ✓ ✓ P9SEL3 ✓ ✓ ✓ ✓ P9SEL2 ✓ ✓ ✓ ✓ P9SEL1 ✓ ✓ ✓ ✓ P9SEL0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-34 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 113: Pa Port Group
✓ PAOEN5 – – – ✓ PAOEN4 – – ✓ ✓ PAOEN3 ✓ ✓ ✓ ✓ PAOEN2 – ✓ ✓ ✓ PAOEN1 – ✓ ✓ ✓ PAOEN0 – – ✓ ✓ Seiko Epson Corporation 7-35 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 114 ✓ PACHATEN5 – – – ✓ PACHATEN4 – – ✓ ✓ PACHATEN3 ✓ ✓ ✓ ✓ PACHATEN2 – ✓ ✓ ✓ PACHATEN1 – ✓ ✓ ✓ PACHATEN0 – – ✓ ✓ Seiko Epson Corporation 7-36 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 115: Pd Port Group
PDIN5 – – – – ✓ PDIN4 – – ✓ ✓ PDIN3 ✓ ✓ ✓ ✓ PDIN2 ✓ ✓ ✓ ✓ PDIN1 ✓ ✓ ✓ ✓ PDIN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-37 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 116 – – OSC4 ✓ ✓ ✓ ✓ – – – – – – – – – – ✓ ✓ – – – – – – – – – – – ✓ Seiko Epson Corporation 7-38 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 117: Common Registers Between Port Groups
✓ P5INT ✓ ✓ ✓ ✓ P4INT ✓ ✓ ✓ ✓ P3INT ✓ ✓ ✓ ✓ P2INT ✓ ✓ ✓ ✓ P1INT ✓ ✓ ✓ ✓ P0INT ✓ ✓ ✓ ✓ Seiko Epson Corporation 7-39 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 118: Universal Port Multiplexer (Upmux)
4. Initialize the peripheral circuit. 5. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PPORTPxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 119: Control Registers
Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 120: Watchdog Timer (Wdt2)
CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DE- BUG mode. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 121: Operations
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 122: Operations In Halt And Sleep Modes
IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 123: Wdt2 Control Register
WDT2 should also be reset concurrently when running WDT2. WDT2 Counter Compare Match Register Register name Bit name Initial Reset Remarks WDT2CMP 15–10 – 0x00 – – 9–0 CMP[9:0] 0x3ff R/WP Bits 15–10 Reserved Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 124 These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 125: Real-Time Clock (Rtca)
If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 10-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 126: Clock Settings
· · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation 10-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 127: Operations
3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation 10-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 128: Real-Time Clock Counter Operations
The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 10.4.4.1. Seiko Epson Corporation 10-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 129: Interrupts
1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation 10-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 130: Control Registers
This bit executes the 30-second correction time adjustment function. 1 (W): Execute 30-second correction 0 (W): Ineffective 1 (R): 30-second correction is executing. 0 (R): 30-second correction has finished. (Normal operation) Seiko Epson Corporation 10-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 131: Rtca Control Register (High Byte)
1 as well. However, no correcting operation is performed. RTCA Second Alarm Register Register name Bit name Initial Reset Remarks RTCAALM1 – – – 14–12 RTCSHA[2:0] 11–8 RTCSLA[3:0] 7–0 – 0x00 – Bit 15 Reserved Seiko Epson Corporation 10-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 132: Rtca Hour/Minute Alarm Register
BCD code. RTCA Stopwatch Control Register Register name Bit name Initial Reset Remarks RTCASWCTL 15–12 BCD10[3:0] – 11–8 BCD100[3:0] 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation 10-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 133: Rtca Second/1Hz Register
10-second digit and the 1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Seiko Epson Corporation 10-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 134: Rtca Hour/Minute Register
1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCAHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 10-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 135: Rtca Month/Day Register
The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 10.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation 10-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 136: Rtca Interrupt Flag Register
The following shows the correspondence between the bit and interrupt: RTCAINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCAINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCAINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCAINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 10-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 137: Rtca Interrupt Enable Register
The following shows the correspondence between the bit and interrupt: RTCAINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCAINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCAINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCAINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation 10-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 138 RTCAINTE.T1DAYIE bit: 1-day interrupt RTCAINTE.T1HURIE bit: 1-hour interrupt RTCAINTE.T1MINIE bit: 1-minute interrupt RTCAINTE.T1SECIE bit: 1-second interrupt RTCAINTE.T1_2SECIE bit: 1/2-second interrupt RTCAINTE.T1_4SECIE bit: 1/4-second interrupt RTCAINTE.T1_8SECIE bit: 1/8-second interrupt RTCAINTE.T1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 10-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 139: Supply Voltage Detector (Svd3)
- Continuous operation is also possible. Figure 11.1.1 shows the configuration of SVD3. Table 11.1.1 SVD3 Configuration of S1C31D50/D51 Item 48-pin package 64-pin package 80-pin package...
Page 140: Input Pins And External Connection
SLEEP mode and SVD3 stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD3 is supplied and the SVD3 operation resumes. Seiko Epson Corporation 11-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 141: Clock Supply In Debug Mode
SVD3CTL.MODEN bit = 1, wait for at least SVD circuit response SVD_EXT time before reading the SVD3INTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation 11-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 142: Svd3 Operations
SVDIF bit). An interrupt request is sent to the COU core only when the SVD3INTF.SVDIF bit is set while the in- terrupt is enabled by the SVD3INTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 11-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 143: Svd3 Reset
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD3 operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD3. Seiko Epson Corporation 11-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 144: Svd3 Control Register
0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 11-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 145: Svd3 Status And Interrupt Flag Register
, EXSVDn) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT , EXSVDn) ≥ SVD detection voltage V 0 (R): Power supply voltage (V or EXSVD detection voltage V SVD_EXT Bits 7–1 Reserved Seiko Epson Corporation 11-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 146: Svd3 Interrupt Enable Register
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 147: 16-Bit Timers (T16)
• A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 12.1.1 shows the configuration of a T16 channel. Table 12.1.1 T16 Channel Configuration of S1C31D50/D51 Item 48-pin package 64-pin package...
Page 148: Clock Settings
(Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 12-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 149: Counter Underflow
At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation 12-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 150: Counter Value Read
Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 12-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 151: T16 Ch.n Control Register
PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation 12-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 152: T16 Ch.n Reload Data Register
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 12-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 153: T16 Ch.n Interrupt Enable Register
This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 12-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 154: Uart (Uart3)
• Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. • Provides the carrier modulation output function. Figure 13.1.1 shows the UART3 configuration. Table 13.1.1 UART3 Channel Configuration of S1C31D50/D51 Item 48-pin package 64-pin package...
Page 155: Input/Output Pins And External Connections
(Clock source selection) - UART3_nCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 13-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 156: Clock Supply In Sleep Mode
(UART3_nMOD.STPB bit = 1). Parity function The parity function is configured using the UART3_nMOD.PREN and UART3_nMOD.PRMD bits. Table 13.4.1 Parity Function Setting UART3_nMOD.PREN bit UART3_nMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation 13-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 157: Operations
8. Configure the DMA controller and set the following UART3 control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the UART3_nTBEDMAEN and UART3_nRB1FDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 13-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 158: Data Transmission
Read the UART3_nINTF.TBEIF bit UART3_nINTF.TBEIF = 1 ? Write transmit data to the UART3_nTXD register Transmit data remained? Wait for an interrupt request (UART3_nINTF.TBEIF = 1) Figure 13.5.2.2 Data Transmission Flowchart Seiko Epson Corporation 13-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 159: Data Reception
UART3_nINTF.RB1FIF bit to 1 (receive buffer one byte full). If the sec- ond data is received without reading the first data, the UART3_nINTF.RB2FIF bit is set to 1 (receive buffer two bytes full). Seiko Epson Corporation 13-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 160 Set the UART3_nMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation 13-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 161: Carrier Modulation
CAREN = 0 CAREN = 1 USOUTn PECAR = 0 (INVTX = 1) CAREN = 1 PECAR = 1 Figure 13.5.5.1 Carrier Modulation Waveform (UART3_nMOD.CHLN = 1, UART3_nMOD.STPB = 0, UART3_nMOD.PREN = 1) Seiko Epson Corporation 13-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 162: Receive Errors
When an overrun error occurs, the UART3_nINTF.OEIF bit (overrun error interrupt flag) is set to 1. Seiko Epson Corporation 13-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 163: Interrupts
After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 13-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 164: Control Registers
UART3 Ch.n Mode Register Register name Bit name Initial Reset Remarks UART3_nMOD 15–13 – – – PECAR CAREN BRDIV INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Bits 15–13 Reserved Seiko Epson Corporation 13-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 165 1 (R/W): Enable parity function 0 (R/W): Disable parity function Bit 1 PRMD This bit selects either odd parity or even parity when using the parity function. 1 (R/W): Odd parity 0 (R/W): Even parity Seiko Epson Corporation 13-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 166: Uart3 Ch.n Baud-Rate Register
Note: If the UART3_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the UART3_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the UART3_nCTL.SFTRST bit as well. Seiko Epson Corporation 13-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 167: Uart3 Ch.n Transmit Data Register
This bit indicates the receiving status. (See Figure 13.5.3.1.) 1 (R): During receiving 0 (R): Idle Bit 8 TBSY This bit indicates the sending status. (See Figure 13.5.2.1.) 1 (R): During sending 0 (R): Idle Bit 7 Reserved Seiko Epson Corporation 13-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 168: Uart3 Ch.n Interrupt Enable Register
UART3_nINTE.PEIE bit: Parity error interrupt UART3_nINTE.OEIE bit: Overrun error interrupt UART3_nINTE.RB2FIE bit: Receive buffer two bytes full interrupt UART3_nINTE.RB1FIE bit: Receive buffer one byte full interrupt UART3_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 169: Uart3 Ch.n Transmit Buffer Empty Dma Request Enable Register
UART3_nCAWF 15–8 – 0x00 – – 7–0 CRPER[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 CRPER[7:0] These bits set the carrier modulation output frequency. For more information, refer to “Carrier Modu- lation.” Seiko Epson Corporation 13-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 170: Synchronous Serial Interface (Spia)
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 14.1.1 shows the SPIA configuration. Table 14.1.1 SPIA Channel Configuration of S1C31D50/D51 Item 48-pin package...
Page 171: Input/Output Pins And External Connections
SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 14.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 14-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 172: Pin Functions In Master Mode And Slave Mode
16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation 14-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 173: Clock Supply During Debugging
SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPIA_nTXD register Figure 14.3.3.1 SPI Clock Phase and Polarity (SPIA_nMOD.LSBFST bit = 0, SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 174: Data Format
6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 14-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 175: Data Transmission In Master Mode
Data (W) → SPIA_nTXD Data (W) → SPIA_nTXD Software operations Data (W) → SPIA_nTXD 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.2.1 Example of Data Sending Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 176 Transfer destination SPIA_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation 14-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 177: Data Reception In Master Mode
Software operations SPIA_nRXD → Data (R) Data (W) → SPIA_nTXD SPIA_nRXD → Data (R) 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 178 Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation 14-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 179: Terminating Data Transfer In Master Mode
Writing transmit data is not a trigger to start data transfer. Therefore, it is not necessary to write dummy data to the transmit data buffer when performing data reception only. Seiko Epson Corporation 14-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 180: Terminating Data Transfer In Slave Mode
1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations. Seiko Epson Corporation 14-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 181: Interrupts
SPIA_nINTF.BSY SPIA_nMOD register CPOL bit CPHA bit SPICLKn SDOn SPICLKn SDOn SPIA_nINTF.TENDIF Writing data to the SPIA_nTXD register Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 182: Dma Transfer Requests
16 bits 15 bits 14 bits 13 bits 12 bits 11 bits 10 bits 9 bits 8 bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits Setting prohibited Seiko Epson Corporation 14-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 183: Spia Ch.n Control Register
Note: If the SPIA_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the SPIA_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the SPIA_nCTL.SFTRST bit as well. Seiko Epson Corporation 14-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 184: Spia Ch.n Transmit Data Register
These bits indicate the SPIA interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag (OEIF, TENDIF) 0 (W): Ineffective Seiko Epson Corporation 14-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 185: Spia Ch.n Interrupt Enable Register
Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 14-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 186: Quad Synchronous Serial Interface (Qspi)
• Can issue a DMA transfer request when a receive buffer full, a transmit buffer empty, or a memory mapped ac- cess (32-bit read) occurs. Figure 15.1.1 shows the QSPI configuration. Table 15.1.1 QSPI Channel Configuration of S1C31D50/D51 Item 48-pin package...
Page 187: Input/Output Pins And External Connections
In this case, GPIO pins other than #QSPISSn can also be used as the slave select output ports to connect the QSPI to more than one external QSPI device. Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI devices. Seiko Epson Corporation 15-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 188 External dual-I/O SPI slave devices QSDIOn0 SDIO0 QSPICLKn SPICK #SPISS SDIO1 SDIO0 SPICK Figure 15.2.2.3 Connections between QSPI in Register Access Master Mode and External Dual-I/O SPI Slave Devices Seiko Epson Corporation 15-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 189 #SPISS2 External single-I/O SPI master device SPICK SPICK External single-I/O SPI slave devices #SPISS SPICK Figure 15.2.2.5 Connections between QSPI in Slave Mode and External Single-I/O SPI (Legacy SPI) Master Device Seiko Epson Corporation 15-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 190 QSDIO2 QSDIO2 QSDIO1 QSDIO1 QSDIO0 QSDIO0 QSPICLK QSPICLK External QSPI slave devices #QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK Figure 15.2.2.7 Connections between QSPI in Slave Mode and External QSPI Master Device Seiko Epson Corporation 15-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 191: Pin Functions In Master Mode And Slave Mode
To supply CLK_QSPIn to the QSPI, the 16-bit timer clock source must be enabled in the clock generator. It does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the corresponding 16-bit timer channel are set (1 or 0). Seiko Epson Corporation 15-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 192: Clock Supply During Debugging
(Master mode, output) QSDIOn (Slave mode, output) QSDIOn (Slave mode, output) QSDIOn Writing data to the QSPI_nTXD register Figure 15.3.3.1 QSPI Clock Phase and Polarity (QSPI_nMOD.LSBFST bit = 0, QSPI_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 15-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 193: Data Format
Loading Dr[15:0] to the QSPI_nRXD register Figure 15.4.2 Data Format Selection for Dual Transfer Mode Using the QSPI_nMOD.LSBFST Bit (QSPI_nMOD.TMOD[1:0] bits = 0x1, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0) Seiko Epson Corporation 15-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 194: Register Access Mode
(QSPI_nCTL.DIR bit = 1). The number of data transfer clocks is configured with the QSPI_nMOD. CHLN[3:0] bits. Since four data lines are used for data transfer, the data bit length (number of clocks) is obtained by dividing the number of transfer data bits by four. Seiko Epson Corporation 15-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 195: Memory Mapped Access Mode
The QSPI treats the dummy cycle as 8 cycles with 1 driving cycle. (QSPI_nMOD.CHDL[3:0] bits = 0x0, QSPI_nMOD.CHLN[3:0] bits = 0x7) Figure 15.5.2.1 XIP Example - Spansion S25FL128S Quad I/O Read Command Sequence (3-byte address, 0xeb [ExtAdd = 0], LC = 0b00) Seiko Epson Corporation 15-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 196: Initialization
- QSPI_nMOD.MST bit (Select master/slave mode) 3. Configure the following register bits when using memory mapped access mode: - QSPI_nMMACFG1.TCSH[3:0] bits (Set slave select signal negation period) - QSPI_nRMADRH.RMADR[31:20] bits (Set remapping address) Seiko Epson Corporation 15-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 197: Data Transmission In Master Mode
If transmit data has not been written to the QSPI_nTXD register after the last clock is output from the QSPI- CLKn pin, the clock output halts and the QSPI_nINTF.TENDIF bit is set to 1. At the same time QSPI issues an end-of-transmission interrupt request if the QSPI_nINTE.TENDIE bit = 1. Seiko Epson Corporation 15-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 198 DMA transfer in advance so that transmit data will be transferred to the QSPI_nTXD register. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 199: Data Reception In Register Access Master Mode
TMOD[1:0] bits is received when the QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is overwritten with the newly received data and the previously received data is lost. In this case, the QSPI_nINTF.OEIF bit is set. Seiko Epson Corporation 15-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 200 DMA controller and dummy data is transferred from the specified memory to the QSPI_ nTXD register via DMA Ch.x when the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty). Seiko Epson Corporation 15-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 201 DMA controller transfers data from the QSPI_nRXD register and then writes another dummy byte to the QSPI_nTXD register, allowing the QSPI to read the next data. 13. Wait for a DMA interrupt. Seiko Epson Corporation 15-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 202: Data Reception In Memory Mapped Access Mode
If the address in the memory mapped access area that is continuous to the previous read address is read when the FIFO contains the prefetched data (FIFO data ready status), the prefetched data is sent to the internal system bus with the HREADY signal held high (zero-wait read). Seiko Epson Corporation 15-17 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 203 Data cycle 3 QSPI_nMOD register Dummy cycle Data cycle 1 (prefetching) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read Seiko Epson Corporation 15-18 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 204 HRDATA fifo_read_level Data cycle Data cycle QSPI_nMOD register (for n+8) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read Seiko Epson Corporation 15-19 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 205 Dummy cycle (low-order 16 bits) (for n) (for n+8) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.3 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Non-Sequential Read Seiko Epson Corporation 15-20 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 206 HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Dummy cycle Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read Seiko Epson Corporation 15-21 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 207 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read Seiko Epson Corporation 15-22 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 208 Address cycle Dummy cycle Data cycle (low-order 16 bits) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential Read Seiko Epson Corporation 15-23 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 209 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-24 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 210: Terminating Memory Mapped Access Operations
1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). 2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations. 3. Stop the 16-bit timer to disable the clock supply to QSPI Ch.n. Seiko Epson Corporation 15-25 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 211: Data Transfer In Slave Mode
Data (W) → QSPI_nTXD Software operations QSPI_nRXD → Data (R) QSPI_nRXD → Data (R) Figure 15.5.9.1 Example of Data Transfer Operations in Slave Mode (QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3) Seiko Epson Corporation 15-26 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 212: Terminating Data Transfer In Slave Mode
The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating status in register access and memory mapped access modes, respectively. Figure 15.6.1 shows the QSPI_nINTF.BSY, QSPI_ nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings. Seiko Epson Corporation 15-27 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 213: Dma Transfer Requests
When a 32-bit data is prefetched into the FIFO When the FIFO read access FIFO data FIFO data ready flag in memory mapped access mode level is cleared to 0 ready (internal signal) Seiko Epson Corporation 15-28 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 214: Control Registers
Note: When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the same value as the QSPI_nMOD.CHLN[3:0] bits. Bits 11–8 CHLN[3:0] These bits set the number of clocks for data transfer. Seiko Epson Corporation 15-29 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 215 0 (R/W): MSB first Bit 2 CPHA Bit 1 CPOL These bits set the QSPI clock phase and polarity. For more information, refer to “QSPI Clock (QSPI- CLKn) Phase and Polarity.” Seiko Epson Corporation 15-30 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 216: Qspi Ch.n Control Register
Note: If the QSPI_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the QSPI_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the QSPI_nCTL.SFTRST bit as well. Seiko Epson Corporation 15-31 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 217: Qspi Ch.n Transmit Data Register
Transmit/receive busy 0 (R): Idle Bit 6 MMABSY This bit indicates the QSPI memory mapped access operating status. 1 (R): Memory mapped access state machine busy 0 (R): Idle Bits 5–4 Reserved Seiko Epson Corporation 15-32 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 218: Qspi Ch.n Interrupt Enable Register
Ch.15) when a transmit buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 15-33 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 219: Qspi Ch.n Receive Buffer Full Dma Request Enable Register
11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock Note: These bits specify a number of system clocks. Seiko Epson Corporation 15-34 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 220: Qspi Ch.n Remapping Start Address High Register
Flash memory in the memory mapped access mode. This setting is re- quired to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories. Seiko Epson Corporation 15-35 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 221 The QSDIOn[3:0] pins are used. Dual transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Single transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Seiko Epson Corporation 15-36 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 222: Qspi Ch.n Mode Byte Register
Note: In memory mapped access mode, the mode byte is always output from the LSB first. When us- ing a Flash memory that expects the mode byte to be output from the MSB first, write the mode byte to this register in reverse bit order. Seiko Epson Corporation 15-37 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 223: C (I2C)
• Can generate receive buffer full, transmit buffer empty, and other interrupts. • Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs. Figure 16.1.1 shows the I2C configuration. Table 16.1.1 I2C Channel Configuration of S1C31D50/D51 Item 48-pin package...
Page 224: Input/Output Pins And External Connections
• The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 16-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 225: Clock Settings
16.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation 16-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 226: Operations
- Set the I2C_nCTL.MST bit to 0. (Set slave mode) - Set the I2C_nCTL.SFTRST bit to 1. (Execute software reset) - Set the I2C_nCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 16-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 227: Data Transmission In Master Mode
I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condi- tion. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and I2C_nINTF. TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation 16-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 228 Last data sent? Retry? Write 1 to the I2C_nCTL.TXSTOP bit Write data to the I2C_nTXD register Wait for an interrupt request (I2C_nINTF.STOPIF = 1) Figure 16.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 16-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 229: Data Reception In Master Mode
9. (When DMA is not used) Repeat Steps 5 to 7 until the end of data reception. 10. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1). Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred. Seiko Epson Corporation 16-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 230 S: START condition, Sr: Repeated START condition, P: STOP condition, A: ACK, A: NACK, Saddr/R: Slave address + R(1), Data n: 8-bit data Figure 16.4.3.1 Example of Data Receiving Operations in Master Mode Seiko Epson Corporation 16-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 231 Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 (+1) dst_size 0x0 (byte) src_inc 0x3 (no increment) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of receive data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation 16-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 232: 10-Bit Addressing In Master Mode
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data transfer di- rection to the I2C_nTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 16-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 233: Data Transmission In Slave Mode
Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2C_nINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 16-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 234 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 16.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 16-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 235: Data Reception In Slave Mode
I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2C_nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1. After that, the received data can be read out from the I2C_nRXD register. Seiko Epson Corporation 16-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 236 Wait for an interrupt request (I2C_nINTF.RBFIF = 1) Last data received next? Write 1 to the I2C_nCTL.TXNACK bit Read receive data from the I2C_nRXD register Last data received? Figure 16.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 16-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 237: Slave Operations In 10-Bit Address Mode
If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1. Seiko Epson Corporation 16-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 238: Error Detection
4 When 1 is written to the I2C_nCTL. I2C_nINTF.ERRIF = 1 TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to “Au- Automatic bus clearing I2C_nCTL.TXSTART = 0 tomatic Bus Clearing Operation.”) failure I2C_nINTF.STARTIF = 1 Seiko Epson Corporation 16-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 239: Interrupts
Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2C_nOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation 16-17 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 240: Dma Transfer Requests
16.7 Control Registers I2C Ch.n Clock Control Register Register name Bit name Initial Reset Remarks I2C_nCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 16-18 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 241: I2C Ch.n Mode Register
Note: The I2C_nMOD register settings can be altered only when the I2C_nCTL.MODEN bit = 0. I2C Ch.n Baud-Rate Register Register name Bit name Initial Reset Remarks I2C_nBR 15–8 – 0x00 – – – – 6–0 BRT[6:0] 0x7f Bits 15–7 Reserved Seiko Epson Corporation 16-19 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 242: I2C Ch.n Own Address Register
STOP condition has been generated. This bit is automatically cleared when the bus free time (t defined in the I C Specifications) has elapsed after the STOP condition has been generated. Seiko Epson Corporation 16-20 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 243: I2C Ch.n Transmit Data Register
Register name Bit name Initial Reset Remarks I2C_nRXD 15–8 – 0x00 – – 7–0 RXD[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. Seiko Epson Corporation 16-21 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 244: I2C Ch.n Status And Interrupt Flag Register
Bit 0 TBEIF These bits indicate the I2C interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 16-22 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 245: I2C Ch.n Interrupt Enable Register
I2C_nINTE.NACKIE bit: NACK reception interrupt I2C_nINTE.STOPIE bit: STOP condition interrupt I2C_nINTE.STARTIE bit: START condition interrupt I2C_nINTE.ERRIE bit: Error detection interrupt I2C_nINTE.RBFIE bit: Receive buffer full interrupt I2C_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 16-23 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 246: I2C Ch.n Transmit Buffer Empty Dma Request Enable Register
(Ch.0–Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 16-24 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 247: 16-Bit Pwm Timers (T16B)
- The capture circuit captures counter values using external/software trigger signals and generates interrupts or DMA requests. (Can be used to measure external event periods/cycles.) Figure 17.1.1 shows the T16B configuration. Table 17.1.1 T16B Channel Configuration of S1C31D50/D51 Item 48-pin package...
Page 248: Input/Output Pins
If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 17-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 249: Clock Settings
Figure 17.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation 17-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 250: Operations
5. Set the following bits when using the interrupt: - Write 1 to the interrupt flags in the T16B_nINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the T16B_nINTE register to 1. (Enable interrupts) Seiko Epson Corporation 17-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 251: Counter Block Operations
T16Bn, one of the operations shown below is required to read correctly by the CPU. - Read the counter value twice or more and check to see if the same value is read. - Stop the timer and then read the counter value. Seiko Epson Corporation 17-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 252 0x0000 and continues counting down from the new MAX value after a counter under- flow occurs. In one-shot down count mode, the counter returns to the MAX value if a counter underflow occurs and stops automatically at that point. Seiko Epson Corporation 17-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 253 0x0000 and then starts counting up to the new MAX value. In one-shot up/down count mode, the counter stops automatically when it reaches 0x0000 during count down operation. Seiko Epson Corporation 17-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 254: Comparator/Capture Block Operations
When the counter reaches the MAX value in comparator mode, the T16B_nINTF.CNTMAXIF bit (counter MAX interrupt flag) is set to 1. When the counter reaches 0x0000, the T16B_nINTF.CNTZEROIF bit (counter zero interrupt flag) is set to 1. Seiko Epson Corporation 17-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 255 Count cycle = —————— [s] (Eq. 17.2) CLK_T16B CLK_T16B Where T16B_nCCRm register setting value (0 to 65,535) MAX: T16B_nMC register setting value (0 to 65,535) : Count clock frequency [Hz] CLK_T16B Seiko Epson Corporation 17-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 256 (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 257 Count cycle MAX value (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 258 Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 259 Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 260 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 (Note that the T16B_nINTF.CMPCAPmIF/CNTMAXIF/CNTZEROIF bit clearing operations via software are omitted from the figure.) Figure 17.4.3.2 Compare Buffer Operations Seiko Epson Corporation 17-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 261 If the captured data stored in the T16B_nCCRm register is overwritten by the next trigger when the T16B_ nINTF.CMPCAPmIF bit is still set, an overwrite error occurs (the T16B_nINTF.CAPOWmIF bit is set). Seiko Epson Corporation 17-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 262 Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16B_nTC.TC[15:0] Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation Figure 17.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation 17-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 263: Tout Output Control
Furthermore, when the T16B_nCCCTLm.TOUTMT bit is set to 1, the TOUT circuit uses the MATCH signal output from another system in the circuit pair (0 and 1, 2 and 3, 4 and 5). This makes it possible to change the signal twice within a counter cycle. Seiko Epson Corporation 17-17 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 264 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-18 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 265 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.2 TOUT Output Waveform (T16B_nCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation 17-19 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 266 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-20 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 267 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-21 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 268 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.3 TOUT Output Waveform (T16B_nCCCTL0.TOUTMT bit = 1, T16B_nCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation 17-22 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 269: Interrupt
Bit 8 DBRUN This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Seiko Epson Corporation 17-23 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 270: T16B Ch.n Counter Control Register
T16B_nCTL.ONEST bit setting (see Table 17.7.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16B_nCTL.CNTMD[1:0] bit settings (see Table 17.7.2). Seiko Epson Corporation 17-24 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 271: T16B Ch.n Max Counter Data Register
T16B_nCTL.MODEN bit to 1 until the T16B_nCS.BSY bit is set to 0 from 1. • Do not set the T16B_nMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16B_nTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 17-25 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 272: T16B Ch.n Counter Status Register
This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 17-26 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 273: T16B Ch.n Interrupt Flag Register
Note: The configuration of the T16B_nINTF.CAPOWmIF and T16B_nINTF.CMPCAPmIF bits de- pends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 17-27 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 274: T16B Ch.n Interrupt Enable Register
The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 17-28 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 275: T16B Ch.n Comparator/Capture M Control Register
These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16B_nCCRm register in capture mode (see Table 17.7.4). The T16B_nCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 17-29 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 276 T h e s i g n a l b e c o m e s i n a c t i v e b y t h e M AT C H m o r MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 17-30 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 277: T16B Ch.n Compare/Capture M Data Register
In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 17-31 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 278: T16B Ch.n Counter Max/Zero Dma Request Enable Register
(Ch.0–Ch.15) when the counter value reaches the compare data or is captured. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 17-32 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 279: Ir Remote Controller (Remc3)
• Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 18.1.1 shows the REMC3 configuration. Table 18.1.1 REMC3 Channel Configuration of S1C31D50/D51 Item 48-pin package 64-pin package...
Page 280: External Connections
1. Write 1 to the REMC3DBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMC3CLK.CLKSRC[1:0] and REMC3CLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 18-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 281: Data Transmission Procedures
The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 18.4.3.1 shows an example of the output waveform. Seiko Epson Corporation 18-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 282 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REMC3DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMC3A- PLEN.APLEN[15:0] and REMC3DBLEN.DBLEN[15:0] bits. Figure 18.4.3.3 shows an example of the data signal generated. Seiko Epson Corporation 18-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 283: Continuous Data Transmission And Compare Buffers
(REMC3DBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMC3DBLEN.DBLEN[15:0] bit-setting value. 18.4.4 Continuous Data Transmission and Compare Buffers Figure 18.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation 18-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 284: Interrupts
CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 18-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 285: Application Example: Driving El Lamp
This bit sets whether the REMC3 operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation 18-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 286: Remc3 Data Bit Counter Control Register
This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 18-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 287: Remc3 Data Bit Counter Register
0x0000 H0/S0 Cleared by writing 1 to the REMC3DBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation 18-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 288: Remc3 Data Bit Active Pulse Length Register
Transfer to the REMC3APLEN buffer has not completed. 0 (R): Transfer to the REMC3APLEN buffer has completed. While this bit is set to 1, writing to the REMC3APLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 18-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 289: Remc3 Interrupt Enable Register
REMC3CARR.CRPER[7:0] bit-setting value. (See Figure 18.4.3.2.) REMC3 Carrier Modulation Control Register Register name Bit name Initial Reset Remarks REMC3CCTL 15–9 – 0x00 – – OUTINVEN 7–1 – 0x00 – CARREN Seiko Epson Corporation 18-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 290 This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMC3DBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 18-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 291: 12-Bit A/D Converter (Adc12A)
• Can convert multiple analog input signals sequentially. • Can generate conversion completion and overwrite error interrupts. • Can issue a DMA transfer request when a conversion has completed. Figure 19.1.1 shows the ADC12A configuration. Table 19.1.1 ADC12A Configuration of S1C31D50/D51 Item 48-pin package 64-pin package...
Page 292: Input Pins And External Connections
: acquisition time). Figure 19.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 19.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 19-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 293: Operations
Writing 1 to the ADC12A_nCTL.ADST bit enables the ADC12A to accept trigger inputs. After that, A/D con- version is started when an underflow occurs in the 16-bit timer Ch.k. Software trigger Writing 1 to the ADC12A_nCTL.ADST bit starts A/D conversion. Seiko Epson Corporation 19-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 294: Conversion Mode And Analog Input Pin Settings
3. Read the A/D conversion result of the analog input m (ADC12A_nADD.ADD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12A_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 19-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 295 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 19-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 296: Interrupts
After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 19-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 297: Control Registers
Note: The data written to the ADC12A_nCTL.ADST bit must be retained for one or more CLK_T16_ k clock cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written. Seiko Epson Corporation 19-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 298: Adc12A Ch.n Trigger/Analog Input Select Register
Right justified (ADC12A_nTRG.STMD bit = 0) 0 (MSB) 12-bit conversion result (LSB) Figure 19.7.1 Conversion Data Alignment Bit 6 CNVMD This bit sets the A/D conversion mode. 1 (R/W): Continuous conversion mode 0 (R/W): One-time conversion mode Seiko Epson Corporation 19-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 299: Adc12A Ch.n Configuration Register
A/D conversion. • Be aware that ADC circuit current I flows if the ADC12_nCFG.VRANGE[1:0] bits are set to a value other than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1. Seiko Epson Corporation 19-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 300: Adc12A Ch.n Interrupt Flag Register
0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: ADC12A_nINTE.OVIE bit: A/D conversion result overwrite error interrupt ADC12A_nINTE.ADmCIE bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation 19-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 301: Adc12A Ch.n Dma Request Enable Register M
ADC12A Ch.n Result Register Register name Bit name Initial Reset Remarks ADC12A_nADD 15–0 ADD[15:0] 0x0000 – Bits 15–0 ADD[15:0] The A/D conversion results are set to these bits. Seiko Epson Corporation 19-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 302: F Converter (Rfc)
• Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 20.1.1 shows the RFC configuration. Table 20.1.1 RFC Channel Configuration of S1C31D50/D51 Item 48-pin package 64-pin package...
Page 303: Input/Output Pins And External Connections
Figure 20.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C31 RFC : Reference capacitor Figure 20.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 20-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 304: Clock Settings
(Clear interrupt flags) - Set the interrupt enable bits in the RFC_nINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 20-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 305: Operating Modes
To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 20-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 306: Converting Operations And Control Procedure
The measurement counter overflow sets the RFC_nINTF.EREFIF bit to 1 indicating that the reference os- cillation has been terminated normally. If the RFC_nINTE.EREFIE bit = 1, a reference oscillation comple- tion interrupt request occurs at this point. Seiko Epson Corporation 20-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 307 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 20.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 20-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 308: Cr Oscillation Frequency Monitoring Function
The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 20-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 309: Control Registers
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 20-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 310: Rfc Ch.n Oscillation Trigger Register
This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation 20-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 311: Rfc Ch.n Measurement Counter Low And High Registers
Note: The time base counter must be set from the low-order value (RFC_nTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFC_nTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 20-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 312: Rfc Ch.n Interrupt Flag Register
RFC_nINTE.OVTCIE bit: Time base counter overflow error interrupt RFC_nINTE.OVMCIE bit: Measurement counter overflow error interrupt RFC_nINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFC_nINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFC_nINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation 20-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 313: Hw Processor (Hwp) And Sound Output
HWP is a functional block having the “Sound Play” and “Memory Check” functions. It can work without any CPU resources by only issuing a command. HWP uses SDAC (S1C31D50/D51) or T16B Ch.0 (S1C31D51) for sound output. SDAC is a DAC that converts the sound data generated by the HWP into PWM signals and outputs them to the external audio amplifier.
Page 314 MCU peripheral circuit area, other names represent a HWP internal register. • For the specifications of sound data and the setting of the external Flash memory for storing sound data, refer to the application note or the sample software manual. Seiko Epson Corporation 21-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 315: Output Pins And External Connections
21 HW Processor (HWP) and Sound Output 21.2 Output Pins and External Connections 21.2.1 List of Output Pins Table 21.2.1.1 lists the S1C31D50/D51 SDAC output pins. Table 21.2.1.1 S1C31D50/D51 SDAC Output Pins Pin name Initial status Function SDACOUT_P O (L)
Page 316: Clock Settings
- SYSCLK source = OSC3 - OSC3 oscillation frequency = 16 MHz 2. Set the following SDACCLK register bits (set in S1C31D50/D51 regardless of the sound output destination): - Set the SDACCLK.CLKSRC[1:0] bits to 0x02. (Clock source = OSC3) - Set the SDACCLK.CLKDIV[1:0] bits to 0x0.
Page 317 - Set the SDACINTE register to 0x0000. (Disable interrupts) - Write 0x0003 to the SDACINTF register. (Clear interrupt flag) Initializing T16B Ch.0 6. Assign the T16B Ch.0 TOUT outputs to the ports (UPMAX) used for sound output. Seiko Epson Corporation 21-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 318 (sp_state_idle = sound play function idle state). Initialize the SDAC, T16B Ch.0, and HWP in this order again if the HWPINTF.HWP1IF bit = 1. Sound play state transition Figure 21.4.1.1 shows the sound play state transition diagram. Seiko Epson Corporation 21-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 319 The current Ch.n operating state can be monitored by reading the STATE_n.STATE[15:0] bits (except hwp_ sleep). Furthermore, an interrupt can be generated when a state transition to the designated state occurs. Seiko Epson Corporation 21-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 320 (Occurrence of state transition) 9. Confirm that the STATE_n.STATE[15:0] bits = 0x0001 (sp_state_idle) as necessary. When the sound data ends, playback output is automatically terminated and the sound play function transits to sp_state_idle state. Seiko Epson Corporation 21-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 321 18. Wait until the HWPINTF.HWP0IF bit is set to 1 (interrupt). (Occurrence of state transition) 19. Confirm that the STATE_1.STATE[15:0] bits = 0x0001 (sp_state_idle) as necessary. 20. Write 0 to the HWPINTF.HWP0IF bit. (Clear interrupt flag) Seiko Epson Corporation 21-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 322 From this point, the volume returns to the level it was before being muted. 6. Confirm that the STATE_n.STATE[15:0] bits = 0x0002 (sp_state_play) as necessary. 7. Write 0 to the HWPINTF.HWP0IF bit. (Clear interrupt flag) Seiko Epson Corporation 21-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 323 (Occurrence of state transition) The HWP resumes playback output from this point. 6. Confirm that the STATE_n.STATE[15:0] bits = 0x0002 (sp_state_play) as necessary. 7. Write 0 to the HWPINTF.HWP0IF bit. (Clear interrupt flag) Seiko Epson Corporation 21-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 324 Another error has occurred. When a non-fatal error has occurred, reissue a valid command. When a fatal error has occurred, remove the cause of error and redo the processing from initialization. Seiko Epson Corporation 21-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 325: Memory Check Function
_ram_rw _ram_march_c _checksum _crc Figure 21.4.2.1 Memory check State Transition Diagram As shown in the figure above, there are seven operating states in the memory check function. Seiko Epson Corporation 21-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 326 2. Confirm that the STATUS.READY bit = 1. (Command acceptable) 3. Set the COMMAND.COMMAND[7:0] bits. (Select command) 4. Set the MEMADDR.ADDRESS[31:0] bits. (Specify check start address) 5. Set the MEMSIZE.SIZE[31:0] bits. (Specify check size (byte)) Seiko Epson Corporation 21-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 327 When this command is issued by the trigger bit, the HWP transits to mc_state_ram_march_c state to ex- ecute the RAM marching test (March-C algorithm). Note: When an error occurs during RAM check, the check is terminated at the address where the error has occurred. Seiko Epson Corporation 21-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 328 Note: The HWP uses memory mapped access mode (refer to the “Quad Synchronous Serial Interface” chapter) for the external QSPI-Flash check. Therefore, external Flash memories that do not sup- port XIP (eXecute-In-Place) cannot be checked. Seiko Epson Corporation 21-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 329: Interrupts
INTMASK.TO_IDLE sp_state_init, mute, pause, play state → sp_state_idle state Memory check INTMASK.TO_PROCESSING mc_state_idle state → mc_state_ram_rw, ram_march_c, checksum, crc state INTMASK.TO_IDLE mc_state_init, mc_state_ram_rw, ram_march_c, checksum, crc state → mc_state_ idle state Seiko Epson Corporation 21-17 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 330: Hwp Internal Registers
Sound play function using SDAC Other Setting prohibited (error) Interrupt Mask Register Register name Bit name Initial Reset Remarks INTMASK 15–8 – 0x00 – – (Sound Play) 7–4 – – TO_MUTE TO_PAUSE TO_PLAY TO_IDLE Seiko Epson Corporation 21-18 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 331: Rom Address Register
0x03 0000 bytes (192K bytes) or less In case of external QSPI-Flash: 0x100 0000 bytes (16M bytes) or less Key Code Register Register name Bit name Initial Reset Remarks KEYCODE 31–0 KEYCODE[31:0] 0x0000 – (Sound Play) 0000 Seiko Epson Corporation 21-19 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 332: N Command Register
21 HW Processor (HWP) and Sound Output Bits 31–0 KEYCODE[31:0] These bits specify the key code. Write the key code provided by Seiko Epson. Ch.n Command Register Register name Bit name Initial Reset Remarks COMMAND_n 15–8 OPTION[7:0] 0x00 – (Sound Play) 7–0 COMMAND[7:0]...
Page 333: N Repeat Control Register
SPEED_0.SPEED[15:0] bits Playback speed 0x7d 125% Fast 0x78 120% ↑ 0x73 115% 0x6e 110% 0x69 105% 0x64 100% Normal playback speed 0x5f 0x5a 0x55 0x50 ↓ 0x4b Slow Other Setting prohibited Seiko Epson Corporation 21-21 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 334: N State Monitor Register
Register name Bit name Initial Reset Remarks VERSION 15–8 MAJOR[7:0] – 7–0 MINOR[7:0] Bits 15–8 MAJOR[7:0] Bits 7–0 MINOR[7:0] These bits indicate the HWP version number. Version number = MAJOR[7:0] . MINOR[7:0] Seiko Epson Corporation 21-22 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 335: Memory Check Function Register
0x00 0000 + OFFSET, …, 0x0f ffff + OFFSET * The OFFSET is 0x04 0000, the start address of the memory mapped access area for external Flash memory (refer to “Figure 4.1.1 Memory Map”). Seiko Epson Corporation 21-23 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 336: Memory Size Register
Bits 15–0 STATE[15:0] These bits indicate the current state of the memory check function. Table 21.6.10 State Monitor STATE.STATE[15:0] bits State 0x0005 mc_state_crc 0x0004 mc_state_checksum 0x0003 mc_state_ram_march_c 0x0002 mc_state_ram_rw 0x0001 mc_state_idle 0x0000 mc_state_init Seiko Epson Corporation 21-24 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 337: Error Status Register
Register name Bit name Initial Reset Remarks VERSION 15–8 MAJOR[7:0] – 7–0 MINOR[7:0] Bits 15–8 MAJOR[7:0] Bits 7–0 MINOR[7:0] These bits indicate the HWP version number. Version number = MAJOR[7:0] . MINOR[7:0] Seiko Epson Corporation 21-25 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 338: Control Registers
1 (R/W): Enable interrupts 0 (R/W): Disable interrupts HWP Command Trigger Register Register name Bit name Initial Reset Remarks HWPCMDTRG 15–8 – 0x00 – – 7–1 – 0x00 – HWP0TRG Bits 15–1 Reserved Seiko Epson Corporation 21-26 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 339: Sdac Clock Control Register
Bits 15–1 Reserved Bit 0 SDACEN This bit enables the SDAC operations. 1 (R/W): Enable SDAC operations (The operating clock is supplied.) 0 (R/W): Disable SDAC operations (The operating clock is stopped.) Seiko Epson Corporation 21-27 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 340: Sdac Mode Register
SDACINTF.DATREQIF bit: Data request interrupt Note: This register is used by the HWP. Do not write any data to this register while the HWP operation is enabled (HWPCTL.HWPEN bit = 1). Seiko Epson Corporation 21-28 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 341: Sdac Interrupt Enable Register
SDACINTE.DATREQIE bit: Data request interrupt Note: This register is used by the HWP. Do not write any data to this register while the HWP operation is enabled (HWPCTL.HWPEN bit = 1). Seiko Epson Corporation 21-29 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 342 *1 The component values should be determined after performing matching evaluation of the resonator mounted on the printed circuit board actually used. *2 R are not required when using the debug pins as general-purpose I/O ports. DBG1–2 Seiko Epson Corporation 22-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 343: Current Consumption
*3 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 0, CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1. OSDEN bit = 0, C = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), = 7 pF) *4 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 1...
Page 344 Ta [°C] Ta [°C] Current consumption-temperature characteristic in HALT mode (OSC3 operation) IOSC =OFF, OSC1 = 32.768 kHz, OSC3 = ON, Typ. value 16 MHz 8 MHz 4 MHz Ta [°C] Seiko Epson Corporation 22-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 345: System Reset Controller (Src) Characteristics
Low level Schmitt input threshold voltage 0.2 × V – 0.5 × V Schmitt input hysteresis voltage – – Input pull-up resistance Pin capacitance – – Reset Low pulse width – – µs #RESET Seiko Epson Corporation 22-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 346: Clock Generator (Clg) Characteristics
PWGACTL.REGSEL bit = 1 CLGIOSC.IOSCFQ[1:0] bits = 0x0, 1.05 PWGACTL.REGSEL bit = 1 CLGIOSC.IOSCFQ[1:0] bits = 0x1, 1.62 1.89 PWGACTL.REGSEL bit = 0 CLGIOSC.IOSCFQ[1:0] bits = 0x0, 0.78 1.02 PWGACTL.REGSEL bit = 0 Seiko Epson Corporation 22-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 347 Internal oscillator CLGOSC1.OSC1SELCR bit = 1 31.04 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) Seiko Epson Corporation 22-6 S1C31D50/D51 TECHNICAL MANUAL...
Page 348 0.8 × V Low level Schmitt input threshold voltage 0.2 × V – 0.5 × V Schmitt input hysteresis voltage – – = 1/f = 1/f EXOSC EXOSC EXOSC EXOSC EXOSCH EXOSCH EXOSC Seiko Epson Corporation 22-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 349: Flash Memory Characteristics
Low level output current = 0.1 × V – – Leakage current -150 – LEAK Input pull-up resistance Input pull-down resistance Pin capacitance – – High level Low level Input voltage [V] Seiko Epson Corporation 22-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 350: Supply Voltage Detector (Svd3) Characteristics
4.61 SVD3CTL.SVDC[4:0] bits = 0x1b 4.49 4.72 SVD3CTL.SVDC[4:0] bits = 0x1c 4.58 4.82 SVD3CTL.SVDC[4:0] bits = 0x1d 4.68 4.92 SVD3CTL.SVDC[4:0] bits = 0x1e 4.78 5.02 SVD3CTL.SVDC[4:0] bits = 0x1f 4.88 5.13 Seiko Epson Corporation 22-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 351 *1 If CLK_SVD3 is configured in the neighborhood of 32 kHz, the SVD3INTF.SVDDT bit is masked during the t period and it SVDEN retains the previous value. CLK_SVD3 SVD3CTL.MODEN 0x1e 0x10 SVD3CTL.SVDC[4:0] SVD3INTF.SVDDT Invalid Valid Invalid Valid SVDEN Seiko Epson Corporation 22-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 352: Uart (Uart3) Characteristics
1.8 to 3.6 V mode1 – – SDO0 output delay time = 15 pF 1.8 to 5.5 V mode0 – – 1.8 to 3.6 V mode1 – – *1 C = Pin load Seiko Epson Corporation 22-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 353 (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation 22-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 354: Quad Synchronous Serial Interface (Qspi) Characteristics
– – STOP condition setup time t – – – – µs SU:STO Bus free time – – – – µs * After this period, the first clock pulse is generated. Seiko Epson Corporation 22-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 355 , ADIN = V /2, f = 100 ksps, Ta = 25°C, Typ. value REFA REFA 1,100 ADC12A_nCFG.VRANGE[1:0] bits = 1,000 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 REFA Seiko Epson Corporation 22-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 356: R/F Converter (Rfc) Characteristics
= 100 kW, Ta = 25 °C, Typ. value 1,000 1,000 3.6 V 3.6 V 1.8 V 1.8 V ∆f /∆IC ∆f /∆IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation 22-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 357 = 1,000 pF, Typ. value = 1,000 pF, Ta = 25 °C, Typ. value 1,800 = 3.6 V 1,600 1.8 V 1,400 1,200 1,000 = 3.6 V 1.8 V 1,000 10,000 Ta [°C] [kHz] RFCLK Seiko Epson Corporation 22-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 358: Basic External Connection Diagram
*2: For Flash programming (when V is generated internally) *3: When OSC1 crystal oscillator is selected *4: When OSC3 crystal/ceramic oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation 23-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 359 *4: When OSC3 crystal/ceramic oscillator is selected *5: When SDAC is used for sound output *6: When T16B Ch.0 is used for sound output ( ): Do not mount components if unnecessary. Seiko Epson Corporation 23-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 360 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
Page 361: Package
24 PACKAGE 24 Package TQFP12-48PIN (P-TQFP048-0707-0.50) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.7 Figure 24.1 TQFP12-48PIN Package Dimensions Seiko Epson Corporation 24-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 362 24 PACKAGE QFP13-64PIN (P-LQFP064-1010-0.50) INDEX 0.13 /0.27 0.09 /0.2 0° /10° /0.75 Figure 24.2 QFP13-64PIN Package Dimensions Seiko Epson Corporation 24-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 363 24 PACKAGE TQFP14-80PIN (P-TQFP080-1212-0.50) INDEX 0.17 /0.27 0.09 /0.2 0° /8° /0.75 Figure 24.3 TQFP14-80PIN Package Dimensions Seiko Epson Corporation 24-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 364 24 PACKAGE QFP15-100PIN (P-LQFP100-1414-0.50) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.75 Figure 24.4 QFP15-100PIN Package Dimensions Seiko Epson Corporation 24-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 365: Appendix A List Of Peripheral Circuit Control Registers
– – – 0046 (CLG OSC1 Control OSDRB R/WP Register) OSDEN R/WP OSC1BUP R/WP OSC1SELCR R/WP 10–8 CGI1[2:0] R/WP 7–6 INV1B[1:0] R/WP 5–4 INV1N[1:0] R/WP 3–2 – – 1–0 OSC1WT[1:0] R/WP Seiko Epson Corporation AP-A-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 366: Cache Controller (Cache)
– 1–0 CLKSRC[1:0] R/WP 0x0020 WDT2CTL 15–11 – 0x00 – – 00a2 (WDT2 Control 10–9 MOD[1:0] R/WP Register) STATNMI 7–5 – – WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – Seiko Epson Corporation AP-A-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 367: 0X0020 00C0-0X0020 00D2 Real-Time Clock (Rtca)
RTCACTLL.RTCRST bit to 1. RTC2HZ RTC4HZ RTC8HZ RTC16HZ RTC32HZ RTC64HZ RTC128HZ 0x0020 RTCAHUR – – – 00ca (RTCA Hour/Minute RTCAP Register) 13–12 RTCHH[1:0] 11–8 RTCHL[3:0] – – 6–4 RTCMIH[2:0] 3–0 RTCMIL[3:0] Seiko Epson Corporation AP-A-3 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 368 (SVD3 Control 14–13 SVDSC[1:0] R/WP Writing takes effect when the Register) SVD3CTL.SVDMD[1:0] bits are not 0x0. 12–8 SVDC[4:0] 0x1e R/WP – 7–4 SVDRE[3:0] R/WP EXSEL R/WP 2–1 SVDMD[1:0] R/WP MODEN R/WP Seiko Epson Corporation AP-A-4 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 369: 0X0020 0160-0X0020 016C 16-Bit Timer (T16) Ch.0
Flash Controller (FLASHC) Address Register name Bit name Initial Reset Remarks 0x0020 FLASHCWAIT 15–9 – 0x00 – – 01b0 (FLASHC Flash Read (reserved) R/WP Cycle Register) 7–2 – 0x00 – 1–0 RDWAIT[1:0] R/WP Seiko Epson Corporation AP-A-5 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 370 ✓ ✓ P0REN5 ✓ ✓ ✓ ✓ P0REN4 ✓ ✓ ✓ ✓ P0REN3 ✓ ✓ ✓ ✓ P0REN2 – – – ✓ P0REN1 – – – ✓ P0REN0 – – – ✓ Seiko Epson Corporation AP-A-6 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 371 ✓ ✓ 9–8 P04MUX[1:0] ✓ ✓ ✓ ✓ 7–6 P03MUX[1:0] ✓ ✓ ✓ ✓ 5–4 P02MUX[1:0] – – – ✓ 3–2 P01MUX[1:0] – – – ✓ 1–0 P00MUX[1:0] – – – ✓ Seiko Epson Corporation AP-A-7 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 372 ✓ ✓ P1IF5 ✓ ✓ ✓ ✓ P1IF4 ✓ ✓ ✓ ✓ P1IF3 ✓ ✓ ✓ ✓ P1IF2 – ✓ ✓ ✓ P1IF1 – ✓ ✓ ✓ P1IF0 – – ✓ ✓ Seiko Epson Corporation AP-A-8 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 373 ✓ ✓ P2IN5 – ✓ ✓ ✓ P2IN4 – ✓ ✓ ✓ P2IN3 ✓ ✓ ✓ ✓ P2IN2 ✓ ✓ ✓ ✓ P2IN1 ✓ ✓ ✓ ✓ P2IN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-9 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 374 ✓ ✓ P2IE5 – ✓ ✓ ✓ P2IE4 – ✓ ✓ ✓ P2IE3 ✓ ✓ ✓ ✓ P2IE2 ✓ ✓ ✓ ✓ P2IE1 ✓ ✓ ✓ ✓ P2IE0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-10 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 375 ✓ P3OEN5 – – ✓ ✓ P3OEN4 – ✓ ✓ ✓ P3OEN3 – ✓ ✓ ✓ P3OEN2 ✓ ✓ ✓ ✓ P3OEN1 ✓ ✓ ✓ ✓ P3OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-11 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 376 ✓ P3CHATEN5 – – ✓ ✓ P3CHATEN4 – ✓ ✓ ✓ P3CHATEN3 – ✓ ✓ ✓ P3CHATEN2 ✓ ✓ ✓ ✓ P3CHATEN1 ✓ ✓ ✓ ✓ P3CHATEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-12 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 377 ✓ ✓ P4OEN5 ✓ ✓ ✓ ✓ P4OEN4 – ✓ ✓ ✓ P4OEN3 – ✓ ✓ ✓ P4OEN2 – – ✓ ✓ P4OEN1 – – ✓ ✓ P4OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-13 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 378 ✓ ✓ P4CHATEN5 ✓ ✓ ✓ ✓ P4CHATEN4 – ✓ ✓ ✓ P4CHATEN3 – ✓ ✓ ✓ P4CHATEN2 – – ✓ ✓ P4CHATEN1 – – ✓ ✓ P4CHATEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-14 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 379 ✓ P5OEN5 – – – ✓ P5OEN4 – – – ✓ P5OEN3 – – ✓ ✓ P5OEN2 – – ✓ ✓ P5OEN1 ✓ ✓ ✓ ✓ P5OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-15 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 380 ✓ P5CHATEN5 – – – ✓ P5CHATEN4 – – – ✓ P5CHATEN3 – – ✓ ✓ P5CHATEN2 – – ✓ ✓ P5CHATEN1 ✓ ✓ ✓ ✓ P5CHATEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-16 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 381 ✓ P6OEN5 – – – ✓ P6OEN4 – – ✓ ✓ P6OEN3 – – ✓ ✓ P6OEN2 ✓ ✓ ✓ ✓ P6OEN1 ✓ ✓ ✓ ✓ P6OEN0 – – – ✓ Seiko Epson Corporation AP-A-17 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 382 ✓ P6CHATEN5 – – – ✓ P6CHATEN4 – – ✓ ✓ P6CHATEN3 – – ✓ ✓ P6CHATEN2 ✓ ✓ ✓ ✓ P6CHATEN1 ✓ ✓ ✓ ✓ P6CHATEN0 – – – ✓ Seiko Epson Corporation AP-A-18 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 383 ✓ P7OEN5 – – – ✓ P7OEN4 – – ✓ ✓ P7OEN3 ✓ ✓ ✓ ✓ P7OEN2 ✓ ✓ ✓ ✓ P7OEN1 – ✓ ✓ ✓ P7OEN0 – ✓ ✓ ✓ Seiko Epson Corporation AP-A-19 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 384 ✓ P7CHATEN5 – – – ✓ P7CHATEN4 – – ✓ ✓ P7CHATEN3 ✓ ✓ ✓ ✓ P7CHATEN2 ✓ ✓ ✓ ✓ P7CHATEN1 – ✓ ✓ ✓ P7CHATEN0 – ✓ ✓ ✓ Seiko Epson Corporation AP-A-20 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 385 ✓ ✓ P8OEN5 ✓ ✓ ✓ ✓ P8OEN4 ✓ ✓ ✓ ✓ P8OEN3 ✓ ✓ ✓ ✓ P8OEN2 – ✓ ✓ ✓ P8OEN1 – ✓ ✓ ✓ P8OEN0 – – ✓ ✓ Seiko Epson Corporation AP-A-21 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 386 ✓ ✓ P8CHATEN5 ✓ ✓ ✓ ✓ P8CHATEN4 ✓ ✓ ✓ ✓ P8CHATEN3 ✓ ✓ ✓ ✓ P8CHATEN2 – ✓ ✓ ✓ P8CHATEN1 – ✓ ✓ ✓ P8CHATEN0 – – ✓ ✓ Seiko Epson Corporation AP-A-22 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 387 P9OEN5 – ✓ ✓ ✓ ✓ P9OEN4 ✓ ✓ ✓ ✓ P9OEN3 ✓ ✓ ✓ ✓ P9OEN2 ✓ ✓ ✓ ✓ P9OEN1 ✓ ✓ ✓ ✓ P9OEN0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-23 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 388 P9SEL5 – ✓ ✓ ✓ ✓ P9SEL4 ✓ ✓ ✓ ✓ P9SEL3 ✓ ✓ ✓ ✓ P9SEL2 ✓ ✓ ✓ ✓ P9SEL1 ✓ ✓ ✓ ✓ P9SEL0 ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-24 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 389 ✓ PAREN5 – – – ✓ PAREN4 – – ✓ ✓ PAREN3 ✓ ✓ ✓ ✓ PAREN2 – ✓ ✓ ✓ PAREN1 – ✓ ✓ ✓ PAREN0 – – ✓ ✓ Seiko Epson Corporation AP-A-25 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 390 ✓ 9–8 PA4MUX[1:0] – – ✓ ✓ 7–6 PA3MUX[1:0] ✓ ✓ ✓ ✓ 5–4 PA2MUX[1:0] – ✓ ✓ ✓ 3–2 PA1MUX[1:0] – ✓ ✓ ✓ 1–0 PA0MUX[1:0] – – ✓ ✓ Seiko Epson Corporation AP-A-26 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 391 Select Register) 9–8 PD4MUX[1:0] – – ✓ ✓ 7–6 PD3MUX[1:0] ✓ ✓ ✓ ✓ 5–4 PD2MUX[1:0] ✓ ✓ ✓ ✓ 3–2 PD1MUX[1:0] ✓ ✓ ✓ ✓ 1–0 PD0MUX[1:0] ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-27 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 392 2–0 P10PERISEL[2:0] 0x0020 UPMUXP1MUX1 15–13 P13PPFNC[2:0] – ✓ ✓ ✓ ✓ 030a (P12–13 Universal 12–11 P13PERICH[1:0] Port Multiplexer 10–8 P13PERISEL[2:0] Setting Register) 7–5 P12PPFNC[2:0] – ✓ ✓ ✓ 4–3 P12PERICH[1:0] 2–0 P12PERISEL[2:0] Seiko Epson Corporation AP-A-28 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 393 2–0 P32PERISEL[2:0] 0x0020 UPMUXP3MUX2 15–13 P35PPFNC[2:0] – – – ✓ ✓ 031c (P34–35 Universal 12–11 P35PERICH[1:0] Port Multiplexer 10–8 P35PERISEL[2:0] Setting Register) 7–5 P34PPFNC[2:0] – ✓ ✓ ✓ 4–3 P34PERICH[1:0] 2–0 P34PERISEL[2:0] Seiko Epson Corporation AP-A-29 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 394: Uart (Uart3) Ch.0
UART3_0RXD register. PEIF H0/S0 OEIF H0/S0 Cleared by writing 1. RB2FIF H0/S0 Cleared by reading the UART3_0RXD register. RB1FIF H0/S0 TBEIF H0/S0 Cleared by writing to the UART3_0TXD register. Seiko Epson Corporation AP-A-30 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 395: 0X0020 03A0-0X0020 03Ac 16-Bit Timer (T16) Ch.1
(T16 Ch.1 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x0020 T16_1INTE 15–8 – 0x00 – – 03ac (T16 Ch.1 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-31 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 396 Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] 0x0020 I2C_0MOD 15–8 – 0x00 – – 03c2 (I2C Ch.0 Mode 7–3 – 0x00 – Register) OADR10 GCEN – – Seiko Epson Corporation AP-A-32 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 397 – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) 0x0020 I2C_0RBFDMAEN 15–8 – 0x00 – – 03d6 (I2C Ch.0 Receive 7–4 – – Buffer Full DMA Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation AP-A-33 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 398 Enable Register) CMPCAP3IE CAPOW2IE CMPCAP2IE CAPOW1IE CMPCAP1IE CAPOW0IE CMPCAP0IE CNTMAXIE CNTZEROIE 0x0020 T16B_0MZDMAEN 15–8 – 0x00 – – 040e (T16B Ch.0 Counter 7–4 – – Max/Zero DMA Request Enable 3–0 MZDMAEN[3:0] Register) Seiko Epson Corporation AP-A-34 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 399 – 0422 (T16B Ch.0 Compare/ Capture 2 Data Register) 0x0020 T16B_0CC2DMAEN 15–8 – 0x00 – – 0424 (T16B Ch.0 Compare/ 7–4 – – Capture 2 DMA Request Enable 3–0 CC2DMAEN[3:0] Register) Seiko Epson Corporation AP-A-35 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 400 15–0 TC[15:0] 0x0000 – 0446 (T16B Ch.1 Timer Counter Data Register) 0x0020 T16B_1CS 15–8 – 0x00 – – 0448 (T16B Ch.1 Counter 7–6 – – Status Register) CAPI3 CAPI2 CAPI1 CAPI0 UP_DOWN Seiko Epson Corporation AP-A-36 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 401 14–12 CBUFMD[2:0] Capture 1 Control 11–10 CAPIS[1:0] Register) 9–8 CAPTRG[1:0] – – TOUTMT TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD 0x0020 T16B_1CCR1 15–0 CC[15:0] 0x0000 – 045a (T16B Ch.1 Compare/ Capture 1 Data Register) Seiko Epson Corporation AP-A-37 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 402 – – 0482 (T16 Ch.3 Mode 7–1 – 0x00 – Register) TRMD 0x0020 T16_3CTL 15–9 – 0x00 – – 0484 (T16 Ch.3 Control PRUN Register) 7–2 – 0x00 – PRESET MODEN Seiko Epson Corporation AP-A-38 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 403: 0X0020 04A0-0X0020 04Ac 16-Bit Timer (T16) Ch.4
0x0020 T16_5CTL 15–9 – 0x00 – – 04c4 (T16 Ch.5 Control PRUN Register) 7–2 – 0x00 – PRESET MODEN 0x0020 T16_5TR 15–0 TR[15:0] 0xffff – 04c6 (T16 Ch.5 Reload Data Register) Seiko Epson Corporation AP-A-39 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 404 – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) 0x0020 SPIA_2RBFDMAEN 15–8 – 0x00 – – 04de (SPIA Ch.2 Receive 7–4 – – Buffer Full DMA Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation AP-A-40 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 405: 0X0020 0600-0X0020 0614 Uart (Uart3) Ch.1
TBEIF H0/S0 Cleared by writing to the UART3_1TXD register. 0x0020 UART3_1INTE 15–8 – 0x00 – – 060e (UART3 Ch.1 – – Interrupt Enable TENDIE Register) FEIE PEIE OEIE RB2FIE RB1FIE TBEIE Seiko Epson Corporation AP-A-41 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 406 15–8 – 0x00 – – 0628 (UART3 Ch.2 Trans- 7–0 TXD[7:0] 0x00 mit Data Register) 0x0020 UART3_2RXD 15–8 – 0x00 – – 062a (UART3 Ch.2 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation AP-A-42 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 407: 0X0020 0660-0X0020 066C 16-Bit Timer (T16) Ch.6
Register) 7–2 – 0x00 – PRESET MODEN 0x0020 T16_6TR 15–0 TR[15:0] 0xffff – 0666 (T16 Ch.6 Reload Data Register) 0x0020 T16_6TC 15–0 TC[15:0] 0xffff – 0668 (T16 Ch.6 Counter Data Register) Seiko Epson Corporation AP-A-43 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 408 – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) 0x0020 SPIA_1RBFDMAEN 15–8 – 0x00 – – 067e (SPIA Ch.1 Receive 7–4 – – Buffer Full DMA Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation AP-A-44 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 409: 0X0020 0680-0X0020 068C 16-Bit Timer (T16) Ch.2
7–4 – – Register) MSTSSO SFTRST MODEN 0x0020 QSPI_0TXD 15–0 TXD[15:0] 0x0000 – 0694 (QSPI Ch.0 Transmit Data Register) 0x0020 QSPI_0RXD 15–0 RXD[15:0] 0x0000 – 0696 (QSPI Ch.0 Receive Data Register) Seiko Epson Corporation AP-A-45 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 410 Register name Bit name Initial Reset Remarks 0x0020 I2C_1CLK 15–9 – 0x00 – – 06c0 (I2C Ch.1 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-46 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 411 – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) 0x0020 I2C_1RBFDMAEN 15–8 – 0x00 – – 06d6 (I2C Ch.1 Receive 7–4 – – Buffer Full DMA Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation AP-A-47 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 412 I2C_2RXD register. TBEIF H0/S0 Cleared by writing to the I2C_2TXD register. 0x0020 I2C_2INTE 15–8 – 0x00 – – 06f2 (I2C Ch.2 Interrupt BYTEENDIE Enable Register) GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Seiko Epson Corporation AP-A-48 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 413: 0X0020 0720-0X0020 0732 Ir Remote Controller (Remc3)
15–8 CRDTY[7:0] 0x00 – 0730 (REMC3 Carrier 7–0 CRPER[7:0] 0x00 Waveform Register) 0x0020 REMC3CCTL 15–9 – 0x00 – – 0732 (REMC3 Carrier OUTINVEN Modulation Control 7–1 – 0x00 – Register) CARREN Seiko Epson Corporation AP-A-49 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 414 – figuration Register) 1–0 VRANGE[1:0] 0x0020 ADC12A_0INTF 15–9 – 0x00 – – 07a8 (ADC12A Ch.0 OVIF Cleared by writing 1. Interrupt Flag AD7CIF Register) AD6CIF AD5CIF AD4CIF AD3CIF AD2CIF AD1CIF AD0CIF Seiko Epson Corporation AP-A-50 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 415: 0X0020 0840-0X0020 0850 R/F Converter (Rfc) Ch.0
7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] 0x0020 RFC_0CTL 15–9 – 0x00 – – 0842 (RFC Ch.0 Control RFCLKMD Register) CONEN EVTEN 5–4 SMODE[1:0] 3–1 – – MODEN Seiko Epson Corporation AP-A-51 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 416 (SDAC Interrupt Flag 7–2 – 0x00 – Register) ERRIF Cleared by writing 1. DATREQIF 0x0020 SDACINTE 15–8 – 0x00 – – 086a (SDAC Interrupt 7–2 – 0x00 – Enable Register) ERRIE DATREQIE Seiko Epson Corporation AP-A-52 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 417: 0X0020 08A0-0X0020 08A8 Hw Processor (Hwp)
– – 3–0 RMCLR[3:0] – – 0x0020 DMACENSET 31–24 – 0x00 – – 1028 (DMAC Enable Set 23–16 – 0x00 – Register) 15–8 – 0x00 – 7–4 – – 3–0 ENSET[3:0] Seiko Epson Corporation AP-A-53 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 418 – ERRIESET 0x0020 DMACERRIECLR 31–24 – 0x00 – – 2014 (DMAC Error Interrupt 23–16 – 0x00 – Enable Clear Register) 15–8 – 0x00 – 7–1 – 0x00 – ERRIECLR – – Seiko Epson Corporation AP-A-54 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 419 • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation AP-B-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 420 Continuous operation mode (SVD3CTL.SVDMD[1:0] bits = 0x0) always detects the power supply voltage, therefore, it increases current consumption. Set the supply voltage detector to intermittent operation mode or turn it on only when required. Seiko Epson Corporation AP-B-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 421 Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation AP-C-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 422 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 423 • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation AP-D-1 S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00)
Page 424 Code No. Page Contents 413699401 New establishment 413699403 Appended “D51” to the model names (S1C31D50/D51) P1-1, 1-3, Added descriptions of the S1C31D51, and modified the figures/tables 4-1, 21-1 to Differences between S1C31D50 and S1C31D51 6, 21-18, • General-purpose RAM size and Voice RAM size 23-2 •...
Page 425 Fax: +86-10-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Phone: +49-89-14005-0 Fax: +49-89-14005-110 Epson Taiwan Technology & Trading Ltd. 15F, No.100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd. 1 HarbourFront Place,...

This manual is also suitable for:

S1c31d51

Epson S1C31D50 Technical Manual

1 Overview

2 Power Supply, Reset, and Clocks

3 CPU and Debugger

4 Memory and Bus

5 Interrupt

6 DMA Controller (DMAC)

7 O Ports (PPORT)

8 Universal Port Multiplexer (UPMUX)

9 Watchdog Timer (WDT2)

10 Real-Time Clock (RTCA)

11 Supply Voltage Detector (SVD3)

16-Bit Timers (T16)

13 Uart (Uart3)

14 Synchronous Serial Interface (SPIA)

15 Quad Synchronous Serial Interface (QSPI)

Quick Links

Related Manuals for Epson S1C31D50

Summary of Contents for Epson S1C31D50