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periods. Incoming interrupts are synchronized over two clock cycles to the operating
clock of the ICU.
It is a requirement that interrupt signals from all circuitry parts with higher clock frequency
outside the ICU are lengthened to the appropriate minimum pulse time.
The ICU supplies a separate output signal to serve both interrupt levels of the CPU (INTB
and INTA). The interrupt processing within the ICU is performed in separate subblocks for
INTB and INTA. The output signals for the ICU are level-triggered and "active high".
The output signals become inactive again when the interrupt from the CPU is confirmed
or when the Interrupt Request is masked by the CPU before it is acknowledged.
The INTA subblock supports NUM_OF_INT (NUM_OF_INT = 96) interrupt inputs; the
INTB subblock supports NUM_OF_FINT (NUM_OF_INT = 8) interrupt inputs.
Each interrupt source of the INTA subblock can be placed on each interrupt input of the
INTB subblock, where the selected interrupt sources also continue to remain active in the
INTA subblock. The "INTB0" is the exception, because no INTA can be placed on it. For
the configuration of the assignment by the software, the numbers of the selected INTA
inputs are entered in the INTB_SEL_1 – INTB_SEL_ registers. Alt-
hough the INTB_SEL_0 register can be read and written, it is not further processed by
the hardware.
Note that both INTAs and INTBs are edge-triggered as initial setting. If level triggering is
set, the interrupt at the source must be removed, otherwise it will issue a new interrupt
(INTA or INTB) to the CPU after the acknowledge. Note further that only high active
level (in level triggering mode) is supported by ICU whereas in edge triggering
mode both edges are supported. INTA and INTB must always be set to the same trig-
gering. Because this is not checked by the ICU, it must be ensured by the software. In
addition, the software should normally mask the INTA input in the INTA subblock used as
INTB, because otherwise both an INTA and an INTB will be signaled to the CPU when
the interrupt occurs.
The interrupt with number "0" in the INTA subblock is not stimulated by any interrupt
source. The Fast Interrupt with number "0" cannot be assigned by any arbitrary INTA
input but is clamped statically in the ICU itself to "inactive".
The interrupt with number "0" may not be used either in the INTA subblock or in the INTB
subblock. "INTA0" outside the ICU is clamped to the inactive level; the "INTB0" inside
the ICU is clamped to the inactive level. This means that a differentiation between the
default vector and the interrupt vector with number "0" is no longer necessary which sim-
plifies the processing of the default vector by the software.
The ICU supports the AHB-Lite protocol. The ICU has a 32-bit wide data bus. Word ac-
cesses only are supported.
2.3.2.8 Interrupt acquisition
An interrupt to an input signal can be recognized both on an edge and on the level of the
input signal. This trigger mode can be separated for each interrupt input by setting the
appropriate bit in the TRIGREG register. Level-triggered interrupts are acquired as
"active high". The initial setting for each interrupt is the detection of the positive edge.
In edge-triggered mode, each level on the input for synchronous signals must be stable
for at least one clock, for asynchronous signals for at least two clocks.
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ERTEC 200P-2 Manual
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