Siemens C16 Series Instruction Set Manual

Siemens C16 Series Instruction Set Manual

16-bit cmos single-chip microcontrollers
Instruction Set Manual
for the C16x Family of
Siemens 16-Bit CMOS Single-Chip Microcontrollers
Instruction Set Manual Version 1.2, 12.97
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Summary of Contents for Siemens C16 Series

  • Page 1 Instruction Set Manual for the C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers Instruction Set Manual Version 1.2, 12.97...
  • Page 2 Critical components of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems with the ex- press written approval of the Semiconductor Group of Siemens AG.
  • Page 3 Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected]...
  • Page 4: Table Of Contents

    C166 Family Instruction Set Table of Contents Table of Contents Page Introduction ............5 Short Instruction Summary.
  • Page 5: Introduction

    Still the Siemens family concept provides an easy path to upgrade existing applications or to climb the next level of performance in order to realize a subsequent more sophisticated design. Two...
  • Page 6: Short Instruction Summary

    C166 Family Instruction Set 30Mar98@15:00h Short Instruction Summary Short Instruction Summary The following compressed cross-reference tables quickly identify a specific instruction and provide basic information about it. Two ordering schemes are included: The first table (two pages) is a compressed cross-reference table that quickly identifies a specific hexadecimal opcode with the respective mnemonic.
  • Page 7 C166 Family Instruction Set 30Mar98@15:00h Short Instruction Summary Note: Both ordering schemes (hexadecimal opcode and mnemonic) are provided in more detailled lists in the following sections of this manual. Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. They are marked in the cross-reference table.
  • Page 8 C166 Family Instruction Set 30Mar98@15:00h Short Instruction Summary Mnemonic Addressing ModesBytes Mnemonic Addressing ModesBytes ADD[B] CPL[B] ADDC[B] [Rwi] NEG[B] AND[B] [Rwi+] OR[B] #data3 DIVL SUB[B] DIVLU SUBC[B] #data16 DIVU XOR[B] MULU ASHR CMPD1/2 #data4 ROL / ROR #data4 CMPI1/2 #data16 SHL / SHR BAND bitaddrZ.z...
  • Page 9: Instruction Set Summary

    C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary This chapter summarizes the instructions by listing them according to their functional class. This allows to identify the right instruction(s) for a specific required function. The following notes apply to this summary: Data Addressing Modes –...
  • Page 10 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Extension Operations The EXT* instructions override the standard DPP addressing scheme: #pag10: – Immediate 10-bit page address. #seg8: – Immediate 8-bit segment address. Note: The EXTended instructions are not available in the SAB 8XC166(W) devices. Branch Condition Codes Symbolically specifiable condition codes cc_UC...
  • Page 11 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary Mnemonic Description Bytes Arithmetic Operations Rw, Rw Add direct word GPR to direct GPR Rw, [Rw] Add indirect word memory to direct GPR Rw, [Rw +] Add indirect word memory to direct GPR and post- increment source pointer by 2 Rw, #data3 Add immediate word data to direct GPR...
  • Page 12 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Arithmetic Operations (cont’d) ADDCB mem, reg Add direct byte register to direct memory with Carry Rw, Rw Subtract direct word GPR from direct GPR Rw, [Rw] Subtract indirect word memory from direct GPR Rw, [Rw +] Subtract indirect word memory from direct GPR and...
  • Page 13 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Arithmetic Operations (cont’d) SUBCB reg, mem Subtract direct byte memory from direct register with Carry SUBCB mem, reg Subtract direct byte register from direct memory with Carry Rw, Rw Signed multiply direct GPR by direct GPR (16-16-bit) MULU...
  • Page 14 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Logical Instructions (cont’d) Rw, Rw Bitwise OR direct word GPR with direct GPR Rw, [Rw] Bitwise OR indirect word memory with direct GPR Rw, [Rw +] Bitwise OR indirect word memory with direct GPR and post-increment source pointer by 2 Rw, #data3...
  • Page 15 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Boolean Bit Manipulation Operations BCLR bitaddr Clear direct bit BSET bitaddr Set direct bit BMOV bitaddr, bitaddr Move direct bit to direct bit BMOVN bitaddr, bitaddr Move negated direct bit to direct bit BAND bitaddr, bitaddr...
  • Page 16 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Compare and Loop Control Instructions (cont’d) CMPD1 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 1 CMPD2 Rw, #data4 Compare immediate word data to direct GPR and decrement GPR by 2 CMPD2 Rw, #data16...
  • Page 17 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Shift and Rotate Instructions (cont’d) Rw, #data4 Shift right direct word GPR; number of shift cycles specified by immediate data Rw, Rw Rotate left direct word GPR; number of shift cycles specified by direct GPR Rw, #data4 Rotate left direct word GPR;...
  • Page 18 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Data Movement (cont’d) [Rw], mem Move direct word memory to indirect memory mem, [Rw] Move indirect word memory to direct memory reg, mem Move direct word memory to direct register mem, reg Move direct word register to direct memory MOVB...
  • Page 19 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Data Movement (cont’d) MOVBZ Rw, Rb Move direct byte GPR with zero extension to direct word GPR MOVBZ reg, mem Move direct byte memory with zero extension to direct word register MOVBZ mem, reg...
  • Page 20 C166 Family Instruction Set 30Mar98@15:00h Instruction Set Summary Instruction Set Summary (cont’d)* Mnemonic Description Bytes Return Operations Return from intra-segment subroutine RETS Return from inter-segment subroutine RETP Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine System Control SRST...
  • Page 21: Instruction Opcodes

    C166 Family Instruction Set 30Mar98@15:00h Instruction Opcodes Instruction Opcodes The following pages list the instructions of the 16-bit microcontrollers ordered by their hexadecimal opcodes. This helps to identify specific instructions when reading executable code, ie. during the debugging phase. Notes for Opcode Lists These instructions are encoded by means of additional bits in the operand field of the instruction –...
  • Page 22 C166 Family Instruction Set 30Mar98@15:00h Instruction Opcodes Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of ber of code Bytes Bytes Rw, Rw Rw, Rw ADDB Rb, Rb SUBB Rb, Rb reg, mem reg, mem ADDB reg, mem SUBB reg, mem mem, reg...
  • Page 23 C166 Family Instruction Set 30Mar98@15:00h Instruction Opcodes Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of code ber of Bytes Bytes Rw, Rw Rw, Rw CMPB Rb, Rb ANDB Rb, Rb reg, mem reg, mem CMPB reg, mem ANDB reg, mem mem, reg...
  • Page 24 C166 Family Instruction Set 30Mar98@15:00h Instruction Opcodes Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of code ber of Bytes Bytes CMPI1 Rw, #data4 CMPD1 Rw, #data4 NEGB CMPI1 Rw, mem CMPD1 Rw, mem [Rw], mem MOVB [Rw], mem DISWDT CMPI1 Rw, #data16...
  • Page 25 C166 Family Instruction Set 30Mar98@15:00h Instruction Opcodes Hex- Num- Mnemonic Operands Hex- Num- Mnemonic Operands code ber of code ber of Bytes Bytes MOVBZ Rw, Rb Rw, #data4 MOVB Rb, #data4 MOVBZ reg, mem PCALL reg, caddr [Rw+#data16], MOVB [Rw+#data16], MOVBZ mem, reg SCXT...
  • Page 26: Instruction Description

    C166 Family Instruction Set 30Mar98@15:00h Instruction Description Instruction Description This chapter describes each instruction in detail. The instructions are ordered alphabetically, and the description contains the following elements: •Instruction Name• Specifies the mnemonic opcode of the instruction in oversized bold lettering for easy reference.
  • Page 27 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Missing or existing parentheses signify whether the used operand specifies an immediate constant value, an address or a pointer to an address as follows: Specifies the immediate constant value of opX (opX) Specifies the contents of opX (opX Specifies the contents of bit n of opX ((opX))
  • Page 28 C166 Family Instruction Set 30Mar98@15:00h Instruction Description •Description• This part provides a brief verbal description of the action that is executed by the respective instruction. •Condition Code• This notifies that the respective instruction contains a condition code, so it is executed, if the specified condition is true, and is skipped, if it is false.
  • Page 29 C166 Family Instruction Set 30Mar98@15:00h Instruction Description •Condition Flags• This part reflects the state of the N, C, V, Z and E flags in the PSW register which is the state after execution of the corresponding instruction, except if the PSW register itself was specified as the destination operand of that instruction (see Note).
  • Page 30 C166 Family Instruction Set 30Mar98@15:00h Instruction Description •Addressing Modes• This part specifies which combinations of different addressing modes are available for the required operands. Mostly, the selected addressing mode combination is specified by the opcode of the corresponding instruction. However, there are some arithmetic and logical instructions where the addressing mode combination is not specified by the (identical) opcodes but by particular bits within the operand field.
  • Page 31 C166 Family Instruction Set 30Mar98@15:00h Instruction Description N2N1 N4N3 N6N5 N8N7 Representation in the Assembler Listing: High Byte 2nd word Low Byte 2nd word High Byte 1st word Low Byte 1st word Internal Organization: Bits in ascending order LSB Figure 5-1: Instruction Format Representation Notes on the ATOMIC and EXTended Instructions These instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable standard and PEC interrupts and class A traps during a sequence of the following 1...4 instructions.
  • Page 32 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Integer Addition Syntax op1, op2 (op1) ← (op1) + (op2) Operation Data Types WORD Description Performs a 2’s complement binary addition of the source operand speci- fied by op2 and the destination operand specified by op1. The sum is then stored in op1.
  • Page 33 C166 Family Instruction Set 30Mar98@15:00h Instruction Description ADDB ADDB Integer Addition Syntax ADDB op1, op2 (op1) ← (op1) + (op2) Operation Data Types BYTE Description Performs a 2’s complement binary addition of the source operand speci- fied by op2 and the destination operand specified by op1. The sum is then stored in op1.
  • Page 34 C166 Family Instruction Set 30Mar98@15:00h Instruction Description ADDC ADDC Integer Addition with Carry Syntax ADDC op1, op2 (op1) ← (op1) + (op2) + (C) Operation Data Types WORD Description Performs a 2’s complement binary addition of the source operand speci- fied by op2, the destination operand specified by op1 and the previously generated carry bit.
  • Page 35 C166 Family Instruction Set 30Mar98@15:00h Instruction Description ADDCB ADDCB Integer Addition with Carry Syntax ADDCB op1, op2 (op1) ← (op1) + (op2) + (C) Operation Data Types BYTE Description Performs a 2’s complement binary addition of the source operand speci- fied by op2, the destination operand specified by op1 and the previously generated carry bit.
  • Page 36 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Logical AND Syntax op1, op2 (op1) ← (op1) ∧ (op2) Operation Data Types WORD Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1.
  • Page 37 C166 Family Instruction Set 30Mar98@15:00h Instruction Description ANDB ANDB Logical AND Syntax ANDB op1, op2 (op1) ← (op1) ∧ (op2) Operation Data Types BYTE Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1.
  • Page 38 C166 Family Instruction Set 30Mar98@15:00h Instruction Description ASHR ASHR Arithmetic Shift Right Syntax ASHR op1, op2 (count) ← (op2) Operation (V) ← 0 (C) ← 0 DO WHILE (count) ≠ 0 (V) ← (C) ∨ (V) (C) ← (op1 ) ← (op1 (op1 ) [n=0...14] (count) ←...
  • Page 39 C166 Family Instruction Set 30Mar98@15:00h Instruction Description ATOMIC ATOMIC Begin ATOMIC Sequence Syntax ATOMIC (count) ← (op1) [1 ≤ op1 ≤ 4] Operation Disable interrupts and Class A traps DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ←...
  • Page 40 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BAND BAND Bit Logical AND Syntax BAND op1, op2 (op1) ← (op1) ∧ (op2) Operation Data Types Description Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1. The result is then stored in op1. Condition Flags E Always cleared.
  • Page 41 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BCLR BCLR Bit Clear Syntax BCLR (op1) ← 0 Operation Data Types Description CLears the bit specified by op1. This instruction is primarily used for peripheral and system control. Condition Flags E Always cleared. Z Contains the logical negation of the previous state of the specified bit.
  • Page 42 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BCMP BCMP Bit to Bit Compare Syntax BCMP op1, op2 (op1) ⇔ (op2) Operation Data Types Description Performs a single bit comparison of the source bit specified by operand op1 to the source bit specified by operand op2. No result is written by this instruction.
  • Page 43 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BFLDH BFLDH Bit Field High Byte Syntax BFLDH op1, op2, op3 (tmp) ← (op1) Operation (high byte (tmp)) ← ((high byte (tmp) ∧ ¬op2) ∨ op3) (op1) ← (tmp) Data Types WORD Description Replaces those bits in the high byte of the destination word operand op1 which are selected by a ’1’...
  • Page 44 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BFLDL BFLDL Bit Field Low Byte Syntax BFLDL op1, op2, op3 (tmp) ← (op1) Operation (low byte (tmp)) ← ((low byte (tmp) ∧ ¬op2) ∨ op3) (op1) ← (tmp) Data Types WORD Description Replaces those bits in the low byte of the destination word operand op1 which are selected by a ’1’...
  • Page 45 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BMOV BMOV Bit to Bit Move Syntax BMOV op1, op2 (op1) ← (op2) Operation Data Types Description Moves a single bit from the source operand specified by op2 into the des- tination operand specified by op1. The source bit is examined and the flags are updated accordingly.
  • Page 46 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BMOVN BMOVN Bit to Bit Move and Negate Syntax BMOVN op1, op2 (op1) ← ¬(op2) Operation Data Types Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1. The source bit is examined and the flags are updated accordingly.
  • Page 47 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Bit Logical OR Syntax op1, op2 (op1) ← (op1) ∨ (op2) Operation Data Types Description Performs a single bit logical OR of the source bit specified by operand op2 with the destination bit specified by operand op1. The ORed result is then stored in op1.
  • Page 48 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BSET BSET Bit Set Syntax BSET (op1) ← 1 Operation Data Types Description Sets the bit specified by op1. This instruction is primarily used for periph- eral and system control. Condition Flags E Always cleared. Z Contains the logical negation of the previous state of the specified bit.
  • Page 49 C166 Family Instruction Set 30Mar98@15:00h Instruction Description BXOR BXOR Bit Logical XOR Syntax BXOR op1, op2 (op1) ← (op1) ⊕ (op2) Operation Data Types Description Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2 with the destination bit specified by operand op1. The XORed result is then stored in op1.
  • Page 50 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CALLA CALLA Call Subroutine Absolute Syntax CALLA op1, op2 Operation IF (op1) THEN (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← op2 ELSE next instruction END IF Description If the condition specified by op1 is met, a branch to the absolute memory location specified by the second operand op2 is taken.
  • Page 51 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CALLI CALLI Call Subroutine Indirect Syntax CALLI op1, op2 Operation IF (op1) THEN (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← op2 ELSE next instruction END IF Description If the condition specified by op1 is met, a branch to the location specified indirectly by the second operand op2 is taken.
  • Page 52 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CALLR CALLR Call Subroutine Relative Syntax CALLR (SP) ← (SP) - 2 Operation ((SP)) ← (IP) (IP) ← (IP) + sign_extend (op1) Description A branch is taken to the location specified by the instruction pointer, IP, plus the relative displacement, op1.
  • Page 53 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CALLS CALLS Call Inter-Segment Subroutine Syntax CALLS op1, op2 (SP) ← (SP) - 2 Operation ((SP)) ← (CSP) (SP) ← (SP) - 2 ((SP)) ← (IP) (CSP) ← op1 (IP) ← op1 Description A branch is taken to the absolute location specified by op2 within the seg- ment specified by op1.
  • Page 54 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Integer Compare Syntax op1, op2 (op1) ⇔ (op2) Operation Data Types WORD Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1.
  • Page 55 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CMPB CMPB Integer Compare Syntax CMPB op1, op2 (op1) ⇔ (op2) Operation Data Types BYTE Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1.
  • Page 56 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CMPD1 CMPD1 Integer Compare and Decrement by 1 Syntax CMPD1 op1, op2 (op1) ⇔ (op2) Operation (op1) ← (op1) - 1 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops.
  • Page 57 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CMPD2 CMPD2 Integer Compare and Decrement by 2 Syntax CMPD2 op1, op2 (op1) ⇔ (op2) Operation (op1) ← (op1) - 2 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops.
  • Page 58 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CMPI1 CMPI1 Integer Compare and Increment by 1 Syntax CMPI1 op1, op2 (op1) ⇔ (op2) Operation (op1) ← (op1) + 1 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops.
  • Page 59 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CMPI2 CMPI2 Integer Compare and Increment by 2 Syntax CMPI2 op1, op2 (op1) ⇔ (op2) Operation (op1) ← (op1) + 2 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops.
  • Page 60 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Integer One’s Complement Syntax (op1) ← ¬(op1) Operation Data Types WORD Description Performs a 1’s complement of the source operand specified by op1. The result is stored back into op1. Condition Flags E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise.
  • Page 61 C166 Family Instruction Set 30Mar98@15:00h Instruction Description CPLB CPLB Integer One’s Complement Syntax (op1) ← ¬(op1) Operation Data Types BYTE Description Performs a 1’s complement of the source operand specified by op1. The result is stored back into op1. Condition Flags E Set if the value of op1 represents the lowest possible negative number.
  • Page 62 C166 Family Instruction Set 30Mar98@15:00h Instruction Description DISWDT DISWDT Disable Watchdog Timer Syntax DISWDT Operation Disable the watchdog timer Description This instruction disables the watchdog timer. The watchdog timer is ena- bled by a reset. The DISWDT instruction allows the watchdog timer to be disabled for applications which do not require a watchdog function.
  • Page 63 C166 Family Instruction Set 30Mar98@15:00h Instruction Description 16-by-16 Signed Division Syntax (MDL) ← (MDL) / (op1) Operation (MDH) ← (MDL) mod (op1) Data Types WORD Description Performs a signed 16-bit by 16-bit division of the low order word stored in the MD register by the source word operand op1.
  • Page 64 C166 Family Instruction Set 30Mar98@15:00h Instruction Description DIVL DIVL 32-by-16 Signed Division Syntax DIVL (MDL) ← (MD) / (op1) Operation (MDH) ← (MD) mod (op1) Data Types WORD, DOUBLEWORD Description Performs an extended signed 32-bit by 16-bit division of the two words stored in the MD register by the source word operand op1.
  • Page 65 C166 Family Instruction Set 30Mar98@15:00h Instruction Description DIVLU DIVLU 32-by-16 Unsigned Division Syntax DIVLU (MDL) ← (MD) / (op1) Operation (MDH) ← (MD) mod (op1) Data Types WORD, DOUBLEWORD Description Performs an extended unsigned 32-bit by 16-bit division of the two words stored in the MD register by the source word operand op1.
  • Page 66 C166 Family Instruction Set 30Mar98@15:00h Instruction Description DIVU DIVU 16-by-16 Unsigned Division Syntax DIVU (MDL) ← (MDL) / (op1) Operation (MDH) ← (MDL) mod (op1) Data Types WORD Description Performs an unsigned 16-bit by 16-bit division of the low order word stored in the MD register by the source word operand op1.
  • Page 67 C166 Family Instruction Set 30Mar98@15:00h Instruction Description EINIT EINIT End of Initialization Syntax EINIT Operation End of Initialization Description This instruction is used to signal the end of the initialization portion of a program. After a reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT instruction has been executed at which time it goes high.
  • Page 68 C166 Family Instruction Set 30Mar98@15:00h Instruction Description EXTR EXTR Begin EXTended Register Sequence Syntax EXTR (count) ← (op1) [1 ≤ op1 ≤ 4] Operation Disable interrupts and Class A traps SFR_range = Extended DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ←...
  • Page 69 C166 Family Instruction Set 30Mar98@15:00h Instruction Description EXTP EXTP Begin EXTended Page Sequence Syntax EXTP op1, op2 (count) ← (op2) [1 ≤ op2 ≤ 4] Operation Disable interrupts and Class A traps Data_Page = (op1) DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ←...
  • Page 70 C166 Family Instruction Set 30Mar98@15:00h Instruction Description EXTPR EXTPR Begin EXTended Page and Register Sequence Syntax EXTPR op1, op2 (count) ← (op2) [1 ≤ op2 ≤ 4] Operation Disable interrupts and Class A traps Data_Page = (op1) AND SFR_range = Extended DO WHILE ((count) ≠...
  • Page 71 C166 Family Instruction Set 30Mar98@15:00h Instruction Description EXTS EXTS Begin EXTended Segment Sequence Syntax EXTS op1, op2 (count) ← (op2) [1 ≤ op2 ≤ 4] Operation Disable interrupts and Class A traps Data_Segment = (op1) DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ←...
  • Page 72 C166 Family Instruction Set 30Mar98@15:00h Instruction Description EXTSR EXTSR Begin EXTended Segment and Register Sequence Syntax EXTSR op1, op2 (count) ← (op2) [1 ≤ op2 ≤ 4] Operation Disable interrupts and Class A traps Data_Segment = (op1) AND SFR_range = Extended DO WHILE ((count) ≠...
  • Page 73 C166 Family Instruction Set 30Mar98@15:00h Instruction Description IDLE IDLE Enter Idle Mode Syntax IDLE Operation Enter Idle Mode Description This instruction causes the part to enter the idle mode. In this mode, the CPU is powered down while the peripherals remain running. It remains powered down until a peripheral interrupt or external interrupt occurs.
  • Page 74 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Relative Jump if Bit Set Syntax op1, op2 Operation IF (op1) = 1 THEN (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types Description If the bit specified by op1 is set, program execution continues at the loca- tion of the instruction pointer, IP, plus the specified displacement, op2.
  • Page 75 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Relative Jump if Bit Set and Clear Bit Syntax op1, op2 Operation IF (op1) = 1 THEN (op1) = 0 (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types Description If the bit specified by op1 is set, program execution continues at the loca- tion of the instruction pointer, IP, plus the specified displacement, op2.
  • Page 76 C166 Family Instruction Set 30Mar98@15:00h Instruction Description JMPA JMPA Absolute Conditional Jump Syntax JMPA op1, op2 Operation IF (op1) = 1 THEN (IP) ← op2 ELSE Next Instruction END IF Description If the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken.
  • Page 77 C166 Family Instruction Set 30Mar98@15:00h Instruction Description JMPI JMPI Indirect Conditional Jump Syntax JMPI op1, op2 Operation IF (op1) = 1 THEN (IP) ← op2 ELSE Next Instruction END IF Description If the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken.
  • Page 78 C166 Family Instruction Set 30Mar98@15:00h Instruction Description JMPR JMPR Relative Conditional Jump Syntax JMPR op1, op2 Operation IF (op1) = 1 THEN (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Description If the condition specified by op1 is met, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2.
  • Page 79 C166 Family Instruction Set 30Mar98@15:00h Instruction Description JMPS JMPS Absolute Inter-Segment Jump Syntax JMPS op1, op2 (CSP) ← op1 Operation (IP) ← op2 Description Branches unconditionally to the absolute address specified by op2 within the segment specified by op1. Condition Flags E Not affected.
  • Page 80 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Relative Jump if Bit Clear Syntax op1, op2 Operation IF (op1) = 0 THEN (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types Description If the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2.
  • Page 81 C166 Family Instruction Set 30Mar98@15:00h Instruction Description JNBS JNBS Relative Jump if Bit Clear and Set Bit Syntax JNBS op1, op2 Operation IF (op1) = 0 THEN (op1) = 1 (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types Description If the bit specified by op1 is clear, program execution continues at the...
  • Page 82 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Move Data Syntax op1, op2 (op1) ← (op2) Operation Data Types WORD Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly.
  • Page 83 C166 Family Instruction Set 30Mar98@15:00h Instruction Description MOVB MOVB Move Data Syntax MOVB op1, op2 (op1) ← (op2) Operation Data Types BYTE Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly.
  • Page 84 C166 Family Instruction Set 30Mar98@15:00h Instruction Description MOVBS MOVBS Move Byte Sign Extend Syntax MOVBS op1, op2 (low byte op1) ← (op2) Operation IF (op2 ) = 1 THEN (high byte op1) ← FF ELSE (high byte op1) ← 00 END IF Data Types WORD, BYTE...
  • Page 85 C166 Family Instruction Set 30Mar98@15:00h Instruction Description MOVBZ MOVBZ Move Byte Zero Extend Syntax MOVBZ op1, op2 (low byte op1) ← (op2) Operation (high byte op1) ← 00 Data Types WORD, BYTE Description Moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1.
  • Page 86 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Signed Multiplication Syntax op1, op2 (MD) ← (op1) * (op2) Operation Data Types WORD Description Performs a 16-bit by 16-bit signed multiplication using the two words specified by operands op1 and op2 respectively. The signed 32-bit result is placed in the MD register.
  • Page 87 C166 Family Instruction Set 30Mar98@15:00h Instruction Description MULU MULU Unsigned Multiplication Syntax MULU op1, op2 (MD) ← (op1) * (op2) Operation Data Types WORD Description Performs a 16-bit by 16-bit unsigned multiplication using the two words specified by operands op1 and op2 respectively. The unsigned 32-bit result is placed in the MD register.
  • Page 88 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Integer Two’s Complement Syntax (op1) ← 0 - (op1) Operation Data Types WORD Description Performs a binary 2’s complement of the source operand specified by op1. The result is then stored in op1. Condition Flags E Set if the value of op1 represents the lowest possible negative number.
  • Page 89 C166 Family Instruction Set 30Mar98@15:00h Instruction Description NEGB NEGB Integer Two’s Complement Syntax NEGB (op1) ← 0 - (op1) Operation Data Types BYTE Description Performs a binary 2’s complement of the source operand specified by op1. The result is then stored in op1. Condition Flags E Set if the value of op1 represents the lowest possible negative number.
  • Page 90 C166 Family Instruction Set 30Mar98@15:00h Instruction Description No Operation Syntax Operation No Operation Description This instruction causes a null operation to be performed. A null operation causes no change in the status of the flags. Condition Flags E Not affected. Z Not affected.
  • Page 91 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Logical OR Syntax op1, op2 (op1) ← (op1) ∨ (op2) Operation Data Types WORD Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags E Set if the value of op2 represents the lowest possible negative number.
  • Page 92 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Logical OR Syntax op1, op2 (op1) ← (op1) ∨ (op2) Operation Data Types BYTE Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags E Set if the value of op2 represents the lowest possible negative number.
  • Page 93 C166 Family Instruction Set 30Mar98@15:00h Instruction Description PCALL PCALL Push Word and Call Subroutine Absolute Syntax PCALL op1, op2 (tmp) ← (op1) Operation (SP) ← (SP) - 2 ((SP)) ← (tmp) (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← op2 Data Types WORD Description...
  • Page 94 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Pop Word from System Stack Syntax (tmp) ← ((SP)) Operation (SP) ← (SP) + 2 (op1) ← (tmp) Data Types WORD Description Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1.
  • Page 95 C166 Family Instruction Set 30Mar98@15:00h Instruction Description PRIOR PRIOR Prioritize Register Syntax PRIOR op1, op2 (tmp) ← (op2) Operation (count) ← 0 ) ≠ 1 AND (count) ≠ 15 AND (op2) ≠ 0 DO WHILE (tmp ) ← (tmp (tmp (count) ←...
  • Page 96 C166 Family Instruction Set 30Mar98@15:00h Instruction Description PUSH PUSH Push Word on System Stack Syntax PUSH (tmp) ← (op1) Operation (SP) ← (SP) - 2 ((SP)) ← (tmp) Data Types WORD Description Moves the word specified by operand op1 to the location in the internal system stack specified by the Stack Pointer, after the Stack Pointer has been decremented by two.
  • Page 97 C166 Family Instruction Set 30Mar98@15:00h Instruction Description PWRDN PWRDN Enter Power Down Mode Syntax PWRDN Operation Enter Power Down Mode Description This instruction causes the part to enter the power down mode. In this mode, all peripherals and the CPU are powered down until the part is externally reset.
  • Page 98 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Return from Subroutine Syntax (IP) ← ((SP)) Operation (SP) ← (SP) + 2 Description Returns from a subroutine. The IP is popped from the system stack. Exe- cution resumes at the instruction following the CALL instruction in the call- ing routine.
  • Page 99 C166 Family Instruction Set 30Mar98@15:00h Instruction Description RETI RETI Return from Interrupt Routine Syntax RETI (IP) ← ((SP)) Operation (SP) ← (SP) + 2 IF (SYSCON.SGTDIS=0) THEN (CSP) ← ((SP)) (SP) ← (SP) + 2 END IF (PSW) ← ((SP)) (SP) ←...
  • Page 100 C166 Family Instruction Set 30Mar98@15:00h Instruction Description RETP RETP Return from Subroutine and Pop Word Syntax RETP (IP) ← ((SP)) Operation (SP) ← (SP) + 2 (tmp) ← ((SP)) (SP) ← (SP) + 2 (op1) ← (tmp) Data Types WORD Description Returns from a subroutine.
  • Page 101 C166 Family Instruction Set 30Mar98@15:00h Instruction Description RETS RETS Return from Inter-Segment Subroutine Syntax RETS (IP) ← ((SP)) Operation (SP) ← (SP) + 2 (CSP) ← ((SP)) (SP) ← (SP) + 2 Description Returns from an inter-segment subroutine. The IP and CSP are popped from the system stack.
  • Page 102 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Rotate Left Syntax op1, op2 (count) ← (op2) Operation (C) ← 0 DO WHILE (count) ≠ 0 (C) ← (op1 ) ← (op1 (op1 ) [n=1...15] ) ← (C) (op1 (count) ← (count) - 1 END WHILE Data Types WORD...
  • Page 103 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Rotate Right Syntax op1, op2 (count) ← (op2) Operation (C) ← 0 (V) ← 0 DO WHILE (count) ≠ 0 (V) ← (V) ∨ (C) (C) ← (op1 ) ← (op1 (op1 ) [n=0...14] ) ←...
  • Page 104 C166 Family Instruction Set 30Mar98@15:00h Instruction Description SCXT SCXT Switch Context Syntax SCXT op1, op2 (tmp1) ← (op1) Operation (tmp2) ← (op2) (SP) ← (SP) - 2 ((SP)) ← (tmp1) (op1) ← (tmp2) Data Types WORD Description Used to switch contexts for any register. Switching context is a push and load operation.
  • Page 105 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Shift Left Syntax op1, op2 (count) ← (op2) Operation (C) ← 0 DO WHILE (count) ≠ 0 (C) ← (op1 ) ← (op1 (op1 ) [n=1...15] ) ← 0 (op1 (count) ← (count) - 1 END WHILE Data Types WORD...
  • Page 106 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Shift Right Syntax op1, op2 (count) ← (op2) Operation (C) ← 0 (V) ← 0 DO WHILE (count) ≠ 0 (V) ← (C) ∨ (V) (C) ← (op1 ) ← (op1 (op1 ) [n=0...14] ) ←...
  • Page 107 C166 Family Instruction Set 30Mar98@15:00h Instruction Description SRST SRST Software Reset Syntax SRST Operation Software Reset Description This instruction is used to perform a software reset. A software reset has the same effect on the microcontroller as an externally applied hardware reset.
  • Page 108 C166 Family Instruction Set 30Mar98@15:00h Instruction Description SRVWDT SRVWDT Service Watchdog Timer Syntax SRVWDT Operation Service Watchdog Timer Description This instruction services the Watchdog Timer. It reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence.
  • Page 109 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Integer Subtraction Syntax op1, op2 (op1) ← (op1) - (op2) Operation Data Types WORD Description Performs a 2’s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. The result is then stored in op1.
  • Page 110 C166 Family Instruction Set 30Mar98@15:00h Instruction Description SUBB SUBB Integer Subtraction Syntax SUBB op1, op2 (op1) ← (op1) - (op2) Operation Data Types BYTE Description Performs a 2’s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. The result is then stored in op1.
  • Page 111 C166 Family Instruction Set 30Mar98@15:00h Instruction Description SUBC SUBC Integer Subtraction with Carry Syntax SUBC op1, op2 (op1) ← (op1) - (op2) - (C) Operation Data Types WORD Description Performs a 2’s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destina- tion operand specified by op1.
  • Page 112 C166 Family Instruction Set 30Mar98@15:00h Instruction Description SUBCB SUBCB Integer Subtraction with Carry Syntax SUBCB op1, op2 (op1) ← (op1) - (op2) - (C) Operation Data Types BYTE Description Performs a 2’s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destina- tion operand specified by op1.
  • Page 113 C166 Family Instruction Set 30Mar98@15:00h Instruction Description TRAP TRAP Software Trap Syntax TRAP (SP) ← (SP) - 2 Operation ((SP)) ← (PSW) IF (SYSCON.SGTDIS=0) THEN (SP) ← (SP) - 2 ((SP)) ← (CSP) (CSP) ← 0 END IF (SP) ← (SP) - 2 ((SP)) ←...
  • Page 114 C166 Family Instruction Set 30Mar98@15:00h Instruction Description Logical Exclusive OR Syntax op1, op2 (op1) ← (op1) ⊕ (op2) Operation Data Types WORD Description Performs a bitwise logical EXCLUSIVE OR of the source operand speci- fied by op2 and the destination operand specified by op1. The result is then stored in op1.
  • Page 115 C166 Family Instruction Set 30Mar98@15:00h Instruction Description XORB XORB Logical Exclusive OR Syntax XORB op1, op2 (op1) ← (op1) ⊕ (op2) Operation Data Types BYTE Description Performs a bitwise logical EXCLUSIVE OR of the source operand speci- fied by op2 and the destination operand specified by op1. The result is then stored in op1.
  • Page 116: Addressing Modes

    Addressing Modes Addressing Modes The Siemens 16-bit microcontrollers provide a lot of powerful addressing modes for access to word, byte and bit data (short, long, indirect), or to specify the target address of a branch instruction (absolute, relative, indirect). The different addressing modes use different formats and cover different scopes.
  • Page 117 C166 Family Instruction Set 30Mar98@15:00h Addressing Modes Rw, Rb: Specifies direct access to any GPR in the currently active context (register bank). Both ’Rw’ and ’Rb’ require four bits in the instruction format. The base address of the current register bank is determined by the content of register CP. ’Rw’ specifies a 4-bit word GPR address relative to the base address (CP), while ’Rb’...
  • Page 118 C166 Family Instruction Set 30Mar98@15:00h Addressing Modes Long Addressing Mode This addressing mode uses one of the four DPP registers to specify a physical 18-bit or 24-bit address. Any word or byte data within the entire address space can be accessed with this mode. The C167/5 devices also support an override mechanism for the DPP adressing scheme.
  • Page 119 C166 Family Instruction Set 30Mar98@15:00h Addressing Modes DPP Override Mechansim in the C167/5 Other than the older devices from the SAB 80C166 group the C167 and C165 devices provide an override mechanism that allows to bypass the DPP addressing scheme temporarily. The EXTP(R) and EXTS(R) instructions override this addressing mechanism.
  • Page 120 C166 Family Instruction Set 30Mar98@15:00h Addressing Modes Note: Word accesses on odd byte addresses are not executed, but rather trigger a hardware trap. After reset, the DPP registers are initialized in a way that all indirect long addresses are directly mapped onto the identical physical addresses. Physical addresses are generated from indirect address pointers via the following algorithm: Calculate the physical address of the word GPR, which is used as indirect address pointer, using the specified short address (’Rw’) and the current register bank base address (CP).
  • Page 121 C166 Family Instruction Set 30Mar98@15:00h Addressing Modes Constants The C166 Family instruction set also supports the use of wordwide or bytewide immediate constants. For an optimum utilization of the available code storage, these constants are represented in the instruction formats by either 3, 4, 8 or 16 bits. Thus, short constants are always zero-extended while long constants are truncated if necessary to match the data format required for the particular operation (see table below): Mnemonic...
  • Page 122 C166 Family Instruction Set 30Mar98@15:00h Addressing Modes caddr: Specifies an absolute 16-bit code address within the current segment. Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit of ’caddr’ must always contain a ’0’, otherwise a hardware trap would occur. rel: This mnemonic represents an 8-bit signed word offset address relative to the current Instruction Pointer contents, which points to the instruction after the branch instruction.
  • Page 123: Instruction State Times

    C166 Family Instruction Set 30Mar98@15:00h Instruction State Times Instruction State Times Basically, the time to execute an instruction depends on where the instruction is fetched from, and where possible operands are read from or written to. The fastest processing mode is to execute a program fetched from the internal ROM.
  • Page 124 C166 Family Instruction Set 30Mar98@15:00h Instruction State Times The total time ( T tot ), which a particular part of a program takes to be processed, can be calculated by the sum of the single instruction processing times ( T In ) of the considered instructions plus an offset value of 6 state times which considers the solitary filling of the pipeline, as follows: T tot T I1 + T I2 + ...
  • Page 125 C166 Family Instruction Set 30Mar98@15:00h Instruction State Times Instructions executed from the internal RAM require the same minimum time as if being fetched from the internal ROM plus an instruction-length dependent number of state times, as follows: For 2-byte instructions: T Imin (RAM) = T Imin (ROM) + 4 States For 4-byte instructions:...
  • Page 126 C166 Family Instruction Set 30Mar98@15:00h Instruction State Times • Internal SFR operand reads: T Iadd = 0, 1 State or 2 States Mostly, SFR read accesses do NOT require additional processing time. In some rare cases, however, either one or two additional state times will be caused by particular SFR operations, as follows: –...
  • Page 127 C166 Family Instruction Set 30Mar98@15:00h Instruction State Times • Jumps into the internal ROM space: T Iadd = 0 or 2 States The minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2 additional state times, if the branch target instruction is a double word instruction at a non- aligned double word location (xxx2 , xxx6...