Related Manuals for Fujitsu CPU369-Module
Summary of Contents for Fujitsu CPU369-Module
- Page 1 CPU369-Module Documentation © Fujitsu Microelectronics Europe GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag, Germany...
- Page 2 History Revision Date Comment V1.0 08.03.01 New Document V1.1 17.10.03 Modifications for F369 module V1.2 14.11.03 Some corrections...
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Page 3: No Liability For Consequential Damages
However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH. - Page 4 This Starterkit contains an evaluation board, documentation and software on a CD-ROM. For documentation or software updates, please refer to our technical web-site http://www.fme.gsdc.de/gsdc.htm or to our Fujitsu home pagee http://www.fme.fujitsu.com Fujitsu reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice.
- Page 5 1. Introduction The Fujitsu CPU369-Modul is a low cost multifunctional evaluation board for Fujitsu’s 32-Bit Flash microcontroller MB91F369 that makes it easy to evaluate and demonstrate almost all features of the microcontroller. It can be used stand alone for software development and testing as a simple target board. It gives you the possibility to develop and evaluate applications with devices of the new embedded-graphic- controller family.
- Page 6 3. Jumpers and Switches This chapter describes all jumpers and switches which can be modified on the evaluation board. The default setting is shown with a gray shaded area. All jumpers and switches are named directly on the board by its meaning, so it is very easy to set the jumpers according to the features.
- Page 7 3.2 Operating Mode (SW2) DIP switch Logical value Description setting 0 (low) Boot signal (SW2/1) Boot signal 0 (low) MD2 (SW2/2) 0 (low) Internal ROM mode MD1 (SW2/3) 0 (low) MD0 (SW2/4) 3.3 UART (JP21, JP22) Jumper setting Description ON (closed) UART0 Output enable SOT_0 (JP21)
- Page 8 3.5 Hardware Standby (JP16) Jumper setting Description HSTX request is released HSTX (JP16) 3.6 Clock Select (JP17, JP18, JP19, JP20) Jumper setting Description Clock enable SELCLK (JP17) Clock disable Jumper setting Description 4MHz clock enable 4MHz clock (JP18) 4MHz clock disable Jumper setting Description 32kHz clock enable...
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Page 9: Important Note
Header for Debug Signals Power supply voltage (JP1, JP2, JP3, JP4, JP5, JP6) • - 12V – GND • - 5V – GND • - 3.3V – GND • - 2.5_1V – GND • - 2.5_2V – GND separated voltage •... - Page 10 3.9 Pin Assignment of Peripheral Jumpers Peripheral_1 Pin MB91F369 Pin Peripheral_2 Pin MB91F369 Pin 2 PH0 2 PM0 3 PH1 3 PM1 4 PH2 4 PN0 SOT4 5 PH3 5 PN1 SIN4 6 PH4 6 PN2 SCK4 7 PH5 7 PN3 SIN3 8 PH6 8 PN4...
- Page 11 4. Connectors 4.1 Serial Interface Connector P1 The following diagram shows the connection of the 9-pin D-Sub female connector P1 which is used for the serial interfaces. GND DTR RXD TXD TXD is the transmit output, RXD is the receive input. The DTR signal is used as an input ,which can be connected to generate a reset.
- Page 12 5. Schematics and Drawings...