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Technology instructions
9.1 High-speed counter
Table 9- 9
HSC counter mode
HSC 1
HSC 2
HSC 3
HSC 4
HSC 5
HSC 6
Table 9- 10
HSC
HSC 1
HSC 2
HSC 5
HSC 6
1
416
CPU 1214C, CPU 1215C, and CPU1217C:
HSC default address assignments
(on-board inputs only, see next table for optional SB addresses)
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
Optional SB in CPUs in above table: HSC default address assignments
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
An SB with only 2 digital inputs provides only the 4.0 and 4.1 inputs.
Digital input byte 0
(default: 0.x)
0
1
2
3
4
C
[d]
[R]
CU CD
[R]
A
B
[R]
[R]
C
[d]
[R] CU CD
[R]
A
B
C
CU CD
A
Digital input byte 1
(default: 1.x)
5
6
7
0
1
[d]
[R]
[R]
B
[R]
[R]
C
[d]
[R] CU CD
[R]
A
B
C
[d]
CU CD [R]
A
B
Optional SB inputs (default: 4.x)
0
1
C
[d]
CU
CD
A
B
[R]
[R]
[R]
C
[d]
CU
CD
A
B
[R]
[R]
[R]
S7-1200 Programmable controller
System Manual, 03/2014, A5E02486680-AG
2
3
4
5
[R]
[R]
C
[d]
[R]
CU CD [R]
A
B
[R]
1
2
3
[R]
[R]
[R]
C
[d]
CU
CD
A
B
[R]
[R]
[R]
C
[d]
CU
CD
A
B
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