Siemens S7-1200 System Manual page 414
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- Operating instructions manual (132 pages) ,
- Programming manualline (74 pages) ,
- Manual (46 pages)
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Technology instructions
9.1 High-speed counter
Input addresses for the HSC
When you configure the CPU, you have the option to enable and configure the "Hardware
inputs" for each HSC.
All HSC inputs must be connected to terminals on the CPU module or optional signal board
that plugs into the front of the CPU module.
Note
As shown in the following tables, the default assignments for the optional signals for the
different HSCs overlap. For example, the optional external reset for HSC 1 uses the same
input as one of the inputs for HSC 2. For
For V4 CPUs or later, you can reassign the HSC inputs during the CPU configuration. You
do not have to use the default input assignments.
Always ensure that you have configured your HSCs so that any one input is not being used
by two HSCs.
The following tables show the HSC input default assignments for the on-board I/O of CPUs
and an optional SB. (If the SB model selected has only 2 inputs, only 4.0 and 4.1 inputs are
available.)
HSC input table definitions
● Single-phase: C is Clock input, [d] is direction input (optional), and [R] is external reset
input (optional)
● Two-phase: CU is Clock Up input, CD is Clock Down input, and [R] is external reset
input.(optional)
(Reset is available only for "Counting" mode.)
● AB-phase quadrature: A is the Clock A input, B is the Clock B input, and [R] is external
reset input (optional). (Reset is available only for "Counting" mode.)
Table 9- 7
HSC
counter mode
HSC 1
HSC 2
HSC 3
HSC4
414
(Reset is available only for "Counting" mode.)
CPU 1211C: HSC default address assignments
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
AB-phase
1-phase
2-phase
CPU on-board input
(default 0.x)
0
1
2
3
C
[d]
[R]
CU
CD
[R]
A
B
[R]
[R]
C
[d]
[R]
CU
CD
[R]
A
B
Optional SB input (default
4.x)
1
4
5
0
1
C
[d]
CU
CD
A
B
[R]
[R]
[R]
C
[d]
C
[d]
C
[d]
C
[d]
CU
CD
S7-1200 Programmable controller
System Manual, 03/2014, A5E02486680-AG
2
3
[R]
[R]
[R]
C
[d]
CU
CD
A
B
R]
R]
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