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Samsung S3F84B8 User Manual

8-bit cmos
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S3F84B8
8-bit CMOS Microcontrollers
Revision 1.00
June 2010
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 2010 Samsung Electronics Co., Ltd. All rights reserved.
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  • Page 1 S3F84B8 8-bit CMOS Microcontrollers Revision 1.00 June 2010  2010 Samsung Electronics Co., Ltd. All rights reserved.
  • Page 2 Samsung products are not designed, intended, or use of the information contained herein. authorized for use as components in systems intended Samsung reserves the right to make changes in its for surgical implant into the body, for other products or product specifications with the intent to...
  • Page 3 Revision History Revision No. Date Description Author(s) 0.00 Sep. 9, 2009  Initial draft Wei Ningning 1.00 April. 30, 2010  Released version Wei Ningning...
  • Page 4 Table of Contents OVERVIEW OF S3F84B8 MICROCONTROLLER ........1-1 1.1 S3C8-Series Microcontrollers ........................1-1 1.1.1 S3F84B8 Microcontroller ........................1-1 1.1.2 Key Features of S3F84B8 ........................ 1-2 1.1.3 Block Diagram of S3F84B8 ......................1-5 1.1.4 Pin Assignments ..........................1-6 1.1.5 Pin Descriptions..........................1-7 1.1.6 Pin Circuits............................
  • Page 5 4.1 Overview of Control Registers ......................... 4-1 4.1.1 ADCON — A/D Converter Control Register: FAH, BANK0 .............. 4-5 4.1.2 AMTDATA — Anti-mis-trigger Data Register: F6H, BANK0............. 4-6 4.1.3 BTCON — Basic Timer Control Register: D3H, BANK0 ..............4-6 4.1.4 BUZCON — BUZ Control Register: F7H, BANK0................4-7 4.1.5 CLKCON —...
  • Page 6 5.1.5 S3F84B8 Interrupt Structure......................5-3 5.1.5.1 Interrupt Vector Addresses ..................... 5-4 5.1.5.2 Enable/Disable Interrupt Instructions (EI, DI)................5-4 5.1.6 System-Level Interrupt Control Registers ..................5-5 5.1.7 Interrupt Processing Control Points....................5-6 5.1.8 Peripheral Interrupt Control Registers ....................5-7 5.1.9 System Mode Register (SYM) ......................5-8 5.1.10 Interrupt Mask Register (IMR) ......................
  • Page 7 6.3.17 CP — Compare ..........................6-29 6.3.18 CPIJE — Compare, Increment, and Jump on Equal..............6-30 6.3.19 CPIJNE — Compare, Increment, and Jump on Non-Equal ............6-31 6.3.20 DA — Decimal Adjust ........................6-32 6.3.21 DA — Decimal Adjust (Continued) ....................6-33 6.3.22 DEC —...
  • Page 8 6.3.70 TCM — Test Complement Under Mask ..................6-82 6.3.71 TM — Test Under Mask ....................... 6-83 6.3.72 WFI — Wait for Interrupt....................... 6-84 6.3.73 XOR — Logical Exclusive OR ...................... 6-85 CLOCK CIRCUIT ..................7-1 7.1 Overview of Clock Circuit......................... 7-1 7.1.1 Clock Status During Power-Down Modes ..................
  • Page 9 12.1.2.2 Timer 0 Control Register (TCCON)..................12-2 12.1.3 Block Diagram of Timer 0 ......................12-4 12.2 Two 8-bit Timers Mode (Timer C and D) ..................... 12-5 12.2.1 Overview of Two 8-bit Timers Mode (Timer C and D)..............12-5 12.2.2 Timer C and D Control Register (TCCON, TDCON) ..............12-5 12.2.3 Functional Description of Two 8-bit Timers Mode (Timer C and D) ..........
  • Page 10 19 EMBEDDED FLASH MEMORY INTERFACE ...........19-1 19.1 Overview of Embedded Flash Memory Interface................. 19-1 19.1.1 Flash ROM Configuration ......................19-1 19.1.2 Key Features of Embedded Flash Memory Interface..............19-1 19.1.3 User Program Mode ........................19-2 19.1.4 Smart Option..........................19-2 19.1.5 Flash Memory Control Registers (User Program Mode) .............. 19-3 19.1.5.1 Flash Memory Control Register (FMCOn) ................
  • Page 11 Program Memory Address Space..................... 2-2 Figure 2-2 Smart Option............................. 2-3 Figure 2-3 Internal Register File Organization in S3F84B8 ................2-5 Figure 2-4 Register Page Pointer (PP) ......................2-6 Figure 2-5 Set 1, Set 2, Prime Area Register Map .................... 2-8 Figure 2-6 8 Byte Working Register Areas (Slices) ...................
  • Page 12 Low Voltage Reset Circuit ........................ 8-2 Figure 8-2 Reset Block Diagram ........................8-3 Figure 8-3 Timing for S3F84B8 after RESET..................... 8-3 Figure 9-1 Port 0 Control Register High Byte (P0CONH) .................. 9-3 Figure 9-2 Port 0 Control Register Low Byte (P0CONL) ................... 9-4 Figure 9-3 Port 0 Interrupt Control Register (P0INT) ..................
  • Page 13 Figure 13-1 A/D Converter Control Register (ADCON) ................... 13-2 Figure 13-2 A/D Converter Circuit Diagram ..................... 13-3 Figure 13-3 A/D Converter Data Register (ADDATAH/L) ................13-3 Figure 13-4 A/D Converter Timing Diagram..................... 13-4 Figure 13-5 Recommended A/D Converter Circuit for Highest Absolute Accuracy......... 13-5 CMP0 Control Register (CMP0CON) ...................
  • Page 14 TB84B8 Target Board Configuration .................... 22-3 Figure 22-3 DIP Switch for Smart Option......................22-6 Figure 22-4 40-Pin Connector for TB84B8....................... 22-7 Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package ................22-7 20-DIP-300A Package Dimensions ....................23-1 Figure 23-1 Figure 23-2 20-SOP-375 Package Dimensions....................23-2...
  • Page 15 Table 6-5 Opcode Quick Reference........................6-9 Table 6-6 Condition Codes ..........................6-11 Table 8-1 S3F84B8 Set1 Registers Values after RESET .................. 8-6 Table 8-2 System and Peripheral Control Registers Set1 Bank1 ..............8-8 Table 9-1 S3F84B8 Port Configuration Overview....................9-1 Table 9-2 Port Data Register Summary ......................
  • Page 16 Table 22-1 TB84B8 Components........................22-4 Table 22-2 Power Selection Settings for TB84B8.................... 22-4 Table 22-3 Using Single Header Pins to Select Clock Source and Enable/Disable PWM ......22-5...
  • Page 17 List of Examples Example Title Page Number Number Example 2-1 Setting the Register Pointers ...................... 2-10 Example 2-2 Using the RPs to Calculate the Sum of a Series of Registers............ 2-11 Example 2-3 Addressing the Common Working Register Area ............... 2-14 Example 2-4 Standard Stack Operations Using PUSH and POP..............

  • Page 18: Overview Of S3F84B8 Microcontroller

    High current LED drive I/O ports (High current output: Typical 12 mA) The S3F84B8 microcontroller is ideal for use in a wide range of home applications requiring simple timer/counter, ADC, and so on. They are currently available in 20-pin SOP/DIP package.

  • Page 19: Key Features Of S3F84B8

    S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1.1.2 KEY FEATURES OF S3F84B8 The key features of S3F84B8 include:  SAM8RC CPU core Memory  8K-byte internal multi-time program memory Full-Flash  Sector size: 128 Bytes  10 Years data retention ...
  • Page 20 S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 10-bit IH PWM  10-bit IH specific PWM 1-channel  Cooperate with CMPs  Anti-mis-trigger function  Delay trigger function Comparators  4 integrated comparators A/D Converter  8 analog input pins (MAX) ...
  • Page 21 S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER Built-in RESET Circuit (LVR)  Low-voltage check to reset system  = 1.9/2.3/3.0/3.6/3.9V (by smart option) Operating Temperature Range  – 40C to + 85C Operating Voltage Range  1.8V to 5.5V @ 0.4 – 2MHz ...

  • Page 22: Block Diagram Of S3F84B8

    S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1.1.3 BLOCK DIAGRAM OF S3F84B8 shows the block diagram of S3F84B8. Figure 1-1 ( ADC0-7) P0.0-0.6 Port 0 (INT0-INT5) OSC/nRESET P0.2/ nRESET I/ O Port and Interrupt Control 8-Bit Port 1 P1.0-1.2 Basic Timer...

  • Page 23: Pin Assignments

    S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1.1.4 PIN ASSIGNMENTS shows the pin assignments (20-DIP, 20-SOP) in S3F84B8. Figure 1-2 INT0/X /P0.0 P2.7/ADC7/(SCL) INT1/X /P0.1 P2.6/ADC6/(SDA) /nRESET/P0.2 P2.5/ADC5/CMP3_N BUZ/INT2/P0.3 P2.4/ADC4/CMP2_N S3F84B8 PWM/INT3/P0.4 P2.3/ADC3(OPA_O) 20-DIP/ 20-SOP INT4/P0.5 P2.2/ADC2/OPA_N TAOUT/INT5/P0.6 P2.1/ADC1/OPA_P TACK/CMP0_P/P1.0 P2.0/ADC0/TDOUT...

  • Page 24: Pin Descriptions

    S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1.1.5 PIN DESCRIPTIONS shows the pin descriptions (20-DIP/20-SOP) in S3F84B8. Table 1-1 Table 1-1 Pin Descriptions (20-DIP/20-SOP) in S3F84B8 Pin Name Pin Description Circuit Pin No. Shared Type Type Pins INT0-INT5 External interrupts P0.0-P0.6...

  • Page 25: Table 1-2 Pin Descriptions Used To Read/Write The Flash Rom

    S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER shows the pin descriptions used to Read/Write the Flash ROM in S3F84B8. Table 1-2 Table 1-2 Pin Descriptions used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin No. Function P2.6...

  • Page 26: Pin Circuits

    S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1.1.6 PIN CIRCUITS shows the pin circuit type 1 in S3F84B8. Figure 1-3 P-Channel Data N-Channel Output Disable Figure 1-3 Pin Circuit Type 1 shows the pin circuit type 2 in S3F84B8. Figure 1-4...

  • Page 27: Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)

    S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER shows the pin circuit type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7) in S3F84B8. Figure 1-5 Pull-up enable Data Pin Circuit Type 1 Output Disable (Input Mode) Digital Input Analog Input Enable Analog Input Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)
  • Page 28 S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER shows the Pin Circuit Type 1-2 (P2.3) in S3F84B8. Figure 1-6 Pull-up enable Data Pin Type 1 Output Disable (Input Mode) Digital Input Analog Input Enable Analog Input OPA output OPA Enable Bit Figure 1-6 Pin Circuit Type 1-2 (P2.3)
  • Page 29 S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER shows the Pin Circuit Type 1-3 (P0.3, P0.4, P0.6) in S3F84B8. Figure 1-7 Pull-up register (50 kohm typical) Pull-up Enable Data Pin Circuit Type 1 Output Disable Pin config bits Input Noise Ext.INT...
  • Page 30 1 OVERVIEW OF S3F84B8 MICROCONTROLLER shows the Pin Circuit Type 3 (P0.2) in S3F84B8. Figure 1-9 Figure 1-9 Pin Circuit Type 3 (P0.2) shows the Pin Circuit Type 2-2 (P0.0, P0.1) in S3F84B8. Figure 1-10 Pull-up register (50 kohm typical) Pull-up...

  • Page 31: Address Spaces

    CPU and internal register file. The S3F84B8 microcontroller contains 8Kbytes of on-chip program memory configured as Internal ROM. It also contains 272 general-purpose registers in the internal register file, where 59 bytes are mapped for system and...

  • Page 32: Internal Program Memory (Rom)

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2.2 INTERNAL PROGRAM MEMORY (ROM) The internal program memory (ROM) stores program codes or table data. The S3F84B8 microcontroller contains 8Kbytes of internal multi-time programmable (MTP) program memory (see Figure 2-1). The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (except 3CH, 3DH, 3EH, 3FH) in this address range can be used as normal program memory.

  • Page 33: Smart Option

    , you can’t change them to Normal I/O after reset operation. Figure 2-2 Smart Option For Start condition of the chip, Smart option specifies the ROM option. The ROM address used by Smart option is from 003EH to 003FH. Note that 003CH and 003DH are not used in S3F84B8.

  • Page 34: Register Architecture

    0 and bank 1, while the lower 32 byte area specifies a single 32 byte common area. In case of S3F84B8, the total number of addressable 8-bit registers is 336. Of these 336 registers, 15 bytes are meant for the CPU and system control registers, 49 bytes are meant for peripheral control and data registers, 16 bytes are meant for shared working registers.

  • Page 35: Figure 2-3 Internal Register File Organization In S3F84B8

    (Register Addressing Mode) Data Registers Bytes (Indirect Register, Indexed System Registers Mode, and Stack (Register Addressing Mode) Operations) General Purpose Register (Register Addressing Mode) Bytes Page 0 Prime Data Registers Bytes (All Addressing Modes) Figure 2-3 Internal Register File Organization in S3F84B8...

  • Page 36: Register Page Pointer (Pp)

    Register Page Pointer (PP) DFH, Set 1, R/W Source register page selection bits : Not used for the S3F84B8 Destination register page selection bits : Not used for the S3F84B8 NOTE: A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer.

  • Page 37: Register Set 1

    The same 64 byte physical space that is used for set 1 location C0H–FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For S3F84B8, the set 2 address range (C0H–FFH) is accessible on page 0 only.

  • Page 38: Prime Register Space

    2.3.1.3 Prime Register Space The lower 192 bytes (00H–BFH) of 256 byte register page 0 in S3F84B8 is called prime register area. Prime registers can be accessed by using any of the seven addressing modes (see Chapter 3, “Addressing Modes”).

  • Page 39: Working Registers

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2.3.1.4 Working Registers Instructions can access specific 8-bit registers or 16-bit register pairs using 4-bit or 8-bit address fields. When 4-bit working register addressing is used, consider the 256 byte register file as the one that consists of 32 8-byte register groups or “slices.”...

  • Page 40: Using The Register Points (Rp)

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2.3.2 USING THE REGISTER POINTS (RP) Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8 byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

  • Page 41: Figure 2-8 Non-Contiguous 16 Byte Working Register Block

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES F7H (R7) 8-Byte Slice F0H (R0) 16-Byte Register File Contiguous Contains 32 1 1 1 1 0 X X X working 8-Byte Slices Register block 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R0) Figure 2-8...

  • Page 42: Register Addressing

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2.4 REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing and takes full advantage of shorter instruction formats to reduce the execution time. In Register (R) addressing mode, the operand value specifies the content of a specific register or register pair. Here, you can access any location in the register file, except for set 2.
  • Page 43 24 8-byte "slices" of the register file Registers (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). In the S3F84B8 microcontroller, NOTE: page 0-1 are implemented. Page 0 Page 0...

  • Page 44: Common Working Register Area (C0H–Cfh)

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2.4.1 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8 byte register slices in set 1 (locations C0H–CFH) as the active 16 byte working register block. RP0 　 C0H–C7H RP1 　...

  • Page 45: Bit Working Register Addressing

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2.4.2 4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space. The address information stored in a register pointer serves as an addressing “window” that makes it possible for instructions to access working registers efficiently using short 4-bit addresses.

  • Page 46: Figure 2-13 4-Bit Working Register Addressing Example

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 Selects RP0 OPCODE Register Instruction address 0 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 'INC R6' (76H) Figure 2-13...

  • Page 47: Bit Working Register Addressing

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2.4.3 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value “1100B.”...

  • Page 48: Figure 2-15 8-Bit Working Register Addressing Example

    S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 8-bit address Register form instruction 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1 address 'LD R11, R2'...

  • Page 49: System And User Stack

    SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Since only internal memory space is implemented in S3F84B8, the SPL must be initialized to an 8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary.
  • Page 50 S3F84B8_UM_REV 1.00 2 ADDRESS SPACES Example 2-4 Standard Stack Operations Using PUSH and POP Following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions. ; SPL  FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...

  • Page 51: Addressing Modes

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES ADDRESSING MODES 3.1 OVERVIEW OF ADDRESSING MODES The program counter fetches the instructions stored in the program memory for execution. These instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.

  • Page 52: Register (R) Addressing Mode

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.2 REGISTER (R) ADDRESSING MODE In Register (R) addressing mode, the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing since it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

  • Page 53: Indirect Register (Ir) Addressing Mode

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.3 INDIRECT REGISTER (IR) ADDRESSING MODE In Indirect Register (IR) addressing mode, the content of a specified register or register pair is the address of operand. Depending on the instruction used, the actual address can point to a register in register file, to program memory (ROM), or to an external memory space (see through 3-6).

  • Page 54: Indirect Register (Ir) Addressing Mode (Continued)

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.4 INDIRECT REGISTER (IR) ADDRESSING MODE (CONTINUED) Register File Program Memory REGISTER Example PAIR Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...

  • Page 55: Indirect Register (Ir) Addressing Mode (Continued)

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.5 INDIRECT REGISTER (IR) ADDRESSING MODE (CONTINUED) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points Program Memory to start fo working register 4-bit block 3 LSBs Working Register Point to the OPCODE ADDRESS Address...

  • Page 56: Indirect Register (Ir) Addressing Mode (Concluded)

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.6 INDIRECT REGISTER (IR) ADDRESSING MODE (CONCLUDED) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register 4-bit Working block Register Address Register Next 2-bit Point Pair OPCODE to Working...

  • Page 57: Indexed (X) Addressing Mode

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.7 INDEXED (X) ADDRESSING MODE Indexed (X) addressing mode adds an offset value to base address while executing an instruction in order to calculate the effective operand address (see 3-7). You can use Indexed addressing mode to access Figure locations in the internal register file or external memory.

  • Page 58: Indexed (X) Addressing Mode (Continued)

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.8 INDEXED (X) ADDRESSING MODE (CONTINUED) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register block OFFSET NEXT 2 Bits 4-bit Working Register dst/src Register Address Point to Working...

  • Page 59: Indexed (X) Addressing Mode (Concluded)

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.9 INDEXED (X) ADDRESSING MODE (CONCLUDED) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of Program Memory working register OFFSET block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address...

  • Page 60: Direct Address (Da) Mode

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.10 DIRECT ADDRESS (DA) MODE In Direct Address (DA) mode, the instruction provides an operand’s 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address loaded into the PC whenever a JP or CALL instruction is executed.

  • Page 61: Direct Address (Da) Mode (Continued)

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.11 DIRECT ADDRESS (DA) MODE (CONTINUED) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11 Direct Addressing for Call and Jump Instructions 3-11...

  • Page 62: Indirect Address (Ia) Mode

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.12 INDIRECT ADDRESS (IA) MODE In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of next instruction to be executed. Only the CALL instruction can use the Indirect Address mode.

  • Page 63: Relative Address (Ra) Mode

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.13 RELATIVE ADDRESS (RA) MODE In Relative Address (RA) mode, a two’s complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. Its result is the address of next instruction to be executed.

  • Page 64: Immediate Mode (Im)

    S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3.14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in instruction is the value supplied in operand field itself. The operand can be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.

  • Page 65: Control Registers

    4.1 OVERVIEW OF CONTROL REGISTERS This section provides a detailed description of the S3F84B8 control registers in an easy-to-read format to familiarize you with the mapped locations in register file. You can also use them as a quick-reference source when writing application programs.
  • Page 66 S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS Register Name Mnemonic Address and RESET Value (Bit) Location Address Port 0 control register (Low byte) P0CONL – – Port 0 interrupt pending register P0PND – – Port 1 control register P1CON – – Port 2 control register (High byte) P2CONH Port 2 control register (Low byte) P2CONL...
  • Page 67 S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS Table 4-2 System and Peripheral Control Registers Set1 Bank1 Register Name Mnemonic Address and RESET Value (Bit) Location Address Operational Amplifier control register OPACON – – – – – – Timer A control register TACON Timer A clock pre-scalar TAPS –...
  • Page 68 S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register address Register bit or related bits (hexadecimal) Register name FLAGS - System Flags Register Bit Identifier RESET Value Read/Write Carry Flag (C) Operation dose not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit7...

  • Page 69: Adcon — A/D Converter Control Register: Fah, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.1 ADCON — A/D CONVERTER CONTROL REGISTER: FAH, BANK0 Bit Identifier RESET Value Read/Write .7–.5 A/D Converter Input Pin Selection Bits ADC0 (P2.0) ADC1 (P2.1) ADC2 (P2.2) ADC3 (P2.3) ADC4 (P2.4) ADC5 (P2.5) ADC6 (P2.6) ADC7 (P2.7) AD Conversion Completion Interrupt Enable Bit Disables ADC Interrupt.

  • Page 70: Amtdata — Anti-Mis-Trigger Data Register: F6H, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.2 AMTDATA — ANTI-MIS-TRIGGER DATA REGISTER: F6H, BANK0 Bit Identifier RESET Value Read/Write Register addressing mode only Addressing Mode Anti-mis-trigger time= (AMTDATA  4)/fpwmclk + TST .7–.0 NOTE: 0 < TST (setting time) < 4/fpwmclk 4.1.3 BTCON —...

  • Page 71: Buzcon — Buz Control Register: F7H, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.4 BUZCON — BUZ CONTROL REGISTER: F7H, BANK0 Bit Identifier RESET Value Read/Write Register addressing mode only Addressing Mode .7–.6 BUZ Input Clock Selection Code /128 BUZ Enable Bit Disables BUZ. Enables BUZ. .4–.0 BUZ Frequency = f /[(BUZCON.4–0)+1]2...

  • Page 72: Clkcon — Clock Control Register: D4H, Bank0

    Oscillator IRQ Wake-up Function Enable Bit Enables IRQ for main system oscillator wake-up function. Disables IRQ for main system oscillator wake-up function. .6–.5 Not used for S3F84B8. .4–.3 Divided by Selection Bits for CPU Clock Frequency Divide by 16 (f...

  • Page 73: Cmp0Con — Comparator0 Control Register: Eah, Bank0

    – – RESET Value – – – Read/Write .7–.5 Not used for S3F84B8. Comparator0 Output Polarity Select Bit Does not invert CMP0 output. Inverts CMP0 output. Comparator0 Enable Bit Disables CMP0. Enables CMP0. Comparator0 Interrupt Enable Bit Disables CMP0 interrupt.

  • Page 74: Cmp1Con — Comparator1 Control Register: Ebh, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.7 CMP1CON — COMPARATOR1 CONTROL REGISTER: EBH, BANK0 Bit Identifier RESET Value Read/Write .7–.5 Comparator 1 Reference Level Selection Bit 0.45VDD 0.50VDD 0.55VDD 0.60VDD 0.65VDD 0.70VDD 0.75VDD 0.80VDD Comparator1 Output Polarity Select Bit Does not invert CMP1 output. Inverts CMP1 output.

  • Page 75: Cmp2Con — Comparator1 Control Register: Ech, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.8 CMP2CON — COMPARATOR1 CONTROL REGISTER: ECH, BANK0 Bit Identifier RESET Value Read/Write .7–.5 Comparator 2 Reference Level Selection Bit 0.45VDD 0.50VDD 0.55VDD 0.60VDD 0.65VDD 0.70VDD 0.75VDD 0.80VDD Comparator2 Output Polarity Select Bit Does not invert CMP2 output. Inverts CMP2 output.

  • Page 76: Cmp3Con — Comparator1 Control Register: Edh, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.9 CMP3CON — COMPARATOR1 CONTROL REGISTER: EDH, BANK0 Bit Identifier RESET Value Read/Write .7–.5 Comparator3 Reference Level Selection Bit 0.45VDD 0.50VDD 0.55VDD 0.60VDD 0.65VDD 0.70VDD 0.75VDD 0.80VDD Comparator3 Output Polarity Select Bit Does not invert CMP3 output. Inverts CMP3 output.

  • Page 77: Cmpint — Comparator Interrupt Mode Control Register: Eeh, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.10 CMPINT — COMPARATOR INTERRUPT MODE CONTROL REGISTER: EEH, BANK0 Bit Identifier RESET Value Read/Write .7–.6 CMP3 Interrupt Mode Selection Bit Invalid setting Falling edge interrupt Rising edge interrupt Falling and rising edge interrupt .5–.4 CMP2 Interrupt mode selection bit Invalid setting Falling edge interrupt...

  • Page 78: Flags — System Flags Register: D5H, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.11 FLAGS — SYSTEM FLAGS REGISTER: D5H, BANK0 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode Carry Flag (C) Operation does not generate a carry or borrow condition. Operation generates a carry or borrow into high-order bit 7. Zero Flag (Z) Operation results in a non-zero value.

  • Page 79: Fmcon — Flash Memory Control Register: F5H, Bank1

    Not available Sector Erase Status Bit Success sector erase Fail sector erase .2–.1 Not used for the S3F84B8 Flash Operation Start Bit Operation stops. Operation starts (This bit will be cleared automatically just after the corresponding operation is completed). 4.1.13 FMSECH — FLASH MEMORY SECTOR ADDRESS REGISTER (HIGH BYTE): F7H, BANK1...

  • Page 80: Fmsecl — Flash Memory Sector Address Register (Low Byte): F8H, Bank1

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.14 FMSECL — FLASH MEMORY SECTOR ADDRESS REGISTER (LOW BYTE): F8H, BANK1 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode Flash Memory Sector Address Bit (Low Byte) The 7 bit selects a sector of flash ROM. .6–.0 Bits 6–0 Don’t care.

  • Page 81: Imr — Interrupt Mask Register: Ddh, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.16 IMR — INTERRUPT MASK REGISTER: DDH, BANK0 Bit Identifier Reset Value Read/Write Interrupt Level 7 (IRQ7) Disables (mask). Enables (unmask). Interrupt Level 6 (IRQ6) Disables (mask). Enables (unmask). Interrupt Level 5 (IRQ5) Disables (mask). Enables (unmask).

  • Page 82: Iph — Instruction Pointer (High Byte): Dah, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.17 IPH — INSTRUCTION POINTER (HIGH BYTE): DAH, BANK0 Bit Identifier Reset Value Read/Write .7–.0 Instruction Pointer Address (High Byte) The high byte Instruction Pointer’s value is the upper 8-bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).

  • Page 83: Ipr — Interrupt Priority Register: Ffh, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.19 IPR — INTERRUPT PRIORITY REGISTER: FFH, BANK0 Bit Identifier Reset Value Read/Write .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C (Note) Group priority undefined B > C > A A >...

  • Page 84: Irq — Interrupt Request Register: Dch, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.20 IRQ — INTERRUPT REQUEST REGISTER: DCH, BANK0 Bit Identifier Reset Value Read/Write Level 7 (IRQ7) Request Pending Bit Not pending Pending Level 6 (IRQ6) Request Pending Bit Not pending Pending Level 5 (IRQ5) Request Pending Bit Not pending Pending Level 4 (IRQ4) Request Pending Bit...

  • Page 85: Opacon — Op Amp Control Register: E0H, Bank1

    – – – – – Read/Write .7–.2 Not used for S3F84B8. OP AMP Mode Select Bit Off chip mode (External positive input) On chip mode (Internal ground level positive input) OP AMP Enable Bit Disables OP AMP. Enables OP AMP.

  • Page 86: P0Conh — Port 0 Control Register (High Byte): E4H, Bank0

    Bit Identifier – – RESET Value – – Read/Write .7–.6 Not used for S3F84B8. .5–.4 Port 0, P0.6/INT5/TAOUT Configuration Bits Input mode/INT5 falling edge interrupt Input mode with pull-up/INT5 falling edge interrupt Push-pull output Alternative function: TAOUT .3–.2 Port 0, P0.5/INT4 Configuration Bits...

  • Page 87: P0Conl — Port 0 Control Register (Low Byte): E5H, Bank0

    Input mode/INT2 falling edge interrupt Input mode with pull-up/INT2 falling edge interrupt Push-pull output Alternative function: BUZ .5–.4 Not used for S3F84B8. .3–.2 Port 0, P0.1/INT1 Configuration Bits Input mode/INT1 falling edge interrupt Input mode with pull-up/INT1 falling edge interrupt...

  • Page 88: P0Int — Port 0 Interrupt Control Register: E3H, Bank0

    4.1.24 P0INT — PORT 0 INTERRUPT CONTROL REGISTER: E3H, BANK0 Bit Identifier – – RESET Value – – Read/Write Not used for S3F84B8. P0.6/INT5 Interrupt Enable/Disable Selection Bits Disables interrupt. Enables interrupt. P0.5/INT4 Interrupt Enable/Disable Selection Bits Disables interrupt. Enables interrupt. P0.4/INT3 Interrupt Enable/Disable Selection Bits Disables interrupt.

  • Page 89: P0Pnd — Port 0 Interrupt Pending Register: E6H, Bank0

    – RESET Value – – Read/Write Not used for S3F84B8. Port 0.6/INT5 Interrupt Pending Bit No interrupt is pending (when read); clears pending bit (when write). Interrupt is pending (when read); no effect (when write). Port 0.5/INT4 Interrupt Pending Bit No interrupt is pending (when read);...

  • Page 90: P1Con — Port 1 Control Register: E7H, Bank0

    4 CONTROL REGISTERS 4.1.26 P1CON — PORT 1 CONTROL REGISTER: E7H, BANK0 Bit Identifier RESET Value Read/Write .7–.6 Not used for S3F84B8. .5–.4 Port 1, P1.2/CMP1_N Configuration Bits Schmitt trigger input Schmitt trigger input; enables pull-up. Push pull output Alternative function: comparator 1 negative input .3–.2...

  • Page 91: P2Conh — Port 2 Control Register (High Byte): E8H, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.27 P2CONH — PORT 2 CONTROL REGISTER (HIGH BYTE): E8H, BANK0 Bit Identifier RESET Value Read/Write .7–.6 Port2, P2.7/ADC7 Configuration Bits Schmitt trigger input Schmitt trigger input; enables pull-up. Push pull output Alternative function: ADC7 input .5–.4 Port 2, P2.6/ADC6 Configuration Bits Schmitt trigger input...

  • Page 92: P2Conl — Port 2 Control Register (Low Byte): E9H, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.28 P2CONL — PORT 2 CONTROL REGISTER (LOW BYTE): E9H, BANK0 Bit Identifier RESET Value Read/Write .7–.6 Part 2, P2.3/ADC3/(OA_O) Configuration Bits Schmitt trigger input Schmitt trigger input; enables pull-up. Push-pull output (NOTE) Alternative function: ADC3 input .5–.4 Port 2, P2.2/ADC2/OA_N Configuration Bits Schmitt trigger input...

  • Page 93: Pwmcon — Pwm Control Register: Efh, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.29 PWMCON — PWM CONTROL REGISTER: EFH, BANK0 Bit Identifier RESET Value Read/Write .7–.6 PWM Input Clock Select Bits PWM Output Polarity Select Bit Non-inverting output Inverting output PWM Counter Clear Bit No effect. Clears the PWM counter (when write). PWM Counter Enable Bit Stops counter.

  • Page 94: Pwmccon — Pwm Cmp Control Register: F0H, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.30 PWMCCON — PWM CMP CONTROL REGISTER: F0H, BANK0 Bit Identifier RESET Value Read/Write .7–.6 CMP3 PWM Linkage Mode Selection Bits Disables linkage. Soft Lock Hard lock .5–.4 CMP2 PWM Linkage Mode Selection Bit Disables linkage. Soft Lock Hard lock .3–.2...

  • Page 95: Pwmdl — Comparator0 Output Delay Register: F5H, Bank0

    Not used for S3F84B8. NOTE: In S3F84B8, only Page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to ‘00F’ following a hardware reset. These values should not be changed during normal operation.

  • Page 96: Resetid — Reset Source Indicating Register: F2H, Bank1

    – Read/Write Register addressing mode only Addressing Mode .7–.5 Not used for S3F84B8. nReset Pin Indicating Bit Reset is not generated by nReset pin (when read). Reset is generated by nReset pin (when read). Not used for S3F84B8. WDT Reset Indicating Bit Reset is not generated by WDT (when read).

  • Page 97: Rp0 — Register Pointer 0: D6H, Bank0

    8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H and selects the 8-byte working register slice C0H–C7H. .2–.0 Not used for the S3F84B8. 4.1.35 RP1 — REGISTER POINTER 1: D7H, BANK0 Bit Identifier –...

  • Page 98: Spl — Stack Pointer: D9H, Bank0

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.36 SPL — STACK POINTER: D9H, BANK0 Bit Identifier Reset Value Read/Write .7–.0 Stack Pointer Address (Low Byte) The SP value is undefined following a reset. 4.1.37 STOPCON — STOP MODE CONTROL REGISTER: F4H, BANK1 Bit Identifier RESET Value Read/Write...

  • Page 99: Sym — System Mode Register: Deh, Bank0

    – – Read/Write Tri-state External Interface Control Bit Normal operation (disables tri-state operation). Sets the external interface lines to high impedance (enables tri-state operation). .6–.5 Not used for S3F84B8. .4–.2 Fast Interrupt Level Selection Bits IRQ0 IRQ1 IRQ2 IRQ3 IRQ4...

  • Page 100: Tacon — Timer A Control Register: E1H, Bank1

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.39 TACON — TIMER A CONTROL REGISTER: E1H, BANK1 Bit Identifier RESET Value Read/Write .7–.6 Timer A Operating Mode Selection Bits Internal mode (TAOUT mode) Capture mode (captures on rising edge; counter running; OVF can occur) Capture mode (captures on falling edge;...

  • Page 101: Taps — Ta Pre-Scalar Register: E2H, Bank1

    RESET Value – – – Read/Write Timer A Clock Source Selection Internal clock source External clock source from TACK .6–.5 Not used for S3F84B8. .3–.0 Timer A Pre-Scalar Bits TAPS = TA clock/ (2TAPS[3-0]); Pre-scalar values above 12 are invalid. 4-37...

  • Page 102: Tccon — Timer C Control Register: E5H, Bank1

    Read/Write Timer 0 Operation Mode Selection Bit Two 8-bit timers mode (Timer C/D) One 16-bit timer mode (Timer 0) Not used for S3F84B8. Timer C Counter Clear Bit No effect. Clears the timer C counter (After clearing, returns to zero).

  • Page 103: Tcps — Tc Pre-Scalar Register: E6H, Bank1

    Timer C Clock Source Selection Internal clock source CMP0 output .6–.4 Not used for S3F84B8. .3–.0 Timer C Pre-Scalar Bits TC CLK = TC CLK/(2TCPS); Pre-scalar values above 12 are invalid. NOTE: When Timer 0 is working in one 16-bit timer mode, the clock is determined by TCPS.

  • Page 104: Tdcon — Timer D Control Register: E9H, Bank1

    S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4.1.43 TDCON — TIMER D CONTROL REGISTER: E9H, BANK1 Bit Identifier RESET Value Read/Write .7–.6 Timer D Operating Mode Selection Bits Interval mode 6-bit PWM mode (OVF interrupt can occur) 7-bit PWM mode (OVF interrupt can occur) 8-bit PWM mode (OVF interrupt can occur) Timer D Counter Clear Bit No effect...

  • Page 105: Tdps — Td Pre-Scalar Register: Eah, Bank1

    4.1.44 TDPS — TD PRE-SCALAR REGISTER: EAH, BANK1 Bit Identifier – – – – RESET Value – – – – Read/Write .7–.4 Not used for S3F84B8. .3–.0 Timer D Pre-Scalar Bits TD CLK = TD CLK/(2TDPS[.3-.0]) Pre-scalar values above 12 are invalid. 4-41...

  • Page 106: Interrupt Structure

    A source refers to any peripheral that generates an interrupt. It can be an external pin or a counter overflow. Each vector can have several interrupt sources. There are 17 possible interrupt sources in S3F84B8 interrupt structure, which means that every source can have its own vector.

  • Page 107: Interrupt Types

    – S  Type 3: One level (IRQn) + multiple vectors (V – V ) + multiple sources (S – S – S In the S3F84B8 microcontroller, type 1 and type 2 are implemented. Levels Vectors Sources IRQn Type 1: IRQn...

  • Page 108: S3F84B8 Interrupt Structure

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.5 S3F84B8 INTERRUPT STRUCTURE The S3F84B8 microcontroller supports 17 interrupt sources. Every interrupt source has a corresponding interrupt address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.

  • Page 109: Interrupt Vector Addresses

    5 INTERRUPT STRUCTURE 5.1.5.1 Interrupt Vector Addresses All interrupt vector addresses for the S3F84B8 interrupt structure is stored in the vector address area of first 256 bytes of the program memory (ROM). You can allocate unused locations in the vector address area as normal program memory. However, do not overwrite any of the stored vector addresses.

  • Page 110: System-Level Interrupt Control Registers

    Interrupt priority register Controls the relative processing priorities of the interrupt levels. The eight levels of S3F84B8 are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3, and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

  • Page 111: Interrupt Processing Control Points

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.7 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: globally or by specific interrupt level and source. The system- level control points in the interrupt structure are:  Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0) ...

  • Page 112: Peripheral Interrupt Control Registers

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.8 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source, there is one or more corresponding peripheral control register that let you control the interrupt generated by the related peripheral (see Table 5-2). Table 5-2 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register(s)

  • Page 113: System Mode Register (Sym)

    1 = Enable all interrupts processing selection bits: Not used for the Fast interrupt enable bit: 0 0 0 IRQ0 S3F84B8 0 = Disable fast interrupts processing 0 0 1 IRQ1 1 = Enable fast interrupts processing 0 1 0...

  • Page 114: Interrupt Mask Register (Imr)

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.10 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set1) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must be written to their required settings by the initialization routine.

  • Page 115: Interrupt Priority Register (Ipr)

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.11 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set1, Bank0), is used to set the relative priorities of interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must be written to their required settings by the initialization routine.
  • Page 116 S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE Interrupt Priority Register (IPR) FFH, Set1, Bank0, R/W Group priority: Group A 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ1 > IRQ0 Group B = Undefined 0 = IRQ2 > (IRQ3, IRQ4) = B >...

  • Page 117: Interrupt Request Register (Irq)

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.12 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (DCH, Set1), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.

  • Page 118: Interrupt Pending Function Types

    “0”. This type of pending bit is not mapped and cannot be read or written by the application software. In S3F84B8 interrupt structure, TimerA, TimerD, and PWM counter overflow interrupts belong to this category of interrupts, where pending bits can be cleared automatically by the hardware.

  • Page 119: Interrupt Source Polling Sequence

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.14 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to “1”. 2. The CPU polling procedure identifies a pending condition for that source. 3.

  • Page 120: Generating Interrupt Vector Addresses

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.16 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1.

  • Page 121: Instruction Pointer (Ip)

    When a fast interrupt occurs, the contents of FLAGS register are stored in an unmapped, dedicated register called FLAGS’ (“FLAGS prime”). NOTE: For the S3F84B8 microcontroller, the service routine for any one of the eight interrupt levels (IRQ0–IRQ7) can be selected for fast interrupt processing.

  • Page 122: Procedure For Initiating Fast Interrupts

    S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5.1.20 PROCEDURE FOR INITIATING FAST INTERRUPTS To initiate fast interrupt processing, follow these steps: 1. Load the start address of the service routine into the instruction pointer (IP). 2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2). 3.

  • Page 123: Instruction Set

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET INSTRUCTION SET 6.1 OVERVIEW OF INSTRUCTION SET The SAM8RC instruction set is specifically designed to support large register files that are typical of most SAM8 microcontrollers. The set contains 78 instructions. 6.1.1 KEY FEATURES OF INSTRUCTION SET The powerful data manipulation capabilities and features of the instruction set include: ...
  • Page 124 S3F84B8_UM_REV 1.00 6 INSTRUCTION SET Table 6-1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load bit dst,src Load external data memory dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrement LDEI dst,src...
  • Page 125 S3F84B8_UM_REV 1.00 6 INSTRUCTION SET Mnemonic Operands Instruction Complement dst,src Logical OR dst,src Logical exclusive OR Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal...
  • Page 126 S3F84B8_UM_REV 1.00 6 INSTRUCTION SET Mnemonic Operands Instruction Complement carry flag Disable interrupts Enable interrupts IDLE Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers SRP0 Set register pointer 0 SRP1 Set register pointer 1 STOP...

  • Page 127: Flags Register (Flags)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.2 FLAGS REGISTER (FLAGS) The flags register (FLAGS) contains eight bits that describe current status of the CPU operations. Four of these bits, FLAGS.7 to FLAGS.4, can be tested and used with conditional jump instructions; two other bits, FLAGS.3 and FLAGS.2, are used for BCD arithmetic.

  • Page 128: Flag Descriptions

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.2.1 FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to “1” if the result from an arithmetic operation generates a carry-out from (or a borrow to) the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of specified register. Program instructions can set, clear, or complement the carry flag.

  • Page 129: Instruction Set Notation

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.2.2 INSTRUCTION SET NOTATION Table 6-2 Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation –...

  • Page 130: Table 6-4 Instruction Notation Conventions

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET Table 6-4 Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Bit (b) of working register Rn.b (n = 0–15, b = 0–7) Bit 0 (LSB) of working register Rn (n = 0–15) Working register pair...

  • Page 131: Table 6-5 Opcode Quick Reference

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET Table 6-5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1...
  • Page 132 S3F84B8_UM_REV 1.00 6 INSTRUCTION SET OPCODE MAP LOWER NIBBLE (HEX) IDLE        STOP IRET        DJNZ r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA 6-10...

  • Page 133: Condition Codes

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.2.3 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This code specifies the conditions under which the jump is executed. For example, a conditional jump with the condition code for “equal”...

  • Page 134: Instruction Descriptions

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and fast referencing. The following information is included in each instruction description: ...

  • Page 135: Adc — Add With Carry

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.1 ADC — ADD WITH CARRY dst,src dst  dst + src + c Operation: The source operand, along with the carry flag, is added to the destination operand. The sum is stored in the destination. Contents of the source remain unaffected. Two’s-complement addition is performed.

  • Page 136: Add — Add

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.2 ADD — ADD dst,src dst  dst + src Operation: The source operand is added to the destination operand. Their sum is stored in the destination. The contents of source remain unaffected. Two’s-complement addition is performed. C: Set if there is a carry from the most significant bit of the result;...

  • Page 137: And — Logical And

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.3 AND — LOGICAL AND dst,src dst  dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. If the corresponding bits in two operands are both logic ones, AND operation results in a “1”...

  • Page 138: Band — Bit And

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.4 BAND — BIT AND dst,src.b BAND dst.b,src BAND dst(0)  dst(0) AND src(b) Operation: dst(b)  dst(b) AND src(0) The specified bit of source (or destination) is logically ANDed with the zero bit (LSB) of the destination (or source).

  • Page 139: Bcp — Bit Compare

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.5 BCP — BIT COMPARE dst,src.b dst(0) – src(b) Operation: The specified bit of source is compared to (subtracted from) bit zero (LSB) of destination. Zero flag is set if the bits are same; otherwise it is cleared. The contents of both operands remain unaffected by the comparison.

  • Page 140: Bitc — Bit Complement

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.6 BITC — BIT COMPLEMENT dst.b BITC dst(b)  NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits there. C: Unaffected. Flags: Z: Set if the result is “0”; cleared otherwise. S: Cleared to “0”.

  • Page 141: Bitr — Bit Reset

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.7 BITR — BIT RESET dst.b BITR dst(b)  0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. No flags are affected. Flags: Format: Bytes Cycles Opcode...

  • Page 142: Bits — Bit Set

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.8 BITS — BIT SET dst.b BITS dst(b)  1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. No flags are affected. Flags: Format: Bytes Cycles Opcode...

  • Page 143: Bor — Bit Or

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.9 BOR — BIT OR dst,src.b dst.b,src dst(0)  dst(0) OR src(b) Operation: dst(b)  dst(b) OR src(0) The specified bit of source (or destination) is logically ORed with bit zero (LSB) of destination (or source).

  • Page 144: Btjrf — Bit Test, Jump Relative On False

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.10 BTJRF — BIT TEST, JUMP RELATIVE ON FALSE dst,src.b BTJRF If src(b) is a “0”, then PC  PC + dst. Operation: The specified bit within source operand is tested. If the bit is “0”, the relative address is added to the program counter and control shifts to the statement whose address is now in the PC;...

  • Page 145: Btjrt — Bit Test, Jump Relative On True

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.11 BTJRT — BIT TEST, JUMP RELATIVE ON TRUE dst,src.b BTJRT If src(b) is a “1”, then PC  PC + dst. Operation: The specified bit within the source operand is tested. If the bit is “1”, the relative address is added to the program counter and control passes to the statement whose address is in the PC;...

  • Page 146: Bxor — Bit Xor

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.12 BXOR — BIT XOR dst,src.b BXOR dst.b,src BXOR dst(0)  dst(0) XOR src(b) Operation: dst(b)  dst(b) XOR src(0) The specified bit of source (or destination) is logically exclusive-ORed with bit zero (LSB) of destination (or source).

  • Page 147: Call — Call Procedure

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.13 CALL — CALL PROCEDURE CALL  SP – 1 Operation:   SP –1   The current contents of program counter are pushed onto the top of stack. Here, the program counter value used specifies the address of first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and it points to the first instruction of a procedure.

  • Page 148: Ccf — Complement Carry Flag

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.14 CCF — COMPLEMENT CARRY FLAG C  NOT C Operation: The carry flag (C) is complemented. If C = “1”, the value of the carry flag is changed to logic zero; if C = “0”, the value of the carry flag is changed to logic one. C: Complemented.

  • Page 149: Clr — Clear

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.15 CLR — CLEAR dst  “0” Operation: The destination location is cleared to “0”. No flags are affected. Flags: Format: Bytes Cycles Opcode Addr Mode (Hex) Given Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: Examples: ...

  • Page 150: Com — Complement

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.16 COM — COMPLEMENT dst  NOT dst Operation: The contents of destination location are complemented (one’s complement); all “1’s” are changed to “0’s”, and vice versa. C: Unaffected. Flags: Z: Set if the result is “0”; cleared otherwise. S: Set if the result bit 7 is set;...

  • Page 151: Cp — Compare

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.17 CP — COMPARE dst,src dst – src Operation: The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands remain unaffected by the comparison.

  • Page 152: Cpije — Compare, Increment, And Jump On Equal

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.18 CPIJE — COMPARE, INCREMENT, AND JUMP ON EQUAL dst,src,RA CPIJE If dst – src = “0”, PC  PC + RA Operation: Ir  Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is “0”, the relative address is added to the program counter and control is passed to the statement whose address is now in the program counter.

  • Page 153: Cpijne — Compare, Increment, And Jump On Non-Equal

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.19 CPIJNE — COMPARE, INCREMENT, AND JUMP ON NON-EQUAL dst,src,RA CPIJNE “0”, PC  PC + RA If dst – src Operation: Ir  Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not “0”, the relative address is added to the program counter and control is passed to the statement whose address is now in the program counter;...

  • Page 154: Da — Decimal Adjust

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.20 DA — DECIMAL ADJUST dst  DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed.

  • Page 155: Da — Decimal Adjust (Continued)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.21 DA — DECIMAL ADJUST (CONTINUED) Given that working register R0 contains the value 15 (BCD), working register R1 contains Example: the value 27 (BCD), and address 27H contains the value 46 (BCD): C  “0”, H  “0”, Bits 4–7 = 3, bits 0–3 = C, R1  3CH R1,R0 ;...

  • Page 156: Dec — Decrement

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.22 DEC — DECREMENT dst  dst – 1 Operation: The contents of the destination operand are decremented by one. C: Unaffected. Flags: Z: Set if the result is “0”; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred;...

  • Page 157: Decw — Decrement Word

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.23 DECW — DECREMENT WORD DECW dst  dst – 1 Operation: The contents of destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value decremented by one. C: Unaffected.

  • Page 158: Di — Disable Interrupts

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.24 DI — DISABLE INTERRUPTS SYM (0)  0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to “0”, globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them if interrupt processing is disabled.

  • Page 159: Div — Divide (Unsigned)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.25 DIV — DIVIDE (UNSIGNED) dst,src dst ÷ src Operation: dst (UPPER)  REMAINDER dst (LOWER)  QUOTIENT Destination operand (16-bits) is divided by source operand (8-bits). The quotient (8-bits) is stored in the lower half of destination, while the remainder (8-bits) is stored in the upper half of destination.

  • Page 160: Djnz — Decrement And Jump If Non-Zero

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.26 DJNZ — DECREMENT AND JUMP IF NON-ZERO r,dst DJNZ r  r – 1 Operation: If r  0, PC  PC + dst The working register, which is used as a counter, is decremented. If the contents of register are not logic zero after decrementing, the relative address is added to the program counter and control is passed to the statement whose address is now in the PC.

  • Page 161: Ei — Enable Interrupts

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.27 EI — ENABLE INTERRUPTS SYM (0)  1 Operation: An EI instruction sets the bit zero of system mode register, SYM.0, to “1”. This allows the interrupts to be serviced as they occur (assuming they have the highest priority). If an interrupt’s pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.

  • Page 162: Enter — Enter

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.28 ENTER — ENTER ENTER  SP – 2 Operation:     IP + 2 This instruction is useful while implementing threaded-code languages. The contents of instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.

  • Page 163: Figure 6-3 Example Of The Usage Of Exit Statement

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET EXIT — Exit EXIT  Operation:  SP + 2   IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.

  • Page 164: Idle — Idle Operation

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.29 IDLE — IDLE OPERATION IDLE Operation: The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. In application programs, an IDLE instruction must be immediately followed by at least three NOP instructions.

  • Page 165: Inc — Increment

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.30 INC — INCREMENT dst  dst + 1 Operation: The contents of the destination operand are incremented by one. C: Unaffected. Flags: Z: Set if the result is “0”; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred;...

  • Page 166: Incw — Increment Word

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.31 INCW — INCREMENT WORD INCW dst  dst + 1 Operation: The contents of destination (containing an even address) and the byte following that location are treated as a single 16-bit value incremented by one. C: Unaffected.

  • Page 167: Iret — Interrupt Return

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.32 IRET — INTERRUPT RETURN IRET (Normal) IRET (Fast) IRET FLAGS  @SP PC  IP Operation: SP  SP + 1 FLAGS  FLAGS’ PC  @SP FIS  0 SP  SP + 2 SYM(0) ...

  • Page 168: Jp — Jump

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.33 JP — JUMP cc,dst (Conditional) (Unconditional) If cc is true, PC  dst. Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.

  • Page 169: Jr — Jump Relative

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.34 JR — JUMP RELATIVE cc,dst If cc is true, PC  PC + dst. Operation: If the condition specified by condition code (cc) is true, then relative address is added to the program counter and control is passed to the statement whose address is now in the program counter;...

  • Page 170: Ld — Load

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.35 LD — LOAD dst,src dst  src Operation: The contents of the source are loaded into the destination. The source contents remain unaffected. No flags are affected. Flags: Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc src | opc...

  • Page 171: Ld — Load (Continued)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.36 LD — LOAD (CONTINUED) Given R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, Examples: register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:  R0,#10H R0 = 10H ...

  • Page 172: Ldb — Load Bit

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.37 LDB — LOAD BIT dst,src.b dst.b,src dst(0)  src(b) Operation: dst(b)  src(0) The specified bit of source is loaded into bit zero (LSB) of destination, or bit zero of source is loaded into the specified bit of destination. No other bits of the destination are affected. The source remains unaffected.

  • Page 173: Ldc/Lde — Load Memory

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.38 LDC/LDE — LOAD MEMORY dst,src LDC/LDE dst  src Operation: This instruction loads a byte from program or data memory into a working register, or vice versa. The source values remain unaffected. LDC refers to program memory, while LDE refers to data memory.

  • Page 174: Ldc/Lde — Load Memory (Continued)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.39 LDC/LDE — LOAD MEMORY (CONTINUED) LDC/LDE Given R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations Examples: 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H; External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: ;...

  • Page 175: Ldcd/Lded — Load Memory And Decrement

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.40 LDCD/LDED — LOAD MEMORY AND DECREMENT dst,src LDCD/LDED dst  src Operation: rr  rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of memory location is specified by a working register pair.

  • Page 176: Ldci/Ldei — Load Memory And Increment

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.41 LDCI/LDEI — LOAD MEMORY AND INCREMENT dst,src LDCI/LDEI dst  src Operation: rr  rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of memory location is specified by a working register pair.

  • Page 177: Ldcpd/Ldepd — Load Memory With Pre-Decrement

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.42 LDCPD/LDEPD — LOAD MEMORY WITH PRE-DECREMENT LDCPD/ dst,src LDEPD rr  rr – 1 Operation: dst  src These instructions are used for block transfers of data from program or data memory from the register file.

  • Page 178: Ldcpi/Ldepi — Load Memory With Pre-Increment

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.43 LDCPI/LDEPI — LOAD MEMORY WITH PRE-INCREMENT LDCPI/ dst,src LDEPI rr  rr + 1 Operation: dst  src These instructions are used for block transfers of data from program or data memory to the register file.

  • Page 179: Ldw — Load Word

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.44 LDW — LOAD WORD dst,src dst  src Operation: The contents of source (word) are loaded into the destination. The contents of source remain unaffected. No flags are affected. Flags: Format: Bytes Cycles Opcode Addr Mode (Hex) Given R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,...

  • Page 180: Mult — Multiply (Unsigned)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.45 MULT — MULTIPLY (UNSIGNED) dst,src MULT dst  dst  src Operation: The 8-bit destination operand (even register of register pair) is multiplied by the source operand (8-bits), and the product (16-bits) is stored in register pair specified by destination address. Both operands are treated as unsigned integers.

  • Page 181: Next — Next

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.46 NEXT — NEXT NEXT PC  @ IP Operation: IP  IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.

  • Page 182: Nop — No Operation

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.47 NOP — NO OPERATION No action is performed when the CPU executes this instruction. Typically, one or more NOPs are Operation: executed in sequence in order to affect a timing delay of variable duration. No flags are affected.

  • Page 183: Or — Logical Or

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.48 OR — LOGICAL OR dst,src dst  dst OR src Operation: The source operand is logically ORed with the destination operand, and the result is stored in destination. The contents of source remain unaffected. The OR operation results in a “1” being stored whenever either of the corresponding bits in two operands is a “1”;...

  • Page 184: Pop — Pop From Stack

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.49 POP — POP FROM STACK dst  @SP Operation: SP  SP + 1 The contents of location addressed by the stack pointer are loaded into destination. The stack pointer is then incremented by one. No flags are affected.

  • Page 185: Popud — Pop User Stack (Decrementing)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.50 POPUD — POP USER STACK (DECREMENTING) dst,src POPUD dst  src Operation: IR  IR – 1 This instruction is used for user-defined stacks in the register file. The contents of register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.

  • Page 186: Popui — Pop User Stack (Incrementing)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.51 POPUI — POP USER STACK (INCREMENTING) dst,src POPUI dst  src Operation: IR  IR + 1 The POPUI instruction is used for user-defined stacks in register file. The contents of register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.

  • Page 187: Push — Push To Stack

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.52 PUSH — PUSH TO STACK PUSH SP  SP – 1 Operation: @SP  src A PUSH instruction decrements the stack pointer value and loads the contents of source (src) into the location addressed by the decremented stack pointer. The operation then adds new value to the top of stack.

  • Page 188: Pushud — Push User Stack (Decrementing)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.53 PUSHUD — PUSH USER STACK (DECREMENTING) dst,src PUSHUD IR  IR – 1 Operation: dst  src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of source into register addressed by the decremented stack pointer.

  • Page 189: Pushui — Push User Stack (Incrementing)

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.54 PUSHUI — PUSH USER STACK (INCREMENTING) dst,src PUSHUI IR  IR + 1 Operation: dst  src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of source into the register location addressed by the incremented user stack pointer.

  • Page 190: Rcf — Reset Carry Flag

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.55 RCF — RESET CARRY FLAG C  0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. C: Cleared to “0”. Flags: No other flags are affected. Format: Bytes Cycles Opcode (Hex)

  • Page 191: Ret — Return

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.56 RET — RETURN PC  @SP Operation: SP  SP + 2 Typically, the RET instruction is used to return to the previously executed procedure at the end of a procedure entered by a CALL instruction. The contents of location addressed by the stack pointer are popped into the program counter.

  • Page 192: Rl — Rotate Left

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.57 RL — ROTATE LEFT C  dst (7) Operation: dst (0)  dst (7) dst (n + 1)  dst (n), n = 0–6 The contents of destination operand are rotated left one bit position. The initial value of bit 7 is moved to bit zero (LSB) position.

  • Page 193: Rlc — Rotate Left Through Carry

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.58 RLC — ROTATE LEFT THROUGH CARRY dst (0)  C Operation: C  dst (7) dst (n + 1)  dst (n), n = 0–6 The contents of destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C), while the initial value of carry flag replaces bit zero.

  • Page 194: Rr — Rotate Right

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.59 RR — ROTATE RIGHT C  dst (0) Operation: dst (7)  dst (0) dst (n  dst (n +1), n = 0–6 The contents of destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB).

  • Page 195: Rrc — Rotate Right Through Carry

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.60 RRC — ROTATE RIGHT THROUGH CARRY dst (7)  C Operation: C  dst (0) dst (n)  dst (n + 1), n = 0–6 The contents of destination operand and carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...

  • Page 196: Sb0 — Select Bank 0

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.61 SB0 — SELECT BANK 0 BANK  0 Operation: The SB0 instruction clears the bank address flag in FLAGS register (FLAGS.0) to logic zero and selects bank 0 register addressing in set 1 area of the register file. No flags are affected.

  • Page 197: Sbc — Subtract With Carry

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.63 SBC — SUBTRACT WITH CARRY dst,src dst  dst – src – c Operation: The source operand, along with the current value of carry flag, is subtracted from the destination operand. The result is stored in destination. The contents of source remain unaffected. Subtraction is performed by adding the two’s-complement of source operand to destination operand.

  • Page 198: Scf — Set Carry Flag

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.64 SCF — SET CARRY FLAG C  1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Set to “1”. Flags: No other flags are affected. Format: Bytes Cycles Opcode (Hex)

  • Page 199: Sra — Shift Right Arithmetic

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.65 SRA — SHIFT RIGHT ARITHMETIC dst (7)  dst (7) Operation: C  dst (0) dst (n)  dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.

  • Page 200: Rp/Srp0/Srp1 — Set Register Pointer

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.66 RP/SRP0/SRP1 — SET REGISTER POINTER SRP0 SRP1 If src (1) = 1 and src (0) = 0 then: RP0 (3–7) src (3–7) 　 Operation: If src (1) = 0 and src (0) = 1 then: RP1 (3–7) src (3–7) 　...

  • Page 201: Stop — Stop Operation

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.67 STOP — STOP OPERATION STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter the Stop mode. In the Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained.

  • Page 202: Sub — Subtract

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.68 SUB — SUBTRACT dst,src dst  dst – src Operation: Once source operand is subtracted from destination operand, the result is stored in destination. The contents of source remain unaffected. Subtraction is performed by adding the two’s complement of source operand to destination operand.

  • Page 203: Swap — Swap Nibbles

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.69 SWAP — SWAP NIBBLES SWAP dst (0 – 3)  dst (4 – 7) Operation: The contents of lower four bits and upper four bits of the destination operand are swapped. C: Undefined. Flags: Z: Set if the result is “0”;...

  • Page 204: Tcm — Test Complement Under Mask

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.70 TCM — TEST COMPLEMENT UNDER MASK dst,src (NOT dst) AND src Operation: This instruction tests selected bits in destination operand for a logic one value. The bits to be tested are specified by setting a “1” bit in the corresponding position of source operand (mask). The TCM statement complements destination operand, which is then ANDed with source mask.

  • Page 205: Tm — Test Under Mask

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.71 TM — TEST UNDER MASK dst,src dst AND src Operation: This instruction tests selected bits in destination operand for logic zero value. The bits to be tested are specified by setting a “1” bit in the corresponding position of source operand (mask), which is ANDed with destination operand.

  • Page 206: Wfi — Wait For Interrupt

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.72 WFI — WAIT FOR INTERRUPT Operation: The CPU is halted until an interrupt occurs; even though DMA transfers can still take place during the wait state. The WFI status can be released by an internal interrupt, including a fast interrupt. No flags are affected.

  • Page 207: Xor — Logical Exclusive Or

    S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6.3.73 XOR — LOGICAL EXCLUSIVE OR dst,src dst  dst XOR src Operation: Source operand is logically exclusive-ORed with destination operand. The result is stored in destination. The exclusive-OR operation results in a “1” bit being stored whenever the corresponding bits in the operands are different;...

  • Page 208: Clock Circuit

    (P0.1) can be used by normal I/O pins. An internal RC oscillator can provide a typical frequency of 8MHz or 0.5MHz for S3F84B8, depending on the Smart option. On the other hand, an external RC oscillator can provide a typical frequency of 8MHz clock for S3F84B8.

  • Page 209: Clock Status During Power-Down Modes

    In Stop mode, the main oscillator “freezes”. This in turn halts the CPU and peripherals. The contents of register file and current system register values are retained. Using a reset operation or an external interrupt with RC-delay noise filter (for S3F84B8, INT0–INT5), the Stop mode is released and oscillation is started. ...
  • Page 210 An external interrupt (with RC-delay noise filter ) can be used to release stop mode NOTE: and "wake-up" the main oscillator . In the S3F84B8, the INT0-INT5 external interrupts are of this type . Figure 7-4 System Clock Circuit Diagram...

  • Page 211: Reset And Power-Down

    The nRESET signal is inputted through a Schmitt trigger circuit, where it is then synchronized to the CPU clock. This brings the S3F84B8 into a known operating status. To ensure correct start-up, you should make sure that the nRESET signal is not released before the V level is sufficient.
  • Page 212 S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN Watchdog RESET RESET Internal System Longger than 1us RESETB Comparator When the V level is lower than V Longger than 1us Smart Option 3FH.7 NOTES: 1. The target of voltage detection level is the one you selected at smart option 3FH. 2.

  • Page 213: Mcu Initialization Sequence

    Internal nRESET LVR nRESET Watchdog nRESET Figure 8-2 Reset Block Diagram Oscillation Stabilization Wait Time (8.19 ms/at 8 MHz) nRESET Input Operation Mode Idle Mode Normal Mode or Power-Down Mode RESET Operation Figure 8-3 Timing for S3F84B8 after RESET...

  • Page 214: Power-Down Modes

    8.2.1.2 Using an External Interrupt to Release Stop Mode External interrupts with an RC-delay noise filter circuit can release the Stop mode (Clock-related external interrupts cannot be used for this purpose). External interrupts INT0-INT6 in the S3F84B8 interrupt structure meet this criterion.

  • Page 215: Idle Mode

    S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8.2.1.3 Idle Mode Idle mode is invoked by the IDLE (opcode 6FH) instruction. In Idle mode, the CPU operations are halted while select peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt logic and timer/counters.

  • Page 216: Hardware Reset Values

    An “x” means that the bit value is undefined after a reset.  A dash (“–”) means that the bit is either not used or not mapped, but read 0 is the bit value. Table 8-1 S3F84B8 Set1 Registers Values after RESET Register Name Mnemonic Address and...
  • Page 217 S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN Register Name Mnemonic Address and RESET Value (Bit) Location Address Comparator 2 control register CMP2CON Comparator 3 control register CMP3CON Comparator interrupt control register CMPINT PWM control register PWMCON PWM CMP register PWMCCON PWM delay trigger register PWMDL PWM preset data register (High byte) PWMPDATAH...
  • Page 218 S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN Table 8-2 System and Peripheral Control Registers Set1 Bank1 Register Name Mnemonic Address and RESET Value (Bit) Location Address Operational Amplifier control register OPACON – – – – – – Timer A control register TACON Timer A clock pre-scalar TAPS...

  • Page 219: I/O Port

    9.1 OVERVIEW OF I/O PORTS The S3F84B8 microcontroller has three bit-programmable I/O ports (P0, P1, and P2) and 17 I/O pins. Each port can be easily configured to meet the application design requirements. The CPU accesses ports by directly writing or reading the port registers.

  • Page 220: Port 0

    S3F84B8_UM_REV 1.00 9 I/O PORTS 9.1.1.1 Port 0 Port 0 is a 6-bit I/O port that you can use in two ways:  General-purpose I/O  Alternative function Port 0 is accessed directly by writing or reading the port 0 data register, P0, at location E0H, Set1 Bank0. 9.1.1.1.1 Port 0 Control Register (P0CONH, P0CONL) Port 0 pins are configured individually by setting bit-pair in two control registers located at P0CONH (high byte, E4H, Set1 Bank0) and P0CONL (low byte, E3H, Set1 Bank0).

  • Page 221: Figure 9-1 Port 0 Control Register High Byte (P0Conh)

    P0.5 /INT5 /INT3 /INT4 /TAOUT /PWM .7 -.6 bit Not used for S3F84B8 .5 .4 bit/P0.6/INT5/TAOUT Input mode/INT5 falling edge interrupt Input mode with pull -up/INT5 falling edge interrupt Push-pull output Alternative function : TAOUT .3 .2 bit/P0.5/INT4 Input mode/INT4 falling edge interrupt...

  • Page 222: Figure 9-2 Port 0 Control Register Low Byte (P0Conl)

    S3F84B8_UM_REV 1.00 9 I/O PORTS Port 0 Low Control Register (P0CONL) E4H, Set1, Bank0, R/W, Reset value:00H P0.3 P0.1 P0.0 Not Used /INT2 /INT1 /INT0 /BUZ .7 -.6 bit/P0.3/INT2/BUZ Input mode/INT2 falling edge interrupt Input mode with pull up /INT2 falling edge interrupt Push-pull output Alternative function : BUZ output .5 .4 bit Not used for S 3F84B8...

  • Page 223: Figure 9-3 Port 0 Interrupt Control Register (P0Int)

    E3H, Set1, Bank0, R/W, Reset value:00H INT5 INT4 INT3 INT2 INT1 INT0 used used .7 bit Not used for S3F84B8 bit INT5 Interrupt Enable/Disable Selection Interrupt disable Interrupt enable bit INT4 Interrupt Enable/Disable Selection Interrupt disable Interrupt enable bit INT3 Interrupt Enable/Disable Selection...

  • Page 224: Figure 9-4 Port 0 Interrupt Pending Register (P0Pnd)

    S3F84B8_UM_REV 1.00 9 I/O PORTS Port 0 Interrupt Pending Register (P0PND) E6H, Set1, Bank0, R/W, Reset value: 00H P0.0/ P0.1/ Not used INT0 INT1 P0.3/ P0.4/ INT2 P0.5/ INT3 P0.6/ Not used INT4 INT5 P0.n bit configuration settings: No interrupt pending (when read) Pending bit clear (when write) Interrupt is pending (when read) No effect (when write)

  • Page 225: Port 1

    S3F84B8_UM_REV 1.00 9 I/O PORTS 9.1.1.2 Port 1 Port 1 is a 3-bit I/O port that you can use in two ways:  General-purpose I/O  Alternative function Port 1 is accessed directly by writing or reading the port 1 data register, P1, at location E1H, Set1 Bank0. 9.1.1.2.1 Port 1 Control Register (P1CON) Port 1 pins are configured by setting the control registers located at P1CON (E7H, Set1 Bank0).
  • Page 226 S3F84B8_UM_REV 1.00 9 I/O PORTS Port 1 Control Register (P1CON) E7H, Set1, Bank0, R/W, Reset value:00H P1.0 P1.1 Not used P1.2 /CMP0_P /CMP0_N /CMP1_N /TACK /TACAP .5 .4 bit/P1.2/CMP1_N Input mode Input mode with pull up resistor Push-pull output Alternative function: CMP1 negative input .3 .2 bit/P1.1/CMP0_N_TACAP Input mode/TACAP input Input mode with pull-up/TACAP input...

  • Page 227: Port 2

    S3F84B8_UM_REV 1.00 9 I/O PORTS 9.1.1.3 Port 2 Port 2 is an 8-bit I/O port that you can use in two ways:  General-purpose I/O  Alternative function Port 2 is accessed directly by writing or reading the port 2 data register, P2, at location E2H, Set1 Bank0. 9.1.1.3.1 Port 2 Control Register (P2CONH, P2CONL) Port 2 pins are configured individually by setting bit-pair in two control registers located at P2CONL (low byte, E9H, Set1 Bank0) and P2CONH (high byte, E8H, Set1 Bank0).

  • Page 228: Figure 9-6 Port 2 High-Byte Control Register (P2Conh)

    S3F84B8_UM_REV 1.00 9 I/O PORTS Port 2 Control Register , High Byte (P2CONH) E8H, Set1, Bank0, R/W, Reset value:00H P2.5 P2.4 P2.7 P2.6 /ADC5 /ADC4 /ADC7 /ADC6 /CMP3_N /CMP2_N .7 .6 bit/P2.7/ADC7 Input mode Input mode with pull -up Push-pull output Alternative function : ADC7 input .5 .4 bit/P2.6/ADC6 Input mode...

  • Page 229: Figure 9-7 Port 2 Low-Byte Control Register (P2Conl)

    S3F84B8_UM_REV 1.00 9 I/O PORTS Port 2 Control Register, Low Byte (P2CONL) E8H, Set1, Bank0, R/W, Reset value:00H P2.1 P2.2 P2.0 P2.3 /ADC1 /ADC2 /ADC0 /ADC3(OA_O) /OA_P /OA_N /TDOUT .7 .6 bit/P2.3/ADC3(OA_O) Input mode Input mode with pull-up Push-pull output Alternative function: ADC3 input .5 .4 bit/P2.2/ADC2/OA_N Input mode...

  • Page 230: Basic Timer

    S3F84B8_UM_REV 1.00 10 BASIC TIMER BASIC TIMER 10.1 OVERVIEW OF BASIC TIMER You can use the basic timer (BT) in two different ways:  As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ...

  • Page 231: Basic Timer Control Register (Btcon)

    S3F84B8_UM_REV 1.00 10 BASIC TIMER 10.2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, selects the input clock frequency to clear the basic timer counter and frequency dividers and enable (or disable) the watchdog timer function. A reset clears BTCON to “00H”. This enables the watchdog function to select a basic timer clock frequency of /4096.

  • Page 232: Basic Timer Function Description

    S3F84B8_UM_REV 1.00 10 BASIC TIMER 10.2.1 BASIC TIMER FUNCTION DESCRIPTION 10.2.1.1 Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to “00H”, automatically enabling the watchdog timer function.

  • Page 233: Figure 10-2 Oscillation Stabilization Time On Reset

    S3F84B8_UM_REV 1.00 10 BASIC TIMER Oscillation Stabilization Time Normal Operating mode Reset Release Voltage nRESET trst ~ RC Internal Reset Release 0.8 VDD Oscillator (XOUT) Oscillator Stabilization Time BTCNT clock 10000B BTCNT value 00000B tWAIT = (4096x128)/fOSC Basic timer increment and CPU operations are IDLE mode NOTE: Duration of the oscillator stabilization wait time, tWAIT, when it is released by a Power-on-reset is 4096 x 128/fOSC.

  • Page 234: Figure 10-3 Oscillation Stabilization Time On Stop Mode Release

    S3F84B8_UM_REV 1.00 10 BASIC TIMER Normal STOP Mode Oscillation Stabilization Time Normal Operating Operating Mode Mode STOP Instruction STOP Mode Execution Release Signal External Interrupt RESET STOP Release Signal Oscillator (XOUT) BTCNT clock 10000B BTCNT 00000B Value tWAIT Basic Timer Increment NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by an interrupt is determined by the setting in basic timer control register, BTCON.
  • Page 235 S3F84B8_UM_REV 1.00 10 BASIC TIMER Example 10-1 Configuring the Basic Timer This example shows how to configure the basic timer to sample specification. 0000H ;--------------<< Smart Option >> 003CH 0FFH ; 003CH, must be initialized to 0FF 0FFH ; 003DH, must be initialized to 0FF 0FFH ;...

  • Page 236: Bit Timer A

    S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 8-BIT TIMER A 11.1 OVERVIEW OF 8-BIT TIMER A The 8-bit Timer A is a general-purpose timer/counter. It has three operating modes, and you can select one of the modes using the appropriate TACON setting. The three operating modes are: ...

  • Page 237: Functional Description

    S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11.1.1 FUNCTIONAL DESCRIPTION 11.1.1.1 Timer A Interrupts The Timer A module can generate two interrupts: Timer A overflow interrupt (TAOVF) and Timer A match/capture interrupt (TAINT). Timer A overflow interrupt (TAOVF) can be cleared by both software and hardware. On the other hand, Timer A match/capture interrupt (TAINT) pending conditions are cleared by software when it has been serviced.

  • Page 238: Timer A Control Register (Tacon)

    S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11.1.2 TIMER A CONTROL REGISTER (TACON) You can use the Timer A control register (TACON) for the following purposes:  Select the Timer A operating mode (interval timer, capture mode, and PWM mode)  Clear the Timer A counter (TACNT) ...
  • Page 239 S3F84B8_UM_REV 1.00 11 8-BIT TIMER A Timer A Control Register (TACON) E4H, Set1, Bank1, R/W, Reset: 00H Timer A OVF Interrupt pending bit: Timer A operating mode selection bit: 0 = No pending (clear pending bit when write ) 00 = Interval mode (TAOUT mode) 1 = Interrupt pending 01 = Capture mode (capture on rising edge, Timer A match Interrupt pending bit:...
  • Page 240 Timer A clock source selection bit TA CLK = fxx/(2^TAPSB) 0 = Internal clock source 1 = External clock source from TACK Not used for S3F84B8 NOTE: Prescaler values(TAPSB) above 12 are not valid. Figure 11-2 Timer A Prescaler Register (TAPS)

  • Page 241: Block Diagram Of Timer A

    S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11.1.3 BLOCK DIAGRAM OF TIMER A TACON.4 TAOVF Overflow TAPS.3-.0 TAPS.7 Pending Data Bus TACON.0 Clear TACON.5 prescaler 8-bit Up-Counter (Read Only) TACK TACON.3 Match TAINT 8-bit Comparator Pending TACON.1 TACAP TAOUT Timer A Buffer Reg Overflow In PWM mode High level when data >...

  • Page 242: Timer

    S3F84B8_UM_REV 1.00 12 TIMER 0 TIMER 0 12.1 ONE 16-BIT TIMER MODE (TIMER 0) The 16-bit Timer 0 is used in one 16-bit Timer mode or two 8-bit Timers mode. If TCCON.7 is set to “1”, Timer 0 is used as a 16-bit Timer. On the other hand, if TCCON.7 is set to “0”, Timer 0 is used as two 8-bit Timers. ...

  • Page 243: Functional Description Of One 16-Bit Timer Mode (Timer 0)

    S3F84B8_UM_REV 1.00 12 TIMER 0 12.1.2 FUNCTIONAL DESCRIPTION OF ONE 16-BIT TIMER MODE (TIMER 0) 12.1.2.1 Interval Timer Function Timer 0 module can generate Timer 0 match interrupt (TCINT). The TCINT pending bit will be set whenever the match condition is met, in spite of global interrupt and peripheral interrupt enable status. If this interrupt has been serviced, the TCINT pending condition should be cleared by the software.
  • Page 244 Reset Value: 00h Timer C prescaler bit (TCPSB) Timer C clock source selection bit TC CLK = fxx/(2^TCPSB) 0 = Internal clock source Not used for S3F84B8 1 = CMP0 output Pre-scalar values(TCPSB) above 12 are invalid NOTE: Figure 12-2...

  • Page 245: Block Diagram Of Timer 0

    S3F84B8_UM_REV 1.00 12 TIMER 0 12.1.3 BLOCK DIAGRAM OF TIMER 0 TCCON.5 TCPS.3-.0 TCCON.4 TCCNT TDCNT Prescaler CMP0 Match Comparator TCINT TCDATA TDDATA TCPS.7 TCCON.3 NOTE: When TCCON.7 is '1', one 16-bit Timer 0. Figure 12-3 Timer 0 Functional Block Diagram 12-4...

  • Page 246: Two 8-Bit Timers Mode (Timer C And D)

    S3F84B8_UM_REV 1.00 12 TIMER 0 12.2 TWO 8-BIT TIMERS MODE (TIMER C AND D) 12.2.1 OVERVIEW OF TWO 8-BIT TIMERS MODE (TIMER C AND D) Timers C and D are 8-bit general-purpose timers. Timer C works in the interval timer mode, while Timer D works in the interval timer and PWM modes by using the appropriate TCCON and TDCON setting, respectively.
  • Page 247 S3F84B8_UM_REV 1.00 12 TIMER 0 TCCON and TDCON are located in address E5H and E9H, Set1 Bank1, and are read/write addressable using register addressing mode. A reset clears TCCON to “00H”. This disables the Timer C interrupt. You can clear the Timer C counter at any time during normal operation by writing a “1”...

  • Page 248: Figure 12-5 Timer C Prescaler Register (Tcps)

    Timer C prescaler bit (TCPSB) Timer C clock source selection bit TC CLK = fxx/(2^TCPSB) 0 = Internal clock source Not used for S3F84B8 1 = CMP0 output NOTE: Pre-scalar values(TCPSB) above 12 are invalid Figure 12-5 Timer C Prescaler Register (TCPS)
  • Page 249 S3F84B8_UM_REV 1.00 12 TIMER 0 Timer B Control Register (TDCON) E9H, Set1, Bank1, Reset = 00H, R/W Timer D overflow interrupt pending bit Timer D operating mode selection bits: 0 = no interrupt pending 00 = Interval mode (clear pending bit when write) 01 = 6-bit PWM mode (OVF interrupt can occur) 1 = interrupt pending 10 = 7-bit PWM mode (OVF interrupt can occur)

  • Page 250: Functional Description Of Two 8-Bit Timers Mode (Timer C And D)

    S3F84B8_UM_REV 1.00 12 TIMER 0 12.2.3 FUNCTIONAL DESCRIPTION OF TWO 8-BIT TIMERS MODE (TIMER C AND D) 12.2.3.1 Interval Timer Function (Timers C and D) Timers C and D module can generate the Timer C match interrupt (TCINT) and Timer D match interrupt (TDINT). Timer C match interrupt pending condition (TCCON.1) and Timer D match interrupt pending condition (TDCON.1) must be cleared by the software in interrupt service routine by means of writing a “0”...

  • Page 251: Figure 12-8 Timers C And D Function Block Diagram

    S3F84B8_UM_REV 1.00 12 TIMER 0 TCCON.4 TCPS.3-.0 Clear TCCON.5 TCCNT Prescaler CMP0 Match Comparator TCINT TCDATA TCPS.7 TCCON.3 TDCON.2 TDOVF TDCON.3 Overflow TDDATA TDINT TDOUT Match Comparator TDPS.3-.0 P2.0 TDCNT Prescaler Clear TDCON.5 TDCON.7-.6 When TCCON.7 is '0', two 8-bit timer C/D (Interval mode). NOTE: Figure 12-8 Timers C and D Function Block Diagram...

  • Page 252: Pulse Width Modulation Mode (Timer D)

    S3F84B8_UM_REV 1.00 12 TIMER 0 12.2.3.2 Pulse Width Modulation Mode (Timer D) Pulse width modulation (PWM) mode allows you to program the width (duration) of pulse that is outputted at the TDOUT (P2.0) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to Timer D data register.

  • Page 253: A/D Converter

    S3F84B8_UM_REV 1.00 13 A/D CONVERTER A/D CONVERTER 13.1 OVERVIEW OF A/D CONVERTER The 10-bit analog-to-digital (A/D) converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. Analog input level must lie between the V and V values.

  • Page 254: Using A/D Pins For Standard Digital Input

    S3F84B8_UM_REV 1.00 13 A/D CONVERTER 13.1.1 USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module’s input pins are alternatively used as digital input in port2. 13.1.1.1 A/D Converter Control Register (ADCON) The A/D converter control register, ADCON, is located at FAH address. ADCON has five functions: ...

  • Page 255: Internal Reference Voltage Levels

    13.1.2 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The reference voltage is internally connected to VDD in S3F84B8. Thus, the analog input level must remain within the range of to V Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step.
  • Page 256 S3F84B8_UM_REV 1.00 13 A/D CONVERTER ADCON.0 50 ADC Clock Conversion Start . . . ADDATA Previous Valid ADDATAH (8-Bit) + ADDATAL (2-Bit) Value Data 40 Clock Set up time 10 clock Figure 13-4 A/D Converter Timing Diagram 13-4...

  • Page 257: Conversion Timing

    5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit). The ADC module then enters an Idle state. 6. The digital conversion result can now be read from ADDATAH and ADDATAL registers. Analog ADC0-ADC7 Input Pin S3F84B8 Figure 13-5 Recommended A/D Converter Circuit for Highest Absolute Accuracy 13-5...
  • Page 258 S3F84B8_UM_REV 1.00 13 A/D CONVERTER Example 13-1 Configuring A/D Converter ;-----------------<< Interrupt Vector Address >> VECTOR F0H, INT_ADC ;--------------<< Smart Option >> 003CH 0FFH ; 003CH, must be initialized to 1 0FFH ; 003DH, must be initialized to 1 0FFH ;...

  • Page 259: Comparator

    COMPARATOR 14.1 OVERVIEW OF COMPARATOR The S3F84B8 microcontroller has four comparators (Comparator 0, 1, 2, and 3). The operation of these four comparators is controlled by four registers, namely, CMP0CON, CMP1CON, CMP2CON, and CMP3CON. The interrupt control register (CMPINT) controls the interrupt mode of four comparators.

  • Page 260: Figure 14-2 Cmp Interrupt Mode Control Register (Cmpint)

    S3F84B8_UM_REV 1.00 14 COMPARATOR CMP0 Control Register (CMP0CON) EAH, Set1, Bank0, Reset = 02H, R/W Not used CMP0 interrupt pending bit: 0 = No interrupt pending CMP 0 output polarity select bit 0 = CMP0 output is not inverted (Clear pending bit when write) = Interrupt is pending 1 = CMP0 output is inverted CMP0 enable bit...
  • Page 261 S3F84B8_UM_REV 1.00 14 COMPARATOR 14.1.1.1.2 Block Diagram of Comparator 0 C0EN (CMP0CON.3) INT Enable (CMP0CON.2) Interrupt CTRL CMP0CON.0 CMP0_P Fosc CMP0 CMPINT.1-.0 CMP0_N CMP0CON.1 C0PLR (CMP0CON.4) NOTE: 1. Polarity selection bit (CMP 0CON .4) will not affect interrupt generation logic. 2.

  • Page 262: Comparator 1/2/3

    S3F84B8_UM_REV 1.00 14 COMPARATOR 14.1.1.2 Comparator 1/2/3 Comparator 1, 2, and 3 have the same structure. Their positive input is internally connected with reference voltage, programmable from 0.45VDD to 0.8VDD with the step length of 0.05VDD. The output (falling edge) of comparator 1, 2, and 3 can be configured to generate PWM hard lock trigger signal (PWMCCON.1–.2/.3-0.4/.5/.6 = 11) or soft lock trigger signal (PWMCCON.1–.2/.3–0.4/.5/.6 = 01).
  • Page 263 S3F84B8_UM_REV 1.00 14 COMPARATOR CMP1 Control Register (CMP1CON) EBH, Set1, Bank0, Reset = 02H, R/W CMP 1 reference level select bit CMP 1 interrupt pending bit: 000 = 0.45VDD 0 = No interrupt pending CMP 1 output polarity select bit 001 = 0.50VDD (Clear pending bit when write) 0 = CMP1 output is not inverted...

  • Page 264: Figure 14-7 Cmp Interrupt Mode Control Register (Cmpint)

    S3F84B8_UM_REV 1.00 14 COMPARATOR CMP3 Control Register (CMP3CON) EDH, Set1, Bank0, Reset = 02H, R/W CMP 3 reference level select bit CMP 3 interrupt pending bit: 000 = 0.45VDD 0 = No interrupt pending CMP 3 output polarity select bit 001 = 0.50VDD (Clear pending bit when write) 0 = CMP3 output is not inverted...
  • Page 265 S3F84B8_UM_REV 1.00 14 COMPARATOR 14.1.1.2.2 Block Diagram of Comparator 1/2/3 CMP1/2/3CON.7-.5 0.45 VDD C1/2/3EN (CMP1/2/3CON.3) 0.50 VDD INT Enable (CMP1/2/3CON.2) Interrupt 0.80 VDD CMP1/2/3CON.0 CTRL Fosc CMP1/2/3 CMPINT.3-.2/.5-.4/.7-.6 CMP0_N CMP1/2/3CON.1 C1/2/3PLR (CMP1/2/3CON.4) NOTE: 1. Polarity selection bit (CMP1/2/3CON.4) will not affect interrupt generation logic . 2.

  • Page 266: Operational Amplifier

    15 OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER 15.1 OVERVIEW OF OPERATIONAL AMPLIFIER The S3F84B8 microcontroller has an Operational Amplifier (OP AMP), which is controlled by a control register (OPACON). 15.1.1 FUNCTIONAL DESCRIPTION OF OPERATIONAL AMPLIFIER The OP AMP has two operation modes, namely, on chip mode and off chip mode.

  • Page 267: Opamp Control Register

    OPAMP operating mode select bit 0 = disbale OPAMP 0 = off chip mode 1 = enable OPAMP 1 = on chip mode Not used for S3F84B8 Figure 15-1 OPAMP Control Register (OPACON) 15.1.3 BLOCK DIAGRAM OF OPAMP OA_N ADC3(OA_O)

  • Page 268: Reference Circuit

    S3F84B8_UM_REV 1.00 15 OPERATIONAL AMPLIFIER 15.1.4 REFERENCE CIRCUIT C 1 102pF Rf 100K R1 10K OA_N ADC3(OA_O) C1 I02pF OPAMP OA_P CL I02pF NOTE: 1. R1 should be no less than 10K ohm 2. Decoupling CAP C1 is for better EFT performance Figure 15-3 OPAMP Application Reference Circuit @ Gain=10 15-3...

  • Page 269: Bit Ih-Pwm

    10-BIT IH-PWM 16.1 OVERVIEW OF 10-BIT IH-PWM The S3F84B8 microcontroller has a 10-bit IH-PWM circuit that can cooperate with the comparators. This circuit is exclusively designed for the IH cooker application. The operation of all PWM circuits is controlled by a control register (PWMCON). The linkage of comparators and PWM is controlled by another control register (PWMCCON).

  • Page 270: Functional Description Of 10-Bit Ih-Pwm

    S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16.2 FUNCTIONAL DESCRIPTION OF 10-BIT IH-PWM 16.2.1 PWM The 10-bit PWM circuit has the following components:  10-bit comparator circuit  10-bit counter  10-bit reference data registers (PWMDATAH/L)  10-bit preset PWM data registers (PWMPDATAH/L) ...

  • Page 271: Pwm Functional Description

    S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16.2.3 PWM FUNCTIONAL DESCRIPTION By disabling the linkage of CMPs and PWM (setting PWMCCON to ‘00H’), PWM module can work in normal 10-bit mode. PWM output will toggle either on PWM counter match or overflow. The output level can be set as inverted (PWMCON.5 = 1) or non-inverted (PWMCON.5 = 0).

  • Page 272: Pwm Control Register (Pwmcon)

    S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16.2.4 PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at register address EFH, Set 1, Bank 0. Bit settings in the PWMCON register control the following functions:  Selects the PWM counter clock ...

  • Page 273: Pwm Cmp Linkage Control Register (Pwmccon)

    S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16.2.5 PWM CMP LINKAGE CONTROL REGISTER (PWMCCON) The control register for linkage of CMP and PWM module, PWMCCON, is located at register address F0H, Set 1, Bank 0. Bit settings in the PWMCCON register control the linkage configuration of PWM CMP0, PWM CMP1, PWM CMP2, and PWM CMP3.

  • Page 274: Block Diagram Of Pwm Module

    S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16.2.6 BLOCK DIAGRAM OF PWM MODULE Hard Lock (anti-mis-trigger)PWMCON.2 PWMCON.7-.6 PWMCON.3 AMTDATA Match PWMCON.4 CMP0 OUT Overflow Enable fxx/64 CLR&ST 10-bit Up-Counter PWMCCON.1 Trigger Logic fxx/8 PWMCCON.0 (Read Only) PWMCON.1 fxx/2 PWMINT CLR&ST Pending 10-bit Comparator PWMCON.0 "1"...

  • Page 275: Figure 16-6 Example Of The Cooperation Of Pwm And Comparator 0_Delay Trigger

    S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM PWMCCON.1-.0 = 01 PWMCCON.1-.0 = 11(Delay trigger enable ) Delay time = 4/fpwmclk Delay trigger disable PWMDATA = 0x7 PWM CLK CMP0 OUTPUT 4/fpwmclk IGBT OFF IGBT OFF PWM OUTPUT PWMDATA PWMDATA IGBT ON IGBT ON 0 <...
  • Page 276 S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM Hard Lock trigger PWM LOCK IGBT OFF PWM OUTPUT IGBT ON NOTE: Because CMP1/2/3 is asynchronous, lock action happens immediately without any setting time . Figure 16-8 Example of the Cooperation of PWM and Comparator 1/2/3_ Hard Lock CMP 0 OUTPUT (SYN CMP) Soft Lock Trigger...

  • Page 277: Programmable Buzzer

    17 PROGRAMMABLE BUZZER PROGRAMMABLE BUZZER 17.1 OVERVIEW OF PROGRAMMABLE BUZZER The S3F84B8 microcontroller has a built-in programmable buzzer, whose operation is controlled by a single control register, BUZCON. 17.2 FUNCTIONAL DESCRIPTION OF PROGRAMMABLE BUZZER The buzzer’s output in S3F84B8 is a square wave with wide frequency range.

  • Page 278: Buz Frequency Table (@4Mhz)

    S3F84B8_UM_REV 1.00 17 PROGRAMMABLE BUZZER 17.2.2 BUZ FREQUENCY TABLE (@4MHZ) Table 17-1 Buzzer Frequency Table (@4MHz) BUZCON Output Frequency (kHz) BUZCON Output Frequency (kHz) .4–.0 .4–.0 f/16 f/32 f/64 f/128 f/16 f/32 f/64 f/128 3.906 1.953 0.977 0.488 7.813 3.906 1.953 0.977 4.032...
  • Page 279 S3F84B8_UM_REV 1.00 17 PROGRAMMABLE BUZZER BUZCON.7-.6 BUZCON.5 fosc/128 fosc/64 Clear 5-bit Up-Counter fosc/32 fosc/16 Match BUZOUT(P0.3) 5-bit Comparator CTRL BUZ Buffer Reg BUZCON.4-.0 (Read/Write) Data Bus Figure 17-2 BUZ Functional Block Diagram 17-3...

  • Page 280: Flash Mcu Rom

    FLASH MCU ROM 18.1 OVERVIEW OF FLASH MCU ROM The S3F84B8 single-chip CMOS microcontroller has an on-chip Flash MCU ROM that can be accessed by serial data format. NOTE: This section only discusses about the Tool Program Mode of Flash MCU ROM. For more details about the User Program Mode, refer to Chapter 19, “Embedded Flash Memory Interface”.
  • Page 281 The Vpp pin on socket board for OTP/MTP writer should be 11V. Therefore, this pin must not be directly connected to Vpp (12.5V) generated from some OTP/MTP writer. A specific adapter board for S3F84B8 must be used while using these OTP/MTP writers.

  • Page 282: Embedded Flash Memory Interface

    19.1.1 FLASH ROM CONFIGURATION The flash memory in S3F84B8 consists of 64 sectors. Each sector, in turn, consists of 128 bytes. So, the total size of flash memory is 12864 bytes (8KB). You can erase the flash memory by a sector unit at any time, and even write data into the flash memory by a byte unit at any time.

  • Page 283: User Program Mode

    This mode supports sector erase, byte programming, byte read, and protection mode (Hard Lock Protection). S3F84B8 has an internal pumping circuit to generate high voltage. Therefore, there is no need to supply high programming voltage to the Vpp (Test) pin. To program flash memory in this mode, several control registers are used.

  • Page 284: Flash Memory Control Registers (User Program Mode)

    0101 = Programming mode 1 = operation start 1010 = Erase mode 0110 = Hard lock mode (This bit will be automatically cleared just Others: not used for S3F84B8 after erase operation) Not used for S3F84B8 Figure 19-2 Flash Memory Control Register (FMCON) The bit 0 of FMCON register (FMCON.0) specifies a bit for the start of Erase and Hard Lock Protection operations.

  • Page 285: Flash Memory Sector Address Registers

    S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19.1.5.3 Flash Memory Sector Address Registers There are two sector address registers for erasing or programming flash memory, namely:  Flash Memory Sector Address Register Low Byte (FMSECL)  Flash Memory Sector Address Register High Byte (FMSECH) FMSECL indicates the low byte of sector address, whereas FMSECH indicates the high byte of sector address.

  • Page 286: Sector Erase

    User Program mode is a sector. The program memory of S3F84B8 (8KB flash memory) is divided into 64 sectors. Every sector has 128 byte size. If you want to program new data into flash memory, sector erase (128 bytes) is needed, even if the destination address was not written after the previous erase operation.

  • Page 287: Figure 19-7 Sector Erase Flowchart In User Program Mode

    ‘0’ to start operation ‘1’. This bit will be cleared automatically just after the erase operation is completed. In other words, when S3F84B8 is in a condition where Flash Memory User Programming Enable Bit is enabled and sector erase is started, the erase operation will start at the selected sector.
  • Page 288 S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE Example 19-1 Sector Erase Case 1. Erase one sector   ERASE_ONESECTOR: FMUSR,#0A5H ; Enables user program mode FMSECH,#04H ; Set sector address 0400H, sector 8, FMSECL,#00H ; among sector 0–32 FMCON,#10100001B ; Select erase mode enable and Start sector erase ERASE_STOP: FMUSR,#00H ;...

  • Page 289: Programming

    S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19.1.7 PROGRAMMING Flash memory is programmed in one-byte unit after sector erase. The write operation of programming is executed using the LDC instruction. Program Procedure in User Program Mode To program Flash memory in User Program mode, follow these steps: 1.

  • Page 290: Figure 19-8 Byte Program Flowchart In A User Program Mode

    S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE Start ; Select Bank1 FMSECH High Address of Sector FMSECL Low Address of Sector ; Set Secotr Base Address R(n) High Address to Write R(n+1) Low Address to Write ; Set Address and Data R(data) 8-bit Data FMUSR...

  • Page 291: Figure 19-9 Program Flowchart In A User Program Mode

    S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE Start ; Select Bank1 FMSECH High Address of Sector ; Set Secotr Base Address FMSECL Low Address of Sector R(n) High Address to Write ; Set Address and Data R(n+1) Low Address to Write R(data) 8-bit Data FMUSR...
  • Page 292 S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE Example 19-2 Programming Case1. 1-Byte Programming   WR_BYTE: ; Writes data “AAH” to destination address 0310H FMUSR,#0A5H ; Enables User Program mode FMCON,#01010000B ; Selects Programming mode FMSECH, #03H ; Sets the base address of sector (0300H) FMSECL, #00H R9,#0AAH ;...
  • Page 293 S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE NZ，WR_BYTE ; Checks whether the end address for programming reaches 0640H. FMUSR,#00H ; Disables User Program mode Case3. Programming to the flash memory space located in other sectors   WR_INSECTOR2: R0,#40H R1,#40H FMUSR,#0A5H ;...
  • Page 294 S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE FMSECH,#06H ; Sets the base address of sector located in target address to write data FMSECL,#00H ; Sector 12’s base address is 0600H R9,#0A3H ; Loads data “A3H” to write R10,#06H ; Loads flash memory upper address into upper register of pair working ;...

  • Page 295: Reading

    S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19.1.8 READING The read operation starts using the ‘LDC’ instruction. Program Procedure in User Program Mode 1. Load flash memory upper address into upper register of pair working register. 2. Load flash memory lower address into lower register of pair working register. 3.

  • Page 296: Hard Lock Protection

    S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19.1.9 HARD LOCK PROTECTION You can set Hard Lock Protection by writing ‘0110B’ in FMCON7–4. This function prevents data change in flash memory area. If this function is enabled, you cannot write or erase data in flash memory anymore. This protection can be released by chip erase in Tool Program mode.

  • Page 297: Low Voltage Reset

    The MCU provides a watchdog timer function to ensure recovery from software malfunction. If the watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated. S3F84B8 has a built-in low voltage reset (LVR) circuit that detects voltage drop of external V input level and prevents the MCU from malfunctioning whenever it encounters fluctuation in power level.
  • Page 298 S3F84B8_UM_REV 1.00 20 LOW VOLTAGE RESET Watchdog RESET External RESETB nRESET Longer than 10us Comparator When the V level is lower than V Longger than 1us Smart Option 3FH.7 NOTE: BGR is Band Gap reference voltage. Figure 20-1 Low Voltage Reset Circuit NOTE: To program the duration of the oscillation stabilization interval, set the basic timer control register, BTCON, before entering the Stop mode.

  • Page 299: Electrical Data

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA ELECTRICAL DATA 21.1 OVERVIEW OF ELECTRICAL DATA This section describes the electrical characteristics of S3F84B8 in the form of tables and graphs. The following information has been provided:  Absolute maximum ratings  DC electrical characteristics ...

  • Page 300: Table 21-1 Absolute Maximum Ratings

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-1 Absolute Maximum Ratings = 25C) Parameter Symbol Conditions Rating Unit Supply voltage – –0.3 to + 6.5 –0.3 to V + 0.3 Input voltage All ports –0.3 to V + 0.3 Output voltage All output ports Output current high One I/O pin is active...
  • Page 301 S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-2 DC Electrical Characteristics = –40C to + 85C, V = 1.8V to 5.5V) Parameter Symbol Conditions Minimum Typical Maximum Unit Operating Voltage Fmain = 0.4 – 2MHz – Fmain = 0.4 – 4MHz –...
  • Page 302 S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Parameter Symbol Conditions Minimum Typical Maximum Unit = 4.5 to 5.5V (LVR enabled) = – 40C ~ 85C NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads and ADC module.
  • Page 303 S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-4 Oscillator Characteristics = –40C to + 85C) Oscillator Clock Circuit Test Condition Minimum Typical Maximum Unit = 2.7 to 5.5V Main crystal or – ceramic (NOTE) – = 2.0 to 2.7V (NOTE) – = 1.8 to 2.0V = 2.7 to 5.5V External clock...
  • Page 304 S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-5 Oscillation Stabilization Time = –40°C to + 85°C, V = 1.8V to 5.5V) Oscillator Test Condition Minimum Typical Maximum Unit > 1.0MHz Main crystal – – stabilization time Main ceramic Oscillation stabilization is achieved when –...

  • Page 305: Figure 21-2 Operating Voltage Range @ External Clock

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA External Clock Frequency 10 MHz 8 MHz 4 MHz 3 MHz 2 MHz 1 MHz 400KHz Supply Voltage (V) Figure 21-2 Operating Voltage Range @ External clock A = 0.2 V B = 0.4 V C = 0.6 V D = 0.8 V 0.3 V...

  • Page 306: Figure 21-4 Stop Mode Release Timing When Initiated By A Reset

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-6 Data Retention Supply Voltage in Stop Mode = –40C to + 85C, V = 1.8V to 5.5V) Parameter Symbol Conditions Minimum Typical Maximum Unit Data retention Stop mode – DDDR supply voltage Stop mode; V = 1.8V Data retention –...

  • Page 307: Table 21-7 A/D Converter Electrical Characteristics

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-7 A/D Converter Electrical Characteristics = –40C to + 85C, V = 1.8V to 5.5V, V = 0V) Parameter Symbol Test Conditions Minimum Typical Maximum Unit Resolution – – 3 Total accuracy – – = 5.12V CPU clock = 10MHz = 0V...

  • Page 308: Table 21-8 Op Amp Electrical Characteristics

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-8 OP AMP Electrical Characteristics = –40C to + 85C, V = 2.0V to 5.5V) Parameter Symbol Conditions Minimum Typical Maximum Unit = 2.0V Input offset voltage – = 5.5V – –0.1 Input common-mode –...

  • Page 309: Table 21-11 Flash Memory Ac Electrical Characteristics

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA Table 21-10 LVR Circuit Characteristics = 25C, V = 1.8V to 5.5V) Parameter Symbol Conditions Minimum Typical Maximum Unit Low voltage reset – LVR,MAX (Reset when the voltage decreases ) LVR,MIN chip starts working when the voltage increases ) Figure 21-5 LVR Reset Timing Table 21-11...

  • Page 310: Figure 21-6 Circuit Diagram To Improve The Eft Characteristics

    S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA S3F84B8 To have better EFT performance , It is recommended to NOTE: 1. Add a 104 capacitor as close to the VDD pin as possible 2. Use 104,102 or 101 capacitor at all input pins, especially the anlog input pins...

  • Page 311: Development Tools

    TB84B8 is a specific target board for the development of application systems using S3F84B8. 22.1.2 PROGRAMMING SOCKET ADAPTER When you program S3F84B8’s flash memory by using an emulator or an OTP/MTP writer, you need a specific programming socket adapter for S3F84B8. 22-1...

  • Page 312: Development System Configuration

    S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22.2 DEVELOPMENT SYSTEM CONFIGURATION shows the Development System Configuration. Figure 22-1 IBM-PC AT or Compatible Emulator [ SK-1200(RS-232,USB ) or OPEN Ice I-500(RS-232) or RS-232C / USB OPENIce I-2000(RS-232,USB)] Target OTP/MTP Writer Block Application System RAM Break/Display Block Probe Adapter...

  • Page 313: Tb84B8 Target Board

    S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22.3 TB84B8 TARGET BOARD The TB84B8 target board is used for S3F84B8 microcontrollers. It is operated as a target CPU with emulator (OPENIce I-500/2000 or SK-1200). Figure 22-2 TB84B8 Target Board Configuration NOTE: TB84B8 should be supplied with 5V normally. Thus, the power supply from Emulator should be set to 5V for the target board operation.
  • Page 314 S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS Table 22-1 TB84B8 Components Mark Usage Description 100-cable interface Connect the emulator and TB84B8 20-cable interface Connect TB84B8 and user system 8- channel switch Smart Option configuration of S3E84B0 RESET Generate reset signal to S3E84B0 VCC, GND Power in Power supply for TB84B8...
  • Page 315 PWM Disable PWM keeps output as the emulator pauses (Default setting). PWM Enable PWM Disable S3E84B0 runs in the Main mode, similar to S3F84B8. The debug Main Mode interface is not available. EVA Mode S3E84B0 runs in the EVA mode (Default setting). While debugging Main Mode the program, set the jumper in this mode.
  • Page 316 S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS High (Default ) NOTE : 1. For EVA chip , smart option is determined by DIP switch not software. 2. Please keep the reserved bits as default value (high). Figure 22-3 DIP Switch for Smart Option ...

  • Page 317: Figure 22-5 S3F84B8 Probe Adapter For 20-Dip Package

    P2.1/ADC 1/OA _P (Top View ) TACK /CMP 0_P/P1.0 P2.0/ADC 0/TDOUT TACAP /CMP 0_N/P1.1 P1.2/CMP 1_N Figure 22-4 40-Pin Connector for TB84B8 Target Board Target System Target Cable for 20 - pin Connector Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package 22-7...

  • Page 318: Third Parties For Development Tools

     US-pro  GW-PRO2 (8-gang programmer) Development Tools Suppliers For buying these development tools, contact Samsung’s local sales offices or the third party tool suppliers directly. The contact information is provided below. 8-bit In-Circuit Emulator AIJI System OPENice - i500 ...

  • Page 319: Otp/Mtp Programmer (Writer)

    Fast programming speed (4Kbps)  Supports the following Samsung devices:  OTP/MTP/Flash MCU Low-cost  Supports NOR Flash memory (SST, Samsung)  Supports NAND Flash memory (SLC)  New devices will be supported just by adding device  files or upgrading the software.
  • Page 320 PC-based menu drives the software for simple  operation Fast program and verify time (OTP: 2Kbps, MTP:  10Kbps) Supports Samsung’s standard Hex or Intel’s Hex  format Driver software runs on various operating systems  (Windows 95/98/2000/XP) Supports full functions of OTP/MTP programmer ...

  • Page 321: Mechanical Data

    S3F84B8_UM_REV 1.00 23 MECHANICAL DATA MECHANICAL DATA 23.1 OVERVIEW OF MECHANICAL DATA S3F84B8 is available in a 20-pin DIP package (Samsung: 20-DIP-300A) and a 20-pin SOP package (Samsung: 20-SOP-375). show the 20-DIP-300A and 20-SOP-375 package dimensions, respectively. Figure 23-1 Figure 23-2...
  • Page 322 S3F84B8_UM_REV 1.00 23 MECHANICAL DATA 20-SOP-375 + 0.10 0.203 - 0.05 13.14 MAX 12.74 0.20 0.10 MAX 1.27 (0.66) + 0.10 0.40 - 0.05 Dimensions are in millimeters. NOTE: Figure 23-2 20-SOP-375 Package Dimensions 23-2...

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